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Messages from 32150

Article: 32150
Subject: Re: Virtex II multiplier question
From: Kolja Sulimma <kolja@sulimma.de>
Date: Sat, 16 Jun 2001 00:37:48 +0200
Links: << >>  << T >>  << A >>
>
>
> I was thinking of perhaps sacrificing a bit of precision by limiting
> filter coeffs to 18 bits, and then the FIR stage consists of a 24x18
> multiplier / adder, which could then be realised by a 18x18 cascaded
> with several 9x9's to get a 27x18 mult, and ignoring the last 3
> bits...

A 18x18 multiplier plus 6 adders would also give you a 24x18 multiplier.
But the ca. 150 extra LUTs per multiplier is just a little more than there
is available in a XC2V150.

But they are a lot faster than the hardware multipliers, so maybe you coud
double pump the adders ;-)

Kolja Sulimma



Article: 32151
Subject: Re: Virtex II multiplier question
From: Kolja Sulimma <kolja@sulimma.de>
Date: Sat, 16 Jun 2001 00:44:42 +0200
Links: << >>  << T >>  << A >>


Alistair Webb wrote:

> I have a question regarding the Virtex II on-chip multipliers:
>
> I would like to use the Virtex II to implement some long FIR filters
> (512 or 1024 taps) with 24 bit coefficients stored in block RAM (it's
> an audio application).
>
> From what I can gather in the data sheets, the dedicated mults can be
> configured either as 18x18, or possibly as multiple 9x9's.
>
> Cascading 4 mults gives me 36x36 which seems a bit wasteful of
> resources considering data is only 24 bits wide.
>
> How can I get the most efficienct use out of these embedded
> multipliers?  Since the data rate is slow (96kHz) I'll be using just a
> few multipliers per filter, with coeffs fetched sequentially from
> block RAM.

Aehh. I did not see this before, but maybe you should just be wasteful?
One multiplier at 100 MHz is sufficent for a 1024 Tap filter
So, if you use the 18x36 variant, you can implement 12 filters in a
XC2V250.

That's not enough? (1,2G MACs)

Kolja Sulimma



Article: 32152
Subject: Re: Virtex II multiplier question
From: awebb@clara.net (Alistair Webb)
Date: Fri, 15 Jun 2001 22:51:35 GMT
Links: << >>  << T >>  << A >>
That's a good suggestion too...  It doesn't have to be pretty, just
cheaper and smaller than a farm of DSPs.  Another nice point about
using the FPGA option is the possibility of embedding a micro and
AES-EBU Receiver/Transmitter logic in a spare corner of the device and
getting a true 'one chip' solution...

I'm hoping someone out there has experience with the embedded mults in
these devices (since they're there and may as well be used!)

But of course I'm more than willing to change plans if someone has a
better idea of how to use the Virtex2 resources.

- Alistair Webb.

On Sat, 16 Jun 2001 00:37:48 +0200, Kolja Sulimma <kolja@sulimma.de>
wrote:

>>
>>
>> I was thinking of perhaps sacrificing a bit of precision by limiting
>> filter coeffs to 18 bits, and then the FIR stage consists of a 24x18
>> multiplier / adder, which could then be realised by a 18x18 cascaded
>> with several 9x9's to get a 27x18 mult, and ignoring the last 3
>> bits...
>
>A 18x18 multiplier plus 6 adders would also give you a 24x18 multiplier.
>But the ca. 150 extra LUTs per multiplier is just a little more than there
>is available in a XC2V150.
>
>But they are a lot faster than the hardware multipliers, so maybe you coud
>double pump the adders ;-)
>
>Kolja Sulimma
>
>


Article: 32153
Subject: Re: Virtex II multiplier question
From: awebb@clara.net (Alistair Webb)
Date: Fri, 15 Jun 2001 22:58:01 GMT
Links: << >>  << T >>  << A >>
I just want to get a feel for how the embedded multipliers can be
'bolted together' on chip...

1.2G MACs is plenty of horsepower for my app, I just want to select
the smallest (cheapest!) device in the Virtex2 family that can do the
job, and have the ability to scale up to larger devices if the number
of filter channels increase...

FWIW, the application is multi-channel audio (scalable from 8 up to 48
channels) so getting 12 complete filters per FPGA is excellent and
should result in a very compact board.

regards,

Al.

On Sat, 16 Jun 2001 00:44:42 +0200, Kolja Sulimma <kolja@sulimma.de>
wrote:

>
>
>Alistair Webb wrote:
>
>> I have a question regarding the Virtex II on-chip multipliers:
>>
>> I would like to use the Virtex II to implement some long FIR filters
>> (512 or 1024 taps) with 24 bit coefficients stored in block RAM (it's
>> an audio application).
>>
>> From what I can gather in the data sheets, the dedicated mults can be
>> configured either as 18x18, or possibly as multiple 9x9's.
>>
>> Cascading 4 mults gives me 36x36 which seems a bit wasteful of
>> resources considering data is only 24 bits wide.
>>
>> How can I get the most efficienct use out of these embedded
>> multipliers?  Since the data rate is slow (96kHz) I'll be using just a
>> few multipliers per filter, with coeffs fetched sequentially from
>> block RAM.
>
>Aehh. I did not see this before, but maybe you should just be wasteful?
>One multiplier at 100 MHz is sufficent for a 1024 Tap filter
>So, if you use the 18x36 variant, you can implement 12 filters in a
>XC2V250.
>
>That's not enough? (1,2G MACs)
>
>Kolja Sulimma
>
>


Article: 32154
Subject: Re: Virtex II multiplier question
From: Ray Andraka <ray@andraka.com>
Date: Sat, 16 Jun 2001 01:12:35 GMT
Links: << >>  << T >>  << A >>
You can do partial products with the 18x18 multipliers.  No need to use 
multiple multipliers if your data rate supports using one sequentially 
(yours does).  You get an improvement in performance by using the 
multipliers as 12x12 instead of the full 18 bits. Use 4 clocks to do the 
multiply, then all you need is the multiplier and a scaling accumulator 
for each.  I don't have the numbers in front of me, but by using the 
pipeline register and only 12 bits you should get to, I 'm guessing, 
about 240 MHz max clock.  You are presumably storing the coefficients in 
block RAM.  Efficient storage (ie to keep coefficients in the RAM 
attached to a multiplier, means a maximum of 512 36 bit coefficients 
(read out 18 bits at a time) per multiplier. At a 96 Khz data rate and 
512 coefficients per multiplier, your system clock needs to be 196MHz. 
That is about what the performance of the pipelined 18x18 multiplier is, 
so there shouldn't be any problem getting it to work as a 12x12.  You 
should be able to fit 4 of these 512 tap filter segments in an XCV40 easily.






Alistair Webb wrote:

> I have a question regarding the Virtex II on-chip multipliers:
> 
> I would like to use the Virtex II to implement some long FIR filters
> (512 or 1024 taps) with 24 bit coefficients stored in block RAM (it's
> an audio application). 
> 
> From what I can gather in the data sheets, the dedicated mults can be
> configured either as 18x18, or possibly as multiple 9x9's.
> 
> Cascading 4 mults gives me 36x36 which seems a bit wasteful of
> resources considering data is only 24 bits wide.
> 
> How can I get the most efficienct use out of these embedded
> multipliers?  Since the data rate is slow (96kHz) I'll be using just a
> few multipliers per filter, with coeffs fetched sequentially from
> block RAM.
> 
> I was thinking of perhaps sacrificing a bit of precision by limiting
> filter coeffs to 18 bits, and then the FIR stage consists of a 24x18
> multiplier / adder, which could then be realised by a 18x18 cascaded
> with several 9x9's to get a 27x18 mult, and ignoring the last 3
> bits...
> 
> All suggestions welcome!  I would really like to keep all filter
> coeffs on-chip as this cuts down the overall cost and need for
> external I/O.
> 
> Maybe someone at Xilinx would care to comment?
> 
> regards,
> 
> Alistair Webb.
> 
> p.s:  Will probably be targetting the XC2V250 device. What is the
> target price for this device and when will it be available?  Until
> then I may prototype on the smaller XC2V40 part and scale up later...


Article: 32155
Subject: Re: From EDF to VHDL?
From: hamish@cloud.net.au
Date: Sat, 16 Jun 2001 02:37:01 GMT
Links: << >>  << T >>  << A >>
Ulises Hernandez <ulisesh@ecs-telecom.removeplease.co.uk.invalid> wrote:
> for the build process, we will probably migrate this design to the Spartan
> II family. But my personal challenge will be to pass them to VHDL. It is a
> nightmare I know, os I would like to know if someone knows some software to
> convert to VHDL a EDF file o convert to VHDL a schematic using Mentor tools.

If you have the original schematics then you should be able to write
out VHDL from Mentor.. within Design Architect I think..
Of course your VHDL will be full of gate instantiations from the
unified Xilinx library.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 32156
Subject: Re: efficient CAM in Virtex or Spartan II?
From: "Peter Ormsby" <faepetedeletethis@mediaone.net>
Date: Sat, 16 Jun 2001 03:31:04 GMT
Links: << >>  << T >>  << A >>
For what it's worth...

If you want small, fast CAMs, the Altera APEX devices are really a much
better choice than the Spartan II or Virtex parts.  Since the memory blocks
have built-in dedicated hardware for implementing CAMs, you get much higher
performance without much hassle.

Just a suggestion.

-Pete-



Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message
news:qhvglxv8kx.fsf@ruckus.brouhaha.com...
> Is there any particularly efficient way to implement a small fast CAM,
> perhaps eight entries, in a Xilinx Virtex or Spartan II FPGA?
>
> The obvious approach is to use eight registers, eight comparators, and
> an eight-input priority encoder.  This uses a lot of CLBs.
>
> The slower approach is to use a RAM, a single comparator, and have a
> counter cycle through the addresses.  But I think this is too slow for
> my current needs.
>
> But is there another approach that I've overlooked?
>
> Thanks!
> Eric Smith



Article: 32157
Subject: Long interconnect in FPGA
From: Kuan Zhou <zhouk@rpi.edu>
Date: Fri, 15 Jun 2001 23:55:16 -0400
Links: << >>  << T >>  << A >>
Hi
   How can you solve the long interconnect problem in 
FPGA?
   When you have a lot of CLBs and they share the global
clock signal,how can you avoid the long interconnect delay
among CLBs?
   Any guy who can give a suggestion?

sincerely
-------------
Kuan Zhou
ECSE department



Article: 32158
Subject: Re: Virtex II multiplier question
From: rotemg@mysticom.com (Rotem Gazit)
Date: 16 Jun 2001 04:59:54 -0700
Links: << >>  << T >>  << A >>
I agree with Ray.
For more information on how to implement such a sequential filter have
a look at my article " Create Efficient FIR Filters Using Virtex and
Spartan FPGAs"  (Xcell Journal 38 Q4 2000).
www.xilinx.com/xcell/xl38/xcell38_32.pdf 

Regards,

Rotem Gazit
MystiCom LTD
rotemg@mysticom.com
http://www.mysticom.com/



Ray Andraka <ray@andraka.com> wrote in message news:<3B2AB26A.3080704@andraka.com>...
> You can do partial products with the 18x18 multipliers.  No need to use 
> multiple multipliers if your data rate supports using one sequentially 
> (yours does).  You get an improvement in performance by using the 
> multipliers as 12x12 instead of the full 18 bits. Use 4 clocks to do the 
> multiply, then all you need is the multiplier and a scaling accumulator 
> for each.  I don't have the numbers in front of me, but by using the 
> pipeline register and only 12 bits you should get to, I 'm guessing, 
> about 240 MHz max clock.  You are presumably storing the coefficients in 
> block RAM.  Efficient storage (ie to keep coefficients in the RAM 
> attached to a multiplier, means a maximum of 512 36 bit coefficients 
> (read out 18 bits at a time) per multiplier. At a 96 Khz data rate and 
> 512 coefficients per multiplier, your system clock needs to be 196MHz. 
> That is about what the performance of the pipelined 18x18 multiplier is, 
> so there shouldn't be any problem getting it to work as a 12x12.  You 
> should be able to fit 4 of these 512 tap filter segments in an XCV40 easily.
> 
> 
> 
> 
> 
> 
> Alistair Webb wrote:
> 
> > I have a question regarding the Virtex II on-chip multipliers:
> > 
> > I would like to use the Virtex II to implement some long FIR filters
> > (512 or 1024 taps) with 24 bit coefficients stored in block RAM (it's
> > an audio application). 
> > 
> > From what I can gather in the data sheets, the dedicated mults can be
> > configured either as 18x18, or possibly as multiple 9x9's.
> > 
> > Cascading 4 mults gives me 36x36 which seems a bit wasteful of
> > resources considering data is only 24 bits wide.
> > 
> > How can I get the most efficienct use out of these embedded
> > multipliers?  Since the data rate is slow (96kHz) I'll be using just a
> > few multipliers per filter, with coeffs fetched sequentially from
> > block RAM.
> > 
> > I was thinking of perhaps sacrificing a bit of precision by limiting
> > filter coeffs to 18 bits, and then the FIR stage consists of a 24x18
> > multiplier / adder, which could then be realised by a 18x18 cascaded
> > with several 9x9's to get a 27x18 mult, and ignoring the last 3
> > bits...
> > 
> > All suggestions welcome!  I would really like to keep all filter
> > coeffs on-chip as this cuts down the overall cost and need for
> > external I/O.
> > 
> > Maybe someone at Xilinx would care to comment?
> > 
> > regards,
> > 
> > Alistair Webb.
> > 
> > p.s:  Will probably be targetting the XC2V250 device. What is the
> > target price for this device and when will it be available?  Until
> > then I may prototype on the smaller XC2V40 part and scale up later...

Article: 32159
Subject: Re: Pin locking in Maxplus2
From: bob elkind <eteam@aracnet.com>
Date: Sat, 16 Jun 2001 05:13:54 -0700
Links: << >>  << T >>  << A >>
To follow up on this thread, in case anyone out there is watching...

Russell Shaw sent me his .ACF (constraints) and .TDF (source code) files.
They compiled just fine on my machine.

Possibilities:

corrupted MAX+2 install
something "different" in the international version (if any) of MAX+2
??

-- Bob Elkind, the e-team -- fpga/design consulting

bob elkind wrote:

> Russell,
>
> I've not installed *any* patches to Max+2 10.0.
>
> We could be here forever.  Why don't you just email me your .ACF file and
> your .TDF file(s).  I'll see if it compiles on my machine.  If it does compile,
> then you may want to re-install MAX+2 without any patches, see if it runs,
> then install a patch and see if it still runs, etc. etc.
>
> -- Bob Elkind, the e-team, fpga/design consulting.
>
> Russell Shaw wrote:
>
> > Hi B.E,
> >
> > I checked all the settings from your report file, and they seem to be
> > the defaults that match what i used. I've reinstalled maxplus2 and the
> > patch, but that didn't fix it.
> >
> > Do you have just the 10.0-10.01 patch applied, or are there other
> > patches?
> > TIA


Article: 32160
(removed)


Article: 32161
Subject: CFP: CASES 2001
From: kenmac@cc.gatech.edu (Kenneth M. Mackenzie)
Date: 17 Jun 2001 03:45:53 -0400
Links: << >>  << T >>  << A >>

                         CALL FOR PAPERS

                           CASES 2001
                  International Conference on
     Compilers, Architectures and Synthesis for Embedded Systems

           http://www.crest.gatech.edu/conferences/CASES2001

                       November 16-17, 2001
                        Grand Hyatt Atlanta
                         Altanta, GA, USA

                Submission deadline: August 10, 2001

CONFERENCE OBJECTIVES

Time-to-market has become a crucial objective to embedded system
designers in the context of enabling technologies such as compilation,
novel architectures, synthesis, reconfigurable hardware and others.
In these contexts, much of the successful research so far has been
performed in increasingly specialized research areas localized into
``communities'' working in vertically integrated fields.  This working
conference, the fourth in the CASES series, will provide a common
forum for researchers from the computer engineering and science
disciplines with an interest in embedded systems to reach across such
vertically integrated communities and to promote potential synergies.

As evident from the past CASES meetings, several of the emerging
application areas are critically dependent on these interactions for
their sustained growth and evolution.  Application areas that embody
application-specific embedded computing include set-top boxes,
hand-held games, mobile and web appliances, advanced automotive
systems, high-performance networking and others.  For these areas to
thrive, new technologies must address constraints on cost, code size,
weight, power consumption and real-time response as well as
performance.  Concerns of time-to-market are a dominant but not
exclusive theme of the conference.

Technical as well as position papers espousing significant novel ideas
and technical results are solicited.  Conference topics include (but
are not limited to) the following:

     * Novel architectures and micro-architectures.
     * New optimizing compilers for embedded-domain constraints.
     * Automated design and synthesis of application- or domain-
       specific processors.
     * Application- or domain-specific embedded system designs
     * Light-weight languages for temporal specification.
     * Synergy between extant parallel computing technologies, such as
       notations for expressing concurrency, and instruction level 
       parallel processing.
     * Reconfigurable or adaptive computing systems.
     * Compiler controlled memory hierarchy management and smart caches.
     * System-on-a-Chip architectures/compilers and embedded software
       including heterogeneous multiprocessor embedded systems.
     * Research infrastructure development for embedded systems.
     * Emerging domains including micro-UAVs and textiles.

CONFERENCE HIGHLIGHTS
 
    * KEYNOTE LECTURES:
 
        Alberto Sangiovanni-Vincentelli, University of California at
        Berkeley and Cadence Design Systems

        Tom Adelmeyer, Intel Corporation

    * PANEL:

        Personal, Handheld, Wireless: The Future of Digital Technology

    * SPECIAL SESSION:

        E-Textiles

INFORMATION FOR AUTHORS:

Please submit either one electronic copy of the paper in postscript
format to the following email address, or FIVE hard copies to the
program chair at the address given below.  There is no page limit, but
the paper must not exceed 4000 words in length.  The proceedings will
be published by ACM Press.  All papers must be submitted in the ACM
format as specified at http://www.acm.org/sigs/pubs/proceed/template.html

E-mail address for submission: CASES@capsl.udel.edu

Mail address for submission:

    CASES 2001
    c/o Prof. Guang R. Gao
    104 Evans Hall
    University of Delaware
    Newark, DE  19716
    USA

IMPORTANT DATES:

    Papers due:  August 10, 2001
    Author notification: September 5, 2001
    Camera ready copy due: October 5, 2001

ORGANIZING COMMITTEE

    Steering Committee:

        James R. Boddie, Lucent Technologies
        Vinod Kathail, Hewlett-Packard Labs
        Edward Lee, University of California Berkeley
        Reid Tatge, Texas Instruments

    General Chair:

        Krishna V. Palem, Georgia Institute of Technology

    Program Co-Chairs:

        Guang R. Gao, University of Delaware
        Trevor Mudge, University of Michigan

    Local Arrangements Vice-Chair:

        Wei Zhao, StarCore, Agere Systems

    Coordination Vice-Chair

        Shuvra S. Bhattacharyya, University of Maryland

    Panel Vice-Chair:

        Rob Schreiber, HP Labs

    Publications Vice-Chair:

        Jack Davidson, University of Virginia

    Publicity Vice-Chair:

        Kenneth Mackenzie, Georgia Institute of Technology

    Program Committee:

        Todd Austin, University of Michigan
        Prithviraj Banerjee, Northwestern University
        George Cai, Intel
        Josh Fisher, Hewlett-Packard Labs
        Mark Franklin, Washington University
        Thomas Gross, Carnegie Mellon University
        Mary Jane Irwin, Pennsylvania State University
        Bruce Jacob, University of Maryland
        Jaime Moreno, IBM T.J. Watson Research Center
        Mateo Valero, UPC Spain
        Paul Webster, AT&T Research Labs
        Wayne Wolf, Princeton University
        Weng-Fai Wong, National University of Singapore

IN THE NEWS

  EE Times covers papers from last year's CASES 2000:

        http://www.eet.com/story/OEG20010216S0024

Article: 32162
Subject: Re: Pin locking in Maxplus2
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Sun, 17 Jun 2001 02:13:53 -0700
Links: << >>  << T >>  << A >>
To follow up more, i just deleted the total win95B installation and
re-installed. Then re-installed maxplus2 over the old version. Still
get the same error, with and without the latest patch. Is it the pc
hardware, or win95B?


bob elkind wrote:
> 
> To follow up on this thread, in case anyone out there is watching...
> 
> Russell Shaw sent me his .ACF (constraints) and .TDF (source code) files.
> They compiled just fine on my machine.
> 
> Possibilities:
> 
> corrupted MAX+2 install
> something "different" in the international version (if any) of MAX+2
> ??
> 
> -- Bob Elkind, the e-team -- fpga/design consulting
> 
> bob elkind wrote:
> 
> > Russell,
> >
> > I've not installed *any* patches to Max+2 10.0.
> >
> > We could be here forever.  Why don't you just email me your .ACF file and
> > your .TDF file(s).  I'll see if it compiles on my machine.  If it does compile,
> > then you may want to re-install MAX+2 without any patches, see if it runs,
> > then install a patch and see if it still runs, etc. etc.
> >
> > -- Bob Elkind, the e-team, fpga/design consulting.
> >
> > Russell Shaw wrote:
> >
> > > Hi B.E,
> > >
> > > I checked all the settings from your report file, and they seem to be
> > > the defaults that match what i used. I've reinstalled maxplus2 and the
> > > patch, but that didn't fix it.
> > >
> > > Do you have just the 10.0-10.01 patch applied, or are there other
> > > patches?
> > > TIA

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 32163
Subject: Xilinx web site ?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 17 Jun 2001 17:00:52 +0100
Links: << >>  << T >>  << A >>
The Xilinx web site seems to have gone very erratic recently with
constant remote server end disconnections.

Is just my setup or has anybody else experienced this ?




Article: 32164
Subject: How to connect mp3 player with a hard disk
From: jlts@hotmail.com (jason lim)
Date: 17 Jun 2001 11:25:57 -0700
Links: << >>  << T >>  << A >>
I am using a mp3 player that use Actel&#8217;s A40MX04 FPGA.
I final year engineering student. And FPGA is very new for me. 
I would to know is there any posibilities to connect it to hard disk,
so that i could store the mp3 file inside it?

Article: 32165
Subject: Re: Xilinx web site ?
From: "david garnett" <dave.garnett@metapurple.co.uk>
Date: Sun, 17 Jun 2001 20:51:07 +0100
Links: << >>  << T >>  << A >>
Yes, I've been unable to download succesfully the latest WebPack stuff due
to apparently random disconnects ...
Dave

"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
news:3B2CD434.12C80AD8@algor.co.uk...
> The Xilinx web site seems to have gone very erratic recently with
> constant remote server end disconnections.
>
> Is just my setup or has anybody else experienced this ?
>
>
>



Article: 32166
Subject: PCI Config Address Space
From: Mario <Mario.Heike.Niklas@t-online.de>
Date: Sun, 17 Jun 2001 22:37:56 +0200
Links: << >>  << T >>  << A >>
Hello,
How can I access on the PCI Configuration Address Space ?
Is it right, that i can do it over the I/O Ports 0CF8h an d0CFAh ?
Can i do it over a Softwareinterface of the BIOS ?
And can i do it with the buscommands C/BE from the PCI Bus ?

Thanks !
Mario


Article: 32167
Subject: Re: Xilinx web site ?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 18 Jun 2001 00:14:22 +0100
Links: << >>  << T >>  << A >>


david garnett wrote:

> Yes, I've been unable to download succesfully the latest WebPack stuff due
> to apparently random disconnects ...
> Dave
>

It took me 4 attempts this afternoon to download the latest v1.5 Virtex2 info.

What's your setup ? I'm on a 128K ISDN from my home to the office web-cache &
from there out on a dedicated 128K line from NTL [the office is just down the
road from the NTL building].

Maybe its just us second class citizens in the UK.

Xilinx: Are you listening ?




Article: 32168
Subject: Re: Xilinx web site ?
From: Peter Alfke <palfke@earthlink.net>
Date: Mon, 18 Jun 2001 03:37:26 GMT
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:

Xilinx: Are you listening ?

Listening, yes. But it's Sunday today ( "Father's Day" to boot )
Let's see on Monday.

Peter Alfke, from home.



Article: 32169
Subject: Verilog or VHDL?
From: "Ralph Mason" <masonralph@yahoo.com>
Date: Mon, 18 Jun 2001 16:27:10 +1200
Links: << >>  << T >>  << A >>
As an absolute beginner I am wondering which language is better to start
with VHDL or Verilog?

I have done a very small CPLD with VHDL some time ago but that was more a
case of a need for a quick solution rather than a desire to learn.

Any input is appreciated.

Thanks




Article: 32170
Subject: Verilog FAQ : Jun 17, 2001
From: rajesh52@hotmail.com (Rajesh Bawankule)
Date: 17 Jun 2001 22:51:00 -0700
Links: << >>  << T >>  << A >>
Greetings
This is semimonthly announcement of Verilog FAQ.

Verilog FAQ is located at
<http://www.parmita.com/verilogfaq/>

Alternate Verilog FAQ is an attempt to gather the answers
to most Frequently Asked Questions about Verilog HDL in
one place. It also  contains list of publications, services,
and products.

Alternate Verilog FAQ is divided into three logical parts.

Part 1 : Introduction and misc. questions
Part 2 : Technical Topics
Part 3 : Tools and Services

What's New section outlines the changes in different versions
and announcements. Links connects you to related
informative links in internet.

Your suggestions to make this FAQ more informative are
welcome.

Rajesh Bawankule
(Also Visit Chip-Guru : http://www.chip-guru.com/ )

Article: 32171
Subject: Re: Teramac FPGA mapping for Pentium
From: Srinivasan Venkataramanan <srini@realchip.co.in>
Date: Mon, 18 Jun 2001 13:41:12 +0530
Links: << >>  << T >>  << A >>
Hi Harsha,
	As such Intel doesn't let the complete detailed  design available
outside. But there is an excellent book that tries to string the bits
and pieces available and tries to give a overall design picture. It is
entitled:


Pentium® Pro and Pentium II Processor System Architecture, 

checkout:

http://www.mindshare.com/books/books_main.html

I have this book (they also have a Pentium architecture book, I
believe) though haven't read it in full - yesterday I checked out the
hardware section and looks pretty detailed - I guess that should get
you started atleast. See if it helps you.

Good Luck,
Srini

Harsha Gordhan Jagasia wrote:
> 
> Hi,
> I am a master's student at Michigan State University.
> I am trying to map the Pentium units onto the Teramac FPGA's.
> Is there some way to know the digital design of certain units of the
> Pentium (say the
> Intruction Decoder) in order to estimate how the functionality of the same
> can de
> implemented using Teramac's Look up tables.
> In other words how many bytes would the Instruction decoder and other
> units
> require?
> Would appreciate any tips!
> Thanks
> Harsha jagasia
> jagasiah@cse.msu.edu

-- 
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India

Article: 32172
Subject: Re: On the prices of the FPGA and how to buy it
From: "Julián Calderón Almendros" <jcalderon@ctima.uma.es>
Date: Mon, 18 Jun 2001 10:29:38 +0200
Links: << >>  << T >>  << A >>
Thanks to all for the recomendations.



Article: 32173
Subject: Re: PCI Config Address Space
From: Thomas Zipper <Thomas.Zipper@icn.siemens.de>
Date: Mon, 18 Jun 2001 10:49:14 +0200
Links: << >>  << T >>  << A >>
Config Space Access:
 - IDSEL of the device must be asserted
 - right command on cbe
 - right function number
 - no address parity error (device specific)
 - type 0 access (2 lsbits must be 0)

Accessing the Config Space via the IO Space: that might be a device
specific "feature". I'm pretty sure that there is nothing like that
defined in the PCI Spec.

There is a mail-reflector for PCI related questions. To subscribe read
the instructions given at http://www.pcisig.com -> Tech-Support ->
Forum.

Thomas

Mario wrote:

> Hello,
> How can I access on the PCI Configuration Address Space ?
> Is it right, that i can do it over the I/O Ports 0CF8h an d0CFAh ?
> Can i do it over a Softwareinterface of the BIOS ?
> And can i do it with the buscommands C/BE from the PCI Bus ?
>
> Thanks !
> Mario


Article: 32174
Subject: Re: Xilinx web site ?
From: "david garnett" <dave.garnett@metapurple.co.uk>
Date: Mon, 18 Jun 2001 10:27:04 +0100
Links: << >>  << T >>  << A >>
I have a BT ISDN line into Pipex, so not too many common factors there -
looks like the problem is over there ...
Dave

"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
news:3B2D39CE.9860E08D@algor.co.uk...
>
>
> david garnett wrote:
>
> > Yes, I've been unable to download succesfully the latest WebPack stuff
due
> > to apparently random disconnects ...
> > Dave
> >
>
> It took me 4 attempts this afternoon to download the latest v1.5 Virtex2
info.
>
> What's your setup ? I'm on a 128K ISDN from my home to the office
web-cache &
> from there out on a dedicated 128K line from NTL [the office is just down
the
> road from the NTL building].
>
> Maybe its just us second class citizens in the UK.
>
> Xilinx: Are you listening ?
>
>
>





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