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Messages from 32225

Article: 32225
Subject: LVDS questions
From: Michiel De Wilde <michiel.dewilde@rug.ac.be>
Date: Wed, 20 Jun 2001 15:49:46 +0200
Links: << >>  << T >>  << A >>
Hi, here's a question from a CE from Ghent University, Belgium:

I wonder if someone can give me an estimate on

* the dimensions of a single LVDS (Low-Voltage Differential Signaling) 
driver/receiver (e.g. in CMOS .25um technology) (e.g. typical dimensions of 
circuitry and pads)
* propagation time from when a signal transition enters a LVDS driver until 
it exits the receiver side, under different wirelengths (loads) at any 
operating frequency in the 0.5GHz-1.5GHz range.
* the power dissipation of a single LVDS driver/receiver at any load and 
operating frequency in the 0.5GHz-1.5GHz range.

(Since newer Xilinx and Altera FPGA's include LVDS interconnect support I 
also posted this on an FPGA newsgroup, so don't be mad at me)

(Partial) answers are much appreciated (but please remove the 
pleaseremovethis when replying),

Michiel De Wilde

Article: 32226
Subject: Re: Timing results Xilinx Core Multiplier in FPGA Compiler 2
From: Andreas Purde <purde@emt.ei.tum.de>
Date: Wed, 20 Jun 2001 14:57:05 +0100
Links: << >>  << T >>  << A >>
The problem was caused by FC2 v3.4. The newer versions 3.5.2 and 3.6 show
the right results.

Andreas

Andreas Purde wrote:

> Hi,
>
> I just compiled a pipelined multiplier (Variable Parallel Virtex
> Multiplier v1.0.2) out of the Xilinx CoreGen with FPGA Compiler 2
> (v3.4). According to the Xilinx Data Sheet it can do up to 143MHz for a
> 16x16 multiplication - the FPGA compiler reports a maximum frequency of
> 26MHz (more than 5 times less).
>
> Any ideas on what I'm doing wrong there?
>
> Thanks,
>
> Andreas


Article: 32227
Subject: Re: Gray counter STRUCTURAL (VHDL)
From: bob elkind <eteam@aracnet.com>
Date: Wed, 20 Jun 2001 09:08:38 -0700
Links: << >>  << T >>  << A >>
There was an extended discussion of grey code counters on this newsgroup
a few months ago.  Several folks posted HDL code for implementing grey
code counters (myself included).

Search the usenet archives for this material (using google/dejanews).

Regards,

Bob Elkind, fpga design/consulting
www.aracnet.com/~eteam

Nikiforakis Manos wrote:

> Hello All.Can anyone please give me a hint on how am I going to desigh a gray code counder (stuctural description)?I've tried using T and D
> flip flops with the equations I got from Carneaut's maps but when I wrote the VHDL model either it falt in loops or it didn't worked at all
> (probably because of multiple feedbacks).I cannot find out what's happening and I cannot find even one model in the internet using styctural
> description for more than 2 bits!I will design (hopefully) a 16 bit counter but any help regarding to a  >2,3bit counter would be what I need
> to start.Thank you in advance. Nikiforakis ManosStuding Physics at Aristotle UniversityThessaloniki, Greeceemail: manolios@auth.gr


Article: 32228
(removed)


Article: 32229
Subject: Re: ee
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 20 Jun 2001 12:51:29 -0400
Links: << >>  << T >>  << A >>
Srinivasan Venkataramanan wrote:
> 
> Hi,
>   Check out User manual of VCS (if you already have it), here is an
> extract:
> 
> VCS and VCSi are identical except that VCS is more highly optimized,
> resulting in
> greater speed for RTL and mixed level designs. Pure gate level designs
> run with
> comparable speed. VCS and VCSi are guaranteed to provide the exact
> same
> simulation results. VCSi implementation requirements are summarized in
> the
> following:
> 1. VCSi is invoked using the vcsi command instead of vcs.
> 2. VCSi uses the VCSI_HOME environment variable instead of VCS_HOME.

I will tell you how they can guarantee that the two simulators produce
the same simulation results. They are the same simulator. 

Think about it. Why would they maintain TWO bodies of code when they can
maintain just one and use some very simple software tricks (wait loops
or slow bus accesses) to slow down the less expensive version. By
maintaining two bodies of code, they would increase their cost and
reduce their income (by selling the cheaper version vs. the more
expensive). 

So don't ever think that when a SW vendor sells two or more versions of
their code with nearly identical functionality, that they are offering
two different products. That is not cost effective. They are selling the
same code in each case with some features crippled in the less expensive
version. 

This is very different from one version being "more highly optimized".
That is what they want you to think so that you will not mind paying a
lot more to remove the cripple. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 32230
Subject: Re: FPGA Boards
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 20 Jun 2001 12:54:34 -0400
Links: << >>  << T >>  << A >>
Lewis wrote:
> 
> Philip Freidin <philip@fliptronics.com> wrote in message news:<cslsit4cln0eeiv2rmrncf357c1rq2cvmq@4ax.com>...
> > Try
> >     http://www.optimagic.com/boards.html
> >
> > I also tried "FPGA development boards" with altavista and it seemed
> > to be reasonable. (without the quotes)
> >
> >
> > On 18 Jun 2001 03:13:00 -0700, eng_any@yahoo.com (Lewis) wrote:
> > >I did a search for FPGA development boards and found that all roads
> > >lead to Nallatech through hidden keywords with the names of their
> > >competitors. Is this a good way to do business ?
> > >
> > >I though "passing off" was a thing of the past and these days the
> > >realm of the sex web site.
> > >
> > >Lew
> >
> > Philip Freidin
> > Fliptronics
> 
> Thanks
> 
> L

I did the same thing and found a lot of unique hits in Yahoo!. Where did
you do your search? You should have found APS, they offer a lot of FPGA
boards. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 32231
Subject: Re: Verilog or VHDL?
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 20 Jun 2001 13:03:09 -0400
Links: << >>  << T >>  << A >>
Nial Stewart wrote:
> 
> "S. Ramirez" wrote:
> 
> >  It isn't that hard to switch
> > from one to the other.
> 
> I've a fair bit of experience with VHDL and have hacked some Verilog.
> 
> Everyone tends to prefer 'their' language, but if you think you'll
> end up using both I think the consensus is that it's easier to move
> from VHDL to Verilog. Having said that VHDL probably has a slightly
> steeper learnign curve.
> 
> Nial.

VHDL has strong typing which is intended to reduce the number of errors
caused by not understanding the issues involved in type conversion. With
strong typing you have to explicitly convert one type to another. This
forces you to think about the issue each time. Unfortunately, it is not
always easy to figure out HOW to convert one type into another as the
libraries and operators are different from one implementation to the
next. 

I don't mean to say that VHDL libraries are built willy-nilly by the
vendor, but some offer IEEE libraries and others offer Synopsis style
libraries with IEEE sounding names. So, for a beginner, it can be a
daunting task to figure out when type conversion is needed in VHDL and
how to do it. 

Verilog is much more automatic. I recently converted from VHDL to coding
in Verilog and, so far, I have only been bitten once by a default that
did not work the way I expected. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 32232
Subject: Re: Force routing on an Apex
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 20 Jun 2001 13:14:32 -0400
Links: << >>  << T >>  << A >>
olivier wrote:
> 
> Hi,
> 
> For some reasons, I need to be able to force the routing on a group of cells
> in an Altera APEX400e.
> I have to create two identical blocks of logic that have to have the same
> routing. So far I could only lock the placement but the routing between the
> blocks remains different (I would like to use only local routing). I checked
> the ressource usage and it looks like that there are plenty of local routing
> available in the area (within a MegaLab). Look to me that the router is
> doing whatever he wants (even if I assign the local routing option), for one
> cell he uses a "fast track fan out" routing type instead of a "local
> routing"; whereas for the other identical block, same cell, he will use
> "local routing".
> Anybody knows how to constraint the router of QuartusII???
> 
> Thanks
> Olivier

I am no Quartus expert, but I believe that they don't provide routing
control because the routing is so simple in the APEX chips. They have a
well defined heirarchy of both logic and routing, which is fastest at
the lowest levels and slowest when you have to use the highest levels.
But you should only use the higher routing levels when routing between
higher/larger logic levels. So I am puzzled when you say two identical
placements are using different levels of routing. 

I would suggest that you double check the placement and verify that your
signals do not need to cross LABs, rows and MegaLABs except where you
expect it. I can't see why the tools would be using higher levels of
routing to stay within a given level of logic. 

The designs I have worked on show the levels of routing very clearly.
Each module which must work at high speeds is placed within a single row
and uses very fast routing exclusively, other than the IOs. Our timing
can tolerate one row to row interconnect which we see on the input. The
rest of the connections are within a row or within the LAB so they are
quite fast. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 32233
Subject: Synplify register replication
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 20 Jun 2001 18:33:52 +0100
Links: << >>  << T >>  << A >>

Has anybody else found that register replication seems to be at least
partly broken for Synplify 6.x.y ? At least for Xilinx devices. I have a
case outstanding and a bug report has been filed that shows some FF
primitives get replicated while others don't.

<flame on>

Its a bit sad that Synplicity's support has suffered the usual post-IPO
syndrome:

o Pre-IPO company is hungry for fame & fortune and will really sweat it
to get a good reputation among us geeks.

o IPO happens and all those engineers who made it happen suddenly
realise the joys that can be theirs when they combine stock opts with
Pacific islands and go for the ``No unit of time less than a season''
option.

o To placate all their new NASDAQ investors a road-map to taking over
the universe is promoted.

o Universe capture requires so much effort/money/time that the
conditions on planet earth start to deteriorate.

o Unrecognised the geek world starts looking for new lean & hungry
startups and drifting in their direction.

o Too late the company finds that (a) somebody already owns the universe
and (b) the customer base has now been hollowed out.

Synplify as a tool is still in the v. good to great range but the signs
of post-IPO megalomania are clearly there.

<flame off, or at least turned down a bit>


Article: 32234
Subject: Re: Gray counter STRUCTURAL (VHDL)
From: dmb2112@hotmail.com (Dave Bancroft)
Date: 20 Jun 2001 10:36:20 -0700
Links: << >>  << T >>  << A >>
Hi,

  You may want to look at pages 19-21 of this document for some help. 

http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf

  The code is in Verilog, but if you read the discussion you should be
able understand it.  I wrote the equivalent VHDL version a while ago
and you're welcome to try it.  I only did minimal testing on it, so
use it at your own risk.

  Dave

 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;

entity gray_counter is
  generic(size:		integer := 9);
  port(clock:		in std_logic;
       inc:		in std_logic;
       rst:		in std_logic;
       gray:		buffer std_logic_vector(size - 1 downto 0));
end gray_counter;

architecture rtl of gray_counter is

  signal gnext:		std_logic_vector(size - 1 downto 0);
  signal bin:		std_logic_vector(size - 1 downto 0);
  signal bnext:		std_logic_vector(size - 1 downto 0);
  
  begin
    Output_Register:
    process(clock)
      begin
        if rising_edge(clock) then
          if (rst = '1') then
            gray <= (others => '0');
          else
            gray <= gnext;
          end if;
        end if;
      end process Output_Register;
    
    gray2binary:
    process(gray)
      begin
	for i in 0 to size - 1 loop
	  bin(i) <= xor_reduce(gray(size - 1 downto i));
	end loop;
      end process gray2binary;
    
    bnext <= bin + inc;
      
    binary2gray:
    process(inc, bnext)
      begin
        for i in 0 to size - 1 loop
          if i = size - 1 then
            gnext(i) <= bnext(i);
          else
            gnext(i) <= bnext(i) xor bnext(i + 1);
          end if;
        end loop;
    end process binary2gray;

end rtl;

Article: 32235
Subject: Re: Pin locking in Maxplus2
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Jun 2001 17:45:16 GMT
Links: << >>  << T >>  << A >>
NT4.0 pretty much has all the 'niceties' of win95.  Are you running any of the
CAE tools under w2000?  If so, which ones, and are they stable too?

Russell Shaw wrote:
> 
> Nial Stewart wrote:
> >
> > Russell Shaw wrote:
> > >
> > > Going to w2k would be worthwhile...
> >
> > Russell,
> >
> > Have you found w2k to be stable?
> 
> Much so. In win95, i had to reset the pc before using netscape to
> reduce the instabilities. w2k is the best attempt yet at a useable
> windoze OS. Its got the niceties of win95, even tho its based on NT.
> The help system even details all the dos-box commands, unlike win95.
> 
> --
>    ___                                           ___
>   /  /\                                         /  /\
>  /  /__\                                       /  /\/\
> /__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
> \  \  /  Victoria, Australia, Down-Under      \  \/\/
>  \__\/                                         \__\/

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 32236
(removed)


Article: 32237
Subject: Re: Phase Locked loop implementation on FPGA
From: "Renzo Venturi" <staff@sisdigi.it>
Date: Wed, 20 Jun 2001 22:10:15 +0200
Links: << >>  << T >>  << A >>

"SilverByte" <vnwarrior@rediffmail.com> ha scritto nel messaggio
news:c0e424f8.0106200427.63b4a55a@posting.google.com...
> hi,
>    I have to implement a Digital PLL on an FPGA. Does anyone have any
> docs regarding this.
> Any docs regarding generic design of a PLL is also appreciated.
> Thanks in advance
> Sandy

http://www.actel.com/appnotes/s04_18.pdf

Renzo Venturi




Article: 32238
Subject: Re: Gray counter STRUCTURAL (VHDL)
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 20 Jun 2001 13:18:20 -0700
Links: << >>  << T >>  << A >>

--------------181F565EDAA47154E2A78675
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

My method to build a Gray counter longer than a few bits - and you may call this
"brute force" -  is as follows:
Build a binary counter, using the dedicated carry structures in modern FPGAs, so
that this counter can run at 200 MHz+.
Then add a second set of flip-flops, the Gray register, aligned with the counter
bits.
Then drive the D of the Gray bits through an XOR gate, using the equivalent
binary bit XORed with the next higher binary bit.
In Virtex, you need not take the binary Qs, you can actually take the binary Ds
as input to the XOR, which means the Gray register does not have a pipeline
delay, and that simplifies the enabling/disabling of the counter.
Yes, it costs two flip-flops per bit, but "flip-flops are cheap".
Speed is more important.

Peter Alfke, Xilinx Applications
==============================
Nikiforakis Manos wrote:

> Hello All.Can anyone please give me a hint on how am I going to desigh a gray
> code counder (stuctural description)?I've tried using T and D flip flops with
> the equations I got from Carneaut's maps but when I wrote the VHDL model
> either it falt in loops or it didn't worked at all (probably because of
> multiple feedbacks).I cannot find out what's happening and I cannot find even
> one model in the internet using styctural description for more than 2 bits!I
> will design (hopefully) a 16 bit counter but any help regarding to a  >2,3bit
> counter would be what I need to start.Thank you in advance. Nikiforakis
> ManosStuding Physics at Aristotle UniversityThessaloniki, Greeceemail:
> manolios@auth.gr

--------------181F565EDAA47154E2A78675
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Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<body bgcolor="#FFFFFF">
My method to build a Gray counter longer than a few bits - and you may
call this "brute force" -&nbsp; is as follows:
<br>Build a binary counter, using the dedicated carry structures in modern
FPGAs, so that this counter can run at 200 MHz+.
<br>Then add a second set of flip-flops, the Gray register, aligned with
the counter bits.
<br>Then drive the D of the Gray bits through an XOR gate, using the equivalent
binary bit XORed with the next higher binary bit.
<br>In Virtex, you need not take the binary Qs, you can actually take the
binary Ds as input to the XOR, which means the Gray register does not have
a pipeline delay, and that simplifies the enabling/disabling of the counter.
<br>Yes, it costs two flip-flops per bit, but "flip-flops are cheap".
<br>Speed is more important.
<p>Peter Alfke, Xilinx Applications
<br>==============================
<br>Nikiforakis Manos wrote:
<blockquote TYPE=CITE><style></style>
<font face="Arial"><font size=-1>Hello
All.</font></font><font face="Arial"><font size=-1>Can anyone please give
me a hint on how am I going to desigh a gray code counder (stuctural description)?</font></font><font face="Arial"><font size=-1>I've
tried using T and D flip flops with the equations I got from Carneaut's
maps but when I wrote the VHDL model either it falt in loops or it didn't
worked at all (probably because of multiple feedbacks).</font></font><font face="Arial"><font size=-1>I
cannot find out what's happening and I cannot find even one model in the
internet using styctural description for more than 2 bits!</font></font><font face="Arial"><font size=-1>I
will design (hopefully) a 16 bit counter but any help regarding to a&nbsp;
>2,3bit counter would be what I need to start.</font></font><font face="Arial"><font size=-1>Thank
you in advance.</font></font>&nbsp;<font face="Arial"><font size=-1>Nikiforakis
Manos</font></font><font face="Arial"><font size=-1>Studing Physics at
Aristotle University</font></font><font face="Arial"><font size=-1>Thessaloniki,
Greece</font></font><font face="Arial"><font size=-1>email: <a href="mailto:manolios@auth.gr">manolios@auth.gr</a></font></font></blockquote>

</body>
</html>

--------------181F565EDAA47154E2A78675--


Article: 32239
Subject: Re: Pin locking in Maxplus2
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 21 Jun 2001 11:20:20 +1000
Links: << >>  << T >>  << A >>
Not sure what is meant by CAE tools. Last time i used NT (can't
remember the version), the plug/play hardware installation and
recognition of win95 was practically non-existant.

Ray Andraka wrote:
> 
> NT4.0 pretty much has all the 'niceties' of win95.  Are you running any of the
> CAE tools under w2000?  If so, which ones, and are they stable too?
> 
> Russell Shaw wrote:
> >
> > Nial Stewart wrote:
> > >
> > > Russell Shaw wrote:
> > > >
> > > > Going to w2k would be worthwhile...
> > >
> > > Russell,
> > >
> > > Have you found w2k to be stable?
> >
> > Much so. In win95, i had to reset the pc before using netscape to
> > reduce the instabilities. w2k is the best attempt yet at a useable
> > windoze OS. Its got the niceties of win95, even tho its based on NT.
> > The help system even details all the dos-box commands, unlike win95.
> >

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 32240
Subject: RAM_blocks inference in Leonardo Spectrum!
From: vazkevin@hotmail.com (Kevin VAZ)
Date: 20 Jun 2001 21:24:10 -0700
Links: << >>  << T >>  << A >>
Dear Friends,

I'am having problems in understanding if my design is infering block rams or
not.

The device used is Vertex E 600ebg432
the EDA is Leonardo Spectrum
The design has 22 3Kbit ram instantiations
yet reports after optimisation is 66CLB
If rams are made black boxes report is 35CLB

I would appreciate if any one can suggest a suitable solution.
Thanks,
Kevin.

Article: 32241
Subject: Re: LVDS questions
From: isu@btae.mam.gov.tr (I. Servan Uzun)
Date: Thu, 21 Jun 2001 05:56:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

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	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi,

1-) Here is an extensive website dedicated to LVDS technology from =
National Semiconductors.
http://www.national.com/appinfo/lvds/

There is a book titled "LVDS Owner's Manual & Design Guide" from =
National. You
can download all chapters in pdf. You can also request a hardcopy of =
this book without any charge. (I have it!)

2-) I am currently using ALTERA APEX family FPGA device.=20
APEX 20KE400, 20KE600, 20KE1000 devices support 16 True-LVDS Receiver
and 16-True LVDS Driver I/Os. And as far as I remember, Altera' s =
Mercury family
supports lots of LVDS Rx and Tx I/Os.

Regards,
Servan


------=_NextPart_000_001D_01C0FA2F.DA7743B0
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	charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2314.1000" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Hi,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>1-) Here is an extensive website =
dedicated to LVDS=20
technology from National Semiconductors.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.national.com/appinfo/lvds/">http://www.national.com/ap=
pinfo/lvds/</A></FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>There is a book titled "LVDS Owner's =
Manual &amp;=20
Design Guide" from National. You</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>can&nbsp;download all chapters in pdf. =
You can also=20
request a hardcopy of this book without </FONT><FONT face=3DArial =
size=3D2>any=20
charge. (I have it!)</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>2-) I am currently using ALTERA APEX =
family FPGA=20
device. </FONT></DIV>
<DIV><FONT face=3DArial size=3D2>APEX 20KE400, 20KE600, 20KE1000 devices =
support 16=20
True-LVDS Receiver</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>and 16-True LVDS Driver I/Os. And as =
far as I=20
remember, Altera' s Mercury family</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>supports lots of LVDS Rx and Tx =
I/Os.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Servan</FONT></DIV>
<DIV>&nbsp;</DIV></BODY></HTML>

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Article: 32242
Subject: Re: Pin locking in Maxplus2
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 21 Jun 2001 08:56:51 +0100
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> NT4.0 pretty much has all the 'niceties' of win95.  Are you running any of the
> CAE tools under w2000?  If so, which ones, and are they stable too?

Ray,

As far as I know NT 4.0 still can't drive USB devices which is why
I was wondering about win2K. If it's as stable as NT with the 
hardware drivers of win 98/95 then it sounds a good bet.

Nial.

Article: 32243
Subject: Re: Pin locking in Maxplus2
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 21 Jun 2001 18:41:06 +1000
Links: << >>  << T >>  << A >>


Nial Stewart wrote:
> 
> Ray Andraka wrote:
> >
> > NT4.0 pretty much has all the 'niceties' of win95.  Are you running any of the
> > CAE tools under w2000?  If so, which ones, and are they stable too?
> 
> Ray,
> 
> As far as I know NT 4.0 still can't drive USB devices which is why
> I was wondering about win2K. If it's as stable as NT with the
> hardware drivers of win 98/95 then it sounds a good bet.

w2k supports usb devices, and installs as winnt on the hdd...

Article: 32244
Subject: Altera configuration devices
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 21 Jun 2001 18:44:25 +1000
Links: << >>  << T >>  << A >>
Hi,

Anyone know if/when altera is going to do more flash-reprogrammable
configuration devices? At the moment, there's only EPC2, and its
a bit difficult getting one here...

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 32245
Subject: Re: FPGA Boards
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 21 Jun 2001 09:46:35 +0100
Links: << >>  << T >>  << A >>
Lewis wrote:
> 

> 
> Thanks
> 
> L

You could also try 

http://www.burched.com.au


There have been quite a few good reports on these and they're
very reasonably priced.

Nial.

Article: 32246
Subject: Date/Time at synthesis -> std_logic_vector
From: "Andrew Bridger" <andrew.bridger@xtra.co.nz>
Date: Thu, 21 Jun 2001 23:30:43 +1200
Links: << >>  << T >>  << A >>
Hi,
We are using Xilinx ISE 3.1, XST synthesis targeting a Virtex-E FPGA.  I
would like to know if there is a way to get the system date/time at
synthesis time and put it into type std_logic_vector(say 32 bits?) into my
code?  This would allow me to read back a register inside the FPGA that
could tell me the date/time synthesis occured.  I.e. this is a form of
development build ID.

The alternative is for me to manually increase a revision number register
each time I synthesize.  This works fine but I thought there might be a more
automated way.

Ideas?











Article: 32247
Subject: FFT limited size input
From: finishf@yahoo.com (finish)
Date: 21 Jun 2001 05:05:04 -0700
Links: << >>  << T >>  << A >>
hello,

From my modest background, i know that for performing the FFT
transform on an input signal, i have to extend it, if required, by
zeros to 2^n.
FFT is a global transform,i.e the whole input sequence should be
available.

In practise, most often we take 1024 or 512, but i see some commercial
hardware implementation for just 16 input data.

How far will this limited input size transform affect the overall
performance ?

thanks

H.S

Article: 32248
Subject: Two's Complement conversion for FIR coefficients
From: dottavio@ised.it (Antonio)
Date: 21 Jun 2001 05:35:37 -0700
Links: << >>  << T >>  << A >>
I've the coefficient 0.102546681502 that I want to translate in
2'complement fixed point binary number having 1 bit for the sign, 1
bit before the point and 10 bit after, what I have to do ?? Is there
any software to make this automatically also for the opposite
conversion ???
Thanks you a lot

Antonio D'Ottavio

Post a follow-up to this

Article: 32249
Subject: Xilinx Software free
From: dottavio@ised.it (Antonio)
Date: 21 Jun 2001 05:39:14 -0700
Links: << >>  << T >>  << A >>
I need the latest version of Xilinx Foundation Software, there is some
way to have it free ?? I'm just a poor student, thank you for your
answer ...

Antonio D'Ottavio



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