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Messages from 32525

Article: 32525
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Fri, 29 Jun 2001 04:22:15 GMT
Links: << >>  << T >>  << A >>
There is a little bit of a catch.  It's the old "Euro vs. US" question.
Capitalism thrives a bit more here so your standard of living, at least
monetarily, is going to be higher.  There is less redistribution of wealth,
so not only will you make more, but you'll keep more.  You'll have more
money, more posessions, better healthcare, etc.

There is a downside.  Growth is unchecked.  You'll have a nice car, but
you'll spend a lot more time in it, on crowded freeways.  You'll have a nice
house, but it will be in a drab suburbia, far removed from any sort of
downtown.  If you really like euro-style cities, denser, with more parks, in
which you can walk from your flat to the bookstore, grocery, etc., then you
might be disappointed.  And I agree with Peter; I've seen European spouses
dissatisfied with their new home.

-Kevin

"cyber_spook" <pjc@cyberspook.freeserve.co.uk> wrote in message
news:3B3BA005.8DEC43F9@cyberspook.freeserve.co.uk...
> A non-techie question....
>
> With the current down turn in profits and stock prices falling. The Job
> market here in the UK has started to get flooded with engineers that are
> being laid off and people are starting to get very unsettled.
>
> All this is tempting me to move to the USA as I constantly see more
> interesting job advertised and for good money. I also know that your
> house prices are better then ours and petrol (gas) is a lot lower.
>
> So my question is... What's the catch? do you all sleep well at night
> knowing that there is enough in the bank to pay the bills? The grass
> looks very green and very tasty from this side of the pond!
>
> Regards
>
> Cyber_spook_man
>
>



Article: 32526
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: stuart_clubb@nospam.hotmail.com (Stuart Clubb)
Date: Fri, 29 Jun 2001 05:24:54 GMT
Links: << >>  << T >>  << A >>
Greetings all, I'm back - did you miss me?

OK, well I have made the transition from The UK to the USA. I did a
huge amount of research into what to expect so I have not been too
surprised so far. Here are some things you need to bear in mind.

1 - Cost of living in Silicon valley is nuts - if you are used to the
gentle hills and dales, or even the M4 corridor, you'll find
California quite a shock. Personally, you could not pay me enough to
work there. Well, about $400K a year might be almost enough :-)

2 - Don't calculate your income on bonuses or stock at all. It's icing
on the cake, but ignore it completely for negotiation purposes. Most
peoples options are in the toilet right now and I firmly believe that
cash in the hand rules.

3 - Do the math carefully about what your take-home will actually be.
Research the current Federal and Local State Income Tax as well as the
cost of living (rent/food/car). I can assist there. You will also want
to keep your National Insurance contributions up, even though you are
away from the UK. It's not expensive, so it's worth doing it.

4 - You'll have NO CREDIT HISTORY. You will be turned down for store
cards based solely on a non-existent credit history (I have been). You
will be turned down for the numerous interest-free offers you will see
relating to electrical goods (forget that widescreen TV matey).
Basically, you will not be able to get finance on anything. The fact
that you make a shed-load of cash and have no debts just wont
register, they'd rather lend money to a Mexican fruit picker with a
recent bankruptcy than YOU. Oh, and furniture stores like Ethan Allen
(nice furniture, but pricey) generally carry zero stock, so expect
12-16 week delivery times unless you buy cheap temporary stuff from
"Goodwill" or ex-rental stores (I have!). Bottom line - you will have
to run on CASH for at least the first six months, probably more like a
year before you even start to get treated reasonably. Expect this and
you will not be disappointed. Also, dont apply for credit too many
times as this also adversely affects your score. You might even have
trouble getting a car loan! I leased a car and had to get three US
citizens to vouch for me, a letter from my employer plus all my
immigration documentation before they finally agreed. However you WILL
get a credit card from your US bank which is often set at 10% of your
income, or $5000, whichever is the lesser. Believe me, trying to do
business expenses on that kind of limit is a right pain in the arse.
Treat that card very carefully, dont go over 75% of the limit and
always pay the balance off. That will help to establish your credit
faster.

Your history in the UK will not count for shit due to the data
protection and consumer credit act. I am investigating how that can be
circumvented seeing as one of the credit agencies, Equifax, operates
in the UK and the USA.

5 - Due to (4) your chances of getting a fair rate mortgage seem to be
very low unless you put a SIGNIFICANT deposit down - That means 20%+
here, which with the current exchange rate means you will not probably
not like what you see unless you are completely loaded. As a UK
engineer I suspect you are not quite hob nobbing with the Sultan of
Brunei ;-). Here in Portland, Oregon, about $300K will get a fairly
reasonable house. (American houses are only wooden huts compared with
the UK though). That means you'll probably need about 50K pounds to
cover closing and down-payment. I'm investigating this right now with
mortgage brokers, so the story may change. As for buying in Silicon
Valley? Hah hah, if you can afford housing within an hour of where you
would be working, then you probably don't need the job in the first
place! You might be able to rent a rabbit hutch for about $1500 a
month about 2Hrs from work! If you have a family, you will probably
want to put them into cold storage for your sojourn to The Valley.
Again, if you are already rich, and have landed that dream $400K a
year job then you need not worry about such things too much.

6 - Good driving record in the UK? Wont help you. You will be treated
like a lunatic 16 year old with a provisional license. Expect to pay
anything up to $1500 for the first six months insurance. They will
usually expect you to get your drivers license within 30 to 60 days of
covering you on an International license. Rest easy though, you'll
pass easily because American driving standards are a joke compared
with the UK. Also, dont forget that if/when you return to the UK, your
car insurance may jump because you have not been driving in the UK.
You can drive a nice car in the US if you want, it's just going to
cost you a lot to do so. Factor this into your equation especially if
you get a company car in the UK now.

7 - When you relocate make sure you get a good relocation package.
Minimum that should include should be:
    i) Relocation and shipping of all household goods etc.
    ii) 1 months corporate rent of a furnished house to enable you to
find permanent accomodation. You should try to sort out a one-week
expensed househunting trip to locate the house/apartment you will
initially stay in. You may want to consider taking over the rent
(unfurnished) at the end of the company provision. Also put a clause
in your relocation that extends the provision for every month that
your shipment from the UK has not arrived. I didn't. No biggie when
single, but a wife would kill you for that kind of mistake.
    iii) Provision of one rental vehicle for yourself and if
        neccessary, your spouse and children. (Insurance to be
provided by your employer too)
    iiii) A large lump sum payable on arrival as a relocation bonus to
cover exceptional expenses and on-costs that are not expensable as
part of your agreed relocation expenses. This will be taxable, so I'd
suggest at least $10K, but $20K is proabbly better. The company might
tie this to you being with the company a year (or you pay it back),
but make sure you set it so that if they fire you they lose all claim
to the cash.

So, what am I saying? If the opportunity is right, and the money is
VERY right, then the experience of working in the USA is generally a
positive one. If you are single, it's less of a risk. If married with
children in school, I'd say don't do it unless the money is such that
you can put the kids into private school and keep you wife duly amused
(remember she wont be able to get a job). Do not be taken in by
seemingly high salaries with big numbers. It seems commonplace for
Silicon Valley employees to make in upwards of $100K with little
competence or skills at all. I have personally interviewed candidates
who were about as much use as chocolate fireguards, yet claimed to
have base salaries of $150K. They were probably bullshitting, but you
will find that the average American engineer is frankly "a bit thick"
in comparison with UK and European standards. That's why Silicon
Valley companies are so reliant on imported Asian, Indian and European
(east and west) talent.

Apologies to the smart US citizens on the board, but I have to be
honest here. Perhaps I just have high standards?

Don't worry about moving out here now and and being fired due to the
"economic slowdown". The secret is to make it so bloody expensive for
them to hire you and ultimately fire you, that they'll fire all the US
national's first :-). If they do fire you, they are legally obliged to
fund your repatriation to your home country. The US Immigration and
Naturalisation Service (INS) enforces that one, but make sure you get
a contract that covers repatriation of any goods and reimbursement of
costs incurred by your forced departure from the USA as well. This is
especially so if you buy a house and then have to sell it remotely
through some thieving scumbag American Realtor who will rape you for
6% of the sale price just for sticking a sign in the front yard. (And
you thought UK Estate agents were bad?)

Oh, one last thing. If you accept a job in the USA..... DO NOT UNDER
ANY CIRCUMSTANCES RESIGN YOUR PRESENT JOB UNTIL YOU HAVE YOUR PASSPORT
BACK WITH YOUR H1-B VISA IN IT.

If all this discourages you, then good. It's not something to consider
doing just because it will make you a few more quid.

Anyone thinking about making the move is welcome to contact me.
through the hotmail address, just remove the spam protection.

Cheers
Stuart

On Thu, 28 Jun 2001 22:22:13 +0100, cyber_spook
<pjc@cyberspook.freeserve.co.uk> wrote:

>A non-techie question....
>
>With the current down turn in profits and stock prices falling. The Job
>market here in the UK has started to get flooded with engineers that are
>being laid off and people are starting to get very unsettled.
>
>All this is tempting me to move to the USA as I constantly see more
>interesting job advertised and for good money. I also know that your
>house prices are better then ours and petrol (gas) is a lot lower.
>
>So my question is... What's the catch? do you all sleep well at night
>knowing that there is enough in the bank to pay the bills? The grass
>looks very green and very tasty from this side of the pond!
>
>Regards
>
>Cyber_spook_man
>


Article: 32527
(removed)


Article: 32528
(removed)


Article: 32529
Subject: Digital PLL, frequency multiplication: looking for problem : )
From: "Thomas Lehner" <thomas.lehner@contec.at>
Date: Fri, 29 Jun 2001 10:11:23 +0200
Links: << >>  << T >>  << A >>
 Something new:
 I already _have_ the solution and am looking for a suitable problem now.

 I found a way to multiply the frequency of a rectangular signal by any
rational value. It works _continuously_ from 0 to say 100 MHz.

Contiously means, that there is no lock-in range or similar behaviour. The
output signal simply tracks the input as fast as possible.

The output frequency can be higher or lower than the input frequency.

Additionally a software filter can remove jitter present in the input
signal.



Currently I use it to write a pattern with variable resolution into a
rotating role with a laser.

A sensor gives 5000 pulses per revolution. My hardware enables the customer
to choose the resolution of the pattern freely. It can be e.g. 128312 pulses
per revolution.

The surface speed of the role is 20 m/sec and the accuracy of the points is
as high as 500 nm !! So the quality of the output signal is really very
good.



Unfortunately my customer sells his machines in a niche market.

So I am looking for new applications.



There _must_ be people out there having the same or a similar problem.



Here some additional specs:



Ratio : can be chosen by software between 1000000 : 1 and  1 : 1000000
(integral steps)

Output jitter: depends on hardware but can be as low as 1 ns.

Reaction time: 10 us





Do you know any applications for this technology ?



Any help would be appreciated.



With kind regards




Thomas


























Article: 32530
Subject: Clock Speed using Modern ASIC technology
From: "Jinsang Kim" <jskim27@kt.co.kr>
Date: Fri, 29 Jun 2001 20:18:46 +0900
Links: << >>  << T >>  << A >>
Dear All:

Do you have any idea what's the maximum clock rate using full-custom
technology and commercial ASIC chips?

Thanks in advance.



Article: 32531
Subject: Re: Clock Speed using Modern ASIC technology
From: Kolja Sulimma <kolja@sulimma.de>
Date: Fri, 29 Jun 2001 13:41:12 +0200
Links: << >>  << T >>  << A >>
This really depends on you design style and you design.

Some examples:

- The propagation delay of an Inverter is only a couple of picoseconds.
- Flip-Flop toggle rates should be in the tens of Gigahertz.
- Stanford university built a 4Gbit/s CMOS serial transceiver years ago.

- some Processors rund at 1,7 GHz
- most 3D graphic accelerator designs do not reach 200 MHz due to the
complexity of the design.
- my former employer still does not believe that you can build anything
with more then 50 MHz.

You can get spice models of a 0.18 micron technology at www.mosis.org
This way you can find out how fast your circuit is going to be....

Kolja Sulimma



Jinsang Kim wrote:

> Dear All:
>
> Do you have any idea what's the maximum clock rate using full-custom
> technology and commercial ASIC chips?
>
> Thanks in advance.


Article: 32532
Subject: Newbee and FAQ
From: "Ruud Baltissen" <Ruud.Baltissen@abp.nl>
Date: Fri, 29 Jun 2001 13:55:14 +0200
Links: << >>  << T >>  << A >>
Hallo allemaal,

I still do a lot of things with the old Commodore computers. One of my last
designs enables one to use PC ISA-cards with a C64 or C128:
http://home.hccnet.nl/g.baltissen/pccard.htm
http://home.hccnet.nl/g.baltissen/pccard16.gif

This design needs over 50 IC's and I already would be happy to replace at
least the glue-logic. So I posted a general question about FPGA's to some C=
users and somebody answered that the FAQ of your newsgroup would answer a
lot of questions. Where can I find it, please?

Is there any body willing to have a quick look at the schematics and then
willing to tell what FPGA could replace all IC's. 8237's, the DMA-chips
don't need to be included.
What programmer and software do I need to program it?
Question: can a FPGA drive a bus or do I need additional buffers?

Thanks for any help in any form !!!
   ___
  / __|__
 / /  |_/     Groetjes, Ruud
 \ \__|_\
  \___|       http://Ruud.C64.org





Article: 32533
Subject: Re: Newbee and FAQ
From: Kolja Sulimma <kolja@sulimma.de>
Date: Fri, 29 Jun 2001 14:12:29 +0200
Links: << >>  << T >>  << A >>
I do not know of any FAQ, but you should be able to do a design like this in any
modern FPGA.
You should make sure that your FPGA of choice tolerate 5V I/O. That's true for
all but the newest FPGAs.

You might want to check if you can do it in a FLASH CPLD instead of an SRAM
FPGA. That way you need no configuration memory that costs money and board area.

Also, FPGAs are not easy to get in Europe - in the Netherlands it's somewhat
bettern than in germany - whereas the XC9500XL CPLDs for example can be ordered
directly from the Xilinx Website.
Alternatively you can connect the configuration pins to some unused CIA I/O or
to the unused 6510 I/O Pins.
Then you can load the FPGA configuration from a floppy disc and configure the
FPGA by software.

Modern FPGAs and CPLDs are usually only available in SMD packages. Do not be
afraid of that. With a PCB of good quality you can solder PQFP by hand. There
are instructions for this on the WWW.

Free Software for small FPGAs and CPLDs is available on the homepages of most
manufactures: www.xilinx.com, www.altera.com, ....

Kolja Sulimma

Ruud Baltissen wrote:

> Hallo allemaal,
>
> I still do a lot of things with the old Commodore computers. One of my last
> designs enables one to use PC ISA-cards with a C64 or C128:
> http://home.hccnet.nl/g.baltissen/pccard.htm
> http://home.hccnet.nl/g.baltissen/pccard16.gif
>
> This design needs over 50 IC's and I already would be happy to replace at
> least the glue-logic. So I posted a general question about FPGA's to some C=
> users and somebody answered that the FAQ of your newsgroup would answer a
> lot of questions. Where can I find it, please?
>
> Is there any body willing to have a quick look at the schematics and then
> willing to tell what FPGA could replace all IC's. 8237's, the DMA-chips
> don't need to be included.
> What programmer and software do I need to program it?
> Question: can a FPGA drive a bus or do I need additional buffers?
>
> Thanks for any help in any form !!!
>    ___
>   / __|__
>  / /  |_/     Groetjes, Ruud
>  \ \__|_\
>   \___|       http://Ruud.C64.org


Article: 32534
Subject: Re: FPGA Boards
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Fri, 29 Jun 2001 14:23:54 +0200
Links: << >>  << T >>  << A >>
Rick Collins <spamgoeshere4@yahoo.com> schrieb in im Newsbeitrag:
3B30D54A.9040D22D@yahoo.com...
>
Have you checked the X2S_EVAL rapid prototyping board
from www.cesys.com ??

Manfred




Article: 32535
Subject: Re: Xilinx System Generator Simulation Problem
From: "JianYong Niu" <cop00jn@shef.ac.uk>
Date: Fri, 29 Jun 2001 16:05:59 +0100
Links: << >>  << T >>  << A >>
Hi, Ray:
Thanks for your suggestion. I have solved the problem following your
suggestion. However, new errors occured as follows:

# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity xlmult_core1
# -- Compiling architecture behavior of xlmult_core1
# ERROR: Could not find
C:/modeltech_xe/xilinx/vhdl/XilinxCoreLib.mult_vgen_v2_0
# ERROR: xlmult_core1.vhd(34): cannot find expanded name:
xilinxcorelib.mult_vgen_v2_0
# ERROR: xlmult_core1.vhd(34): Unknown field: mult_vgen_v2_0.
# ERROR: xlmult_core1.vhd(59): VHDL Compiler exiting
# ERROR: C:/Modeltech_xe/win32xoem/vcom failed.
# Error in macro C:\MATLABR11\work\vcom.do line 26
# C:/Modeltech_xe/win32xoem/vcom failed.
#     while executing
# "vcom -93 xlmult_core1.vhd"

There is only mult_vgen_v1_0 in xilinxcorelib, but no mult_vgen_v2_0. Where
can I find that mult_vgen_v2_0?  If it is a library update problem, where
can I find the update file?

I am using modelsim XE 5.3d with a starter's licence.
Thanks




Ray Andraka <ray@andraka.com> wrote in message
news:3B38CD19.B9FC0B5@andraka.com...
> You are pointing to the unisims source, not to a compiled library.  You
need to
> compile the unisim library with modelsim, and then the token should point
to
> the compiled library.  CHeck the answers data base on the xilinx website.
There
> are instructions there on how to compile the library, as well as tcl
scripts to
> do it.
>
> JianYong Niu wrote:
>
> > Hi, All:
> >
> > I am using Xilinx System Generator to design an application in Matlab
> > simulink evironment. I use ModelSim starter version to simulate the
design.
> >
> > Problems occured while the vcom.do file was excecuted:
> >
> > I have changed the %XILINX% token in the vcom.do file into the xilinx
path
> > in my computer. errors occured as follows:
> >
> > # ERROR: C:/XILINX/vhdl/src/unisims is not a valid library: no info
file.
> > # ERROR:
C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(14):
> > Library unisim not found.
> > # ERROR:
C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15):
> > Unknown identifier: unisim
> > # ERROR:
C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(17):
> > VHDL Compiler exiting
> >
> > what is the info file?
> >
> > I find a info file from my matlab work directory, and copied it into the
> > xilinx unisims path. then the following errors occured when I run
modelsim:
> >
> > ERROR: Could not find C:/XILINX/vhdl/src/unisims.vcomponents
> > # ERROR:
C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15):
> > cannot find expanded name: unisim.vcomponents
> > # ERROR:
C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15):
> > Unknown field: vcomponents.
> > # ERROR:
C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(17):
> > VHDL Compiler exiting
> > # ERROR: C:/Modeltech_xe/win32xoem/vcom failed.
> >
> > However, I do find a file 'unisims.vcomp' in the directory. what is the
> > problem?
> >
> > thanks.
> >
> > Jianyong
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>



Article: 32536
Subject: Error to execute vcom.do in ModelSim XE5.3d
From: "JianYong Niu" <cop00jn@shef.ac.uk>
Date: Fri, 29 Jun 2001 16:11:21 +0100
Links: << >>  << T >>  << A >>
Hi, All:

Here I need your brilliant suggestion:

Errors occured when the vcom.do file was executed in ModelSim XE 5.3d, as
follows:

# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity xlmult_core1
# -- Compiling architecture behavior of xlmult_core1
# ERROR: Could not find
C:/modeltech_xe/xilinx/vhdl/XilinxCoreLib.mult_vgen_v2_0
# ERROR: xlmult_core1.vhd(34): cannot find expanded name:
xilinxcorelib.mult_vgen_v2_0
# ERROR: xlmult_core1.vhd(34): Unknown field: mult_vgen_v2_0.
# ERROR: xlmult_core1.vhd(59): VHDL Compiler exiting
# ERROR: C:/Modeltech_xe/win32xoem/vcom failed.
# Error in macro C:\MATLABR11\work\vcom.do line 26
# C:/Modeltech_xe/win32xoem/vcom failed.
#     while executing
# "vcom -93 xlmult_core1.vhd"

There is only mult_vgen_v1_0 in xilinxcorelib, but no mult_vgen_v2_0. Where
can I find that mult_vgen_v2_0?  If it is a library update problem, where
can I find the update file?

I am using modelsim XE 5.3d with a starter's licence.
Thanks

Jianyong




Article: 32537
Subject: Asynchronous design in Virtex FPGA
From: "Michael" <mke@nospam.dk>
Date: Fri, 29 Jun 2001 17:28:41 +0200
Links: << >>  << T >>  << A >>
Hi,

I am working on a minor project, trying to implement an asynchronous design
in a fpga.
I've got at RC1000-PP with a Virtex 1000 fpga (from the Xilinx university
program).

The design flow is
VHDL -> FPGA Compiler 2 (export edif) -> Xilinx Alliance 3.1i -> upload
bit-file to fpga

The asynchronous design is utilizing a bundled data protocol, that is, a
control- and data path. It is okay that the datapath is optimized, but I
have been fighting the tools to avoid optimization of the logic in the
control path.

1) On the controlpath I need several delay elements (each implemented as an
assymetric c-element in a LUT). Unfortunately the Alliance tool optimizes
this delay path away, and replaces it with a wire.
2) When I make an asynchronous ring (fifo with the output connected to the
input), the stages are optimized away, unless I map a controlsignal from the
stage to an output pad.

Are there a way to pass on a don't touch statement through the edif file, or
prevent Alliance from doing any optimization?

Regards,
-=[ Michael Kristensen ]=[ mke@nospam.dk ]=-



Article: 32538
Subject: obfuscated tools
From: Goran Bilski <goran@xilinx.com>
Date: Fri, 29 Jun 2001 09:12:18 -0700
Links: << >>  << T >>  << A >>
Hi,

Do anyone know of a tool that obfuscate VHDL code?

Thanks
Göran Bilski


Article: 32539
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: Phil James-Roxby <phil.james-roxby@xilinx.com>
Date: Fri, 29 Jun 2001 10:13:55 -0600
Links: << >>  << T >>  << A >>
> However you WILL
> get a credit card from your US bank which is often set at 10% of your
> income, or $5000, whichever is the lesser. Believe me, trying to do
> business expenses on that kind of limit is a right pain in the arse.
> Treat that card very carefully, dont go over 75% of the limit and
> always pay the balance off. That will help to establish your credit
> faster.

> 5 - Due to (4) your chances of getting a fair rate mortgage seem to be
> very low unless you put a SIGNIFICANT deposit down

I have to disagree with Stuart on this point (but only this one) 
Stuarts reply should be regarded as a FAQ, though I think shed is a bit
harsh :-)
My US bank would not give me a credit card after being here for a year,
but they would give me a fair rate mortgate without a huge deposit after
we had been here for 2 months (the same bank!).  Similarly, I easily got
a car lease without any fuss after we had been here less than a month!
I guess my advice would be that all things are possible when it comes to
finance, but it depends on getting the right person who is prepared to
do a little more donkey work for you than the average Joe/Joanne.  This
is more luck than judgement admittedly, but by talking to other ex-pats,
you get to hear about these people.  Since they've jumped through the
considerable hoops more than once, they seem happy to do it again.
And wives/partners can work, they just can't get paid.  So voluntary
work at the local dog pound etc. is still possible.  Its not like
spouses _have_ to sit in the 'shed' all day.
Phil

-- 
---------------------------------------------------------------------
 __
/ /\/  Dr Phil James-Roxby         Direct Dial: 303-544-5545
\ \    Staff Software Engineer     Fax: Unreliable use email :-)
/ /    Loki/DARPA                  Email: phil.james-roxby@xilinx.com
\_\/\  Xilinx Boulder                 
---------------------------------------------------------------------

Article: 32540
Subject: VHDL using Xilinx foundation software
From: dpariseau@compuserve.com (David Pariseau)
Date: 29 Jun 2001 10:19:06 -0700
Links: << >>  << T >>  << A >>
I'm in the process of teaching myself VHDL using Xilinx's
Foundation software.  I've broken a larger design into 
smaller bits and am working on a baud rate generator at the
moment and am perplexed by some strange behavior.

The Vhdl program below checks out and synthesizes fine but
when I run it through the simulator the Init to ICount 
assignment flips the lines around connecting Init[15] -> 
ICount[0] and swapping all the lines accordingly.

I've tried various things to try and remedy this problem
but have been unable to make it work out???  

I've also tried to use the ieee.std_logic_1164.all and 
work.std_arith.all libraries to get around it, but for
some reason Xilinx can't find work.std_arith.all???

Any thoughts?

Thanks 
Dave Pariseau.
-----------------
library ieee;
use ieee.std_logic_1164.all;

entity BaudCounter is
    port (
        Init:  in  integer range 0 to 65535;
        Load:  in  bit;
        Reset: in  bit;
        Clki:  in  bit;
        Clko:  out bit;
        Clko2: out bit 
    );
end BaudCounter;

architecture BaudCounter_arch of BaudCounter is
signal ICount : integer range 0 to 65535;
signal BCount : integer range 0 to 65535;
signal HalfOn : bit;
begin
	process
	begin
		wait until (Clki'event and Clki = '1');
		
		if Load = '1' then
			ICount <= Init;
		elsif Reset = '1' then
			BCount <= ICount;
			HalfOn <= '0';
		elsif BCount = 0 then
			if HalfOn = '0' then
				HalfOn <= '1';
			else
				HalfOn <= '0';
				Clko   <= '1';
			end if;
			Clko2  <= '1';
			BCount <= ICount;
		else 
			Clko   <= '0';
			Clko2  <= '0';
			BCount <= BCount -1;
		end if;
		
	end process;
end BaudCounter_arch;

Article: 32541
Subject: Re: Xc4K still alive? (5v vs 3.3v)
From: Santiago de Pablo <sanpab@eis.uva.es>
Date: Fri, 29 Jun 2001 19:30:35 +0200
Links: << >>  << T >>  << A >>
Hi Peter,

  I'm agree with you: it is better, and cheaper, to change to new
low-voltage, low-consume, high-performance and low-price! components.

  But what about "power electronics": say you want to control an AC
drive
using 1200V-200A semiconductors at 2-5 kHz. Does anyone experience using
3.3v FPGAs in that noisy environment? I'm using 5v PLDs and 5v DSPs, but
I'm afraid that I will have to change to 3.3v ... or 2.5v or ...

  Cheers, Santiago (sanpab@eis.uva.es).
--------

Peter Alfke escribió:
> 
> Here is my personal opinion, not confirmed, edited or censored by Xilinx
> Marketing
> 
> It does not make any sense to use XC4000  parts for new design ( unless there
> are strange circumstances, like no 3.3-V supply available, which would be a
> weird situation today ).
> You get better price, performance, density with more modern parts.
> 
> Xilinx has a tradition of keeping the main-stream families in production for a
> long time.
> We obsoleted XC2000 only after >13 years in production. And we always give
> plenty of "last buy" warning, and then turn the die over to an "after-life
> supplier".
> I personally dislike the big XV parts, Virtex is so much better.
> And Spartan in any flavor beats XC5200 hands-down.
> 
> 5-V parts will bite the dust long before 3.3-V parts.
> 
> Always check software support, since it disappears earlier than the parts ( yes,
> you can always use old software, but who wants to?)
> 
> I often explain FPGA evolution as being at least 15 times faster than human
> aging.
> So,  Virtex being 3 years old,  is in its mid-life (bulging waist, hairline
> receding...), pushed along by the more virile Virtex-E.
> And any XC4000 is really a very senior citizen.  The original XC4000 was
> introduced ten years ago.
> But all these parts can live to be 200, they will just not be competitive.  :-)
> 
> We use rapidly declining prices on the new parts as an incentive to discourage
> you from starting anything with the old families, which cannot be price reduced,
> since their technology is stagnant.
> Old-technology wafers don't get any cheaper...
> 
> Just random thoughts.
> 
> Peter Alfke
> =======================================
> finish wrote:
> 
> > hello,
> >
> > with the outcome of virtex,virtex-e, virtex-II, should  we have the
> > right to still speak about Xc4k design ?
> > for how long will you expect the Xc4k to still exist?
> > which type precisely, E?,EX,XV
> > thanks

Article: 32542
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: johnjakson@earthlink.net (John Jakson)
Date: 29 Jun 2001 10:32:07 -0700
Links: << >>  << T >>  << A >>
More advice for would be engineer emigrants!

You should join with one of the major companies that regularly hires
in the quality Sunday papers. It will take maybe 6months from seeing
the advert to landing here or much much longer. Foreign hiring is
probably slow now so the phase is wrong. By the time you get here the
economy could have changed dramatically either way so take any offer
you are comfortable with.

When you get here, better companies will not let you go until you have
been here one year. If you should lose your job here, getting another
job on a H1 may still be ok, you can transfer it too another company,
(I did many times).

When you get here, you will find Brits all over the bloody place, but
they are invisible till they talk. Be aware of US UK english language
differences, as the saying goes, they own 80% of the stock. Learn
their strange words and you will be accepted quickly, you don't have
to change your accent (thats almost impossible), they luv brit accents
anyway (probably too much).

Remember all the advice you get is tainted, the INS rules & laws
change every 5mins, & half what you read will be innaccurate
(including here).

Don't quit your job in UK yet. If you lost your job get another EC job
(any tech job) asap. INS is looking to ok qualified applicants who are
working already with perhaps 5yrs exp or more.

Expect to make about 50% to 100% more on base salary & expect to spend
it in quite different ways. By and large, once foreign engineers have
settled here for a long time, they can usually be found at the top of
the salary curve in all the right places. Your UK BSc (Hons) is worth
more than a BS here but maybe less than an MS. Your math skills will
be much appreciated.

US companies in EC cannot easily transfer employees in EC to US with
out salary translation jealasy problems with those that remain. So
start on a clean slate with a new company.

If you are single go for it, if married with kids, it will really be
up to her, she probably won't be able to work for many many years
unless she can swing her own H1, she can expect to become very bored &
isolated. If you have local girlfriend, she won't be able to come.

New England (Boston) will be a much better fit for many EC people than
California or Texas (I have been all over the place) but CA & TX have
their charms & excitement too.

Regarding marriage, if you are US citizen or foreigner on H1 or any
visa not yet applying for Green card, you can marry whoever you want
from any country with little difficulty since US ciizens are 1st
class, and H1s are off the INS radar.

Once you file for or have a Green card, you are under the microscope,
you cannot marry your sweetheart from home without very long delays
for her (5 yrs or so), so marry before filing for permanent residence.

Be wary of marrying US girl unless it is the real thing.

Contact old buddies who already settled, advice will be never ending.

The very best of luck

JJ

Article: 32543
Subject: Re: Error to execute vcom.do in ModelSim XE5.3d
From: Ray Andraka <ray@andraka.com>
Date: Fri, 29 Jun 2001 17:46:16 GMT
Links: << >>  << T >>  << A >>
You are using a coregen macro with an earlier version of the library.  You need
to get and install the IP update per the instructions on the website.

JianYong Niu wrote:

> Hi, All:
>
> Here I need your brilliant suggestion:
>
> Errors occured when the vcom.do file was executed in ModelSim XE 5.3d, as
> follows:
>
> # -- Loading package standard
> # -- Loading package std_logic_1164
> # -- Compiling entity xlmult_core1
> # -- Compiling architecture behavior of xlmult_core1
> # ERROR: Could not find
> C:/modeltech_xe/xilinx/vhdl/XilinxCoreLib.mult_vgen_v2_0
> # ERROR: xlmult_core1.vhd(34): cannot find expanded name:
> xilinxcorelib.mult_vgen_v2_0
> # ERROR: xlmult_core1.vhd(34): Unknown field: mult_vgen_v2_0.
> # ERROR: xlmult_core1.vhd(59): VHDL Compiler exiting
> # ERROR: C:/Modeltech_xe/win32xoem/vcom failed.
> # Error in macro C:\MATLABR11\work\vcom.do line 26
> # C:/Modeltech_xe/win32xoem/vcom failed.
> #     while executing
> # "vcom -93 xlmult_core1.vhd"
>
> There is only mult_vgen_v1_0 in xilinxcorelib, but no mult_vgen_v2_0. Where
> can I find that mult_vgen_v2_0?  If it is a library update problem, where
> can I find the update file?
>
> I am using modelsim XE 5.3d with a starter's licence.
> Thanks
>
> Jianyong

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 32544
Subject: VHDL using Xilinx foundation
From: dpariseau@compuserve.com (David Pariseau)
Date: 29 Jun 2001 11:02:44 -0700
Links: << >>  << T >>  << A >>
I'm in the process of teaching myself VHDL using Xilinx's
Foundation software.  I've broken a larger design into 
smaller bits and am working on a baud rate generator at the
moment and am perplexed by some strange behavior.

The Vhdl program below checks out and synthesizes fine but
when I run it through the simulator the Init to ICount 
assignment flips the lines around connecting Init[15] -> 
ICount[0] and swapping all the lines accordingly.

I've tried various things to try and remedy this problem
but have been unable to make it work out???  

I've also tried to use the ieee.std_logic_1164.all and 
work.std_arith.all libraries to get around it, but for
some reason Xilinx can't find work.std_arith.all???

Any thoughts?

Thanks 
Dave Pariseau.
-----------------
library ieee;
use ieee.std_logic_1164.all;

entity BaudCounter is
    port (
        Init:  in  integer range 0 to 65535;
        Load:  in  bit;
        Reset: in  bit;
        Clki:  in  bit;
        Clko:  out bit;
        Clko2: out bit 
    );
end BaudCounter;

architecture BaudCounter_arch of BaudCounter is
signal ICount : integer range 0 to 65535;
signal BCount : integer range 0 to 65535;
signal HalfOn : bit;
begin
	process
	begin
		wait until (Clki'event and Clki = '1');
		
		if Load = '1' then
			ICount <= Init;
		elsif Reset = '1' then
			BCount <= ICount;
			HalfOn <= '0';
		elsif BCount = 0 then
			if HalfOn = '0' then
				HalfOn <= '1';
			else
				HalfOn <= '0';
				Clko   <= '1';
			end if;
			Clko2  <= '1';
			BCount <= ICount;
		else 
			Clko   <= '0';
			Clko2  <= '0';
			BCount <= BCount -1;
		end if;
		
	end process;
end BaudCounter_arch;

Article: 32545
Subject: Re: obfuscated tools
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Fri, 29 Jun 2001 18:07:26 GMT
Links: << >>  << T >>  << A >>
If you synthesize your VHDL, and have the synthesizer output a VHDL netlist
(usually used for function simulation), then this VHDL is functionally
equivalent to your original but highly obfuscated.  It will be more verbose
and slower, though.  It will make use of primitive libraries, in the case of
Xilinx, the UNISIM libraries.

-Kevin

"Goran Bilski" <goran@xilinx.com> wrote in message
news:3B3CA8E2.1B682B6B@xilinx.com...
> Hi,
>
> Do anyone know of a tool that obfuscate VHDL code?
>
> Thanks
> Göran Bilski
>
>



Article: 32546
Subject: Re: Asynchronous design in Virtex FPGA => sleepless nights
From: Andreas Schmidt <as@blueiguana.com>
Date: Fri, 29 Jun 2001 11:28:13 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------E6D700D15CCA0815D51FA40D
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<b>Dear Michael,</b>
<p>first of all please allow me the following question:
<p><b>Do you want sleepless nights?</b>
<p>I guess not...
<br>But you will have them you designing this way
<p>Michael wrote:
<blockquote TYPE=CITE>Hi,
<p>I am working on a minor project, trying to implement an asynchronous
design
<br>in a fpga.
<br>I've got at RC1000-PP with a Virtex 1000 fpga (from the Xilinx university
<br>program).
<p>The design flow is
<br>VHDL -> FPGA Compiler 2 (export edif) -> Xilinx Alliance 3.1i -> upload
<br>bit-file to fpga
<p>The asynchronous design is utilizing a bundled data protocol, that is,
a
<br>control- and data path. It is okay that the datapath is optimized,
but I
<br>have been fighting the tools to avoid optimization of the logic in
the
<br>control path.</blockquote>
Fighting with tools?!?
<br>If I understand you in the right way, you want to avoid optimization
to ensure a specific delay between the parts of your circuit.
<br>In my opinion it's the wrong mentality....
<br>you will have heavy problems during simulation....
<br>How do want to test this?!?
<p><b>You should work with the tools, not against them!</b>
<blockquote TYPE=CITE>&nbsp;
<p>1) On the controlpath I need several delay elements (each implemented
as an
<br>assymetric c-element in a LUT). Unfortunately the Alliance tool optimizes
<br>this delay path away, and replaces it with a wire.</blockquote>
=> I would do the same, clever tool...
<blockquote TYPE=CITE>&nbsp;</blockquote>

<blockquote TYPE=CITE>&nbsp;
<br>2) When I make an asynchronous ring (fifo with the output connected
to the
<br>input), the stages are optimized away, unless I map a controlsignal
from the
<br>stage to an output pad.</blockquote>
Now I understand you right....
<p>When I started to design at the end of 1989 digital circuits using Xilinx
<br>I made some errors of course but I did never things like this....
<p>What is the purpose of this?!?
<p>A person who deeply influenced me, when I started designing digital
circuits using Xilinx FPGA years ago, named
<br>it <b>INVITATION TO DESASTER </b>what you are doing...
<br>(it's not only a typical bloody beginner error)
<p>Please apologize my hard and brutal honest words:
<p><b>What you are doing is raping the software, hardware and the whole
design methodology...</b><b></b>
<p><b>The consequence of this will be:</b><b></b>
<p><b>What you design is what you get....</b><b></b>
<p><b>=> sleepless nights...</b><b></b>
<p><b>cul8r, AS (Andreas)</b>
<br><b>(as@asic.cc)</b>
<br><b></b>&nbsp;
<blockquote TYPE=CITE>&nbsp;
<p>Are there a way to pass on a don't touch statement through the edif
file, or
<br>prevent Alliance from doing any optimization?
<p>Regards,
<br>-=[ Michael Kristensen ]=[ mke@nospam.dk ]=-</blockquote>
</html>

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Content-Transfer-Encoding: 7bit
Content-Description: Card for Andreas Schmidt
Content-Disposition: attachment;
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begin:vcard 
n:Schmidt;Andreas
tel;cell:1-408-768-1088
tel;fax:1-510-687-0466
tel;home:1-510-687-1611
tel;work:1-510-687-0465x116
x-mozilla-html:TRUE
url:http://www.blueiguana.com
org:Blue Iguana Networks;Research & Development
adr:;;4019 Clipper Court;Fremont;CA;94538;USA
version:2.1
email;internet:as@blueiguana.com
title:Dipl.-Ing. / Senior Hardware Engineer
note;quoted-printable:private homesite:=0D=0A=0D=0Ahttp://www.asic.cc=0D=0A=0D=0A=0D=0Aprivate email address:=0D=0A=0D=0Aas@asic.cc
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--------------E6D700D15CCA0815D51FA40D--


Article: 32547
Subject: Re: IOB FF in Synplicity
From: Keith R. Williams <krw@attglobal.net>
Date: Fri, 29 Jun 2001 14:44:27 -0400
Links: << >>  << T >>  << A >>
In article <gr7mjt0b652u7ujjinhehq6r714bdr5n9i@4ax.com>, 
brian@shapes.demon.co.uk says...
> On Wed, 27 Jun 2001 09:13:20 -0400, Keith R. Williams
> <krw@attglobal.net> wrote:
> 
> >In article <9hb26c$jav$1@slb6.atl.mindspring.net>, 
> >austin@da98rkroom.com says...
> >> 
> >> > The xilinx
> >> > mapper will push the FF's to the IOBs if you set the IOB FF's option
> >> > appropriately provided the rules are met for the IOB FFs.
> >> 
> >> That's what I do.  It is the "pr -b" option to map:
> >> 
> >> map -pr b filename
> >
> >I've tried all of the above and it still appears the flops aren't 
> >getting pushed into the IOBs (this is a XCS40XL-BG256).  Map reports:
> >
> >   Number of External IOBs           190 out of 224    92%
> >      Flops:                           0
> >      Latches:                         0
> >
> >----
> >  Keith
> 
> map -pr b doesn't always map IOB flops.
> 
> Using my synthesis tool (Leonardo) I had a frustrating time getting the
> IO flops where I wanted them. If it doesn't happen right away, there
> will be a reason, somewhere, that prevents the mapping. Typically you
> express a desing that allows the mapping, but the synthesis tool
> optimises it into one that doesn't. And in my opinion the diagnostics
> are seriously lacking .... MAP probably knows why it can't move that FF
> into that IOB, but it isn't going to tell you...

> I have resorted to reading .edf files and comparing parts that worked
> with parts that don't. Typically: the individual output enables (ENBFF)
> have been optimised away leaving a single signal; or they have the wrong
> polarity (they must be active low); or the (INFF/OUTFF) flop was part of
> a chain that has been optimised into a SRL; or the (OUTFF) flop has been
> combined with an identical one whose output was used internally; or
> something like that.


Polarity?  Ouch!  My style is everything inside the package is 
positive, controls I design (I'm stuck with what I buy) outside the 
package are negative (hang over from years of TTL design).  Isn't that 
why I'm using a HDL?  Isn't that why the boss plunked down $50K for the 
tools? 
 
> Modifying the design into one that the synthesiser won't screw up has
> been, for me, a tedious and iterative process (not helped by the poor
> diagnostics)

...and I thought HDLs were intended to improve productivity.

> Keith: you could check your design for the abovementioned conditions
> (not an exhaustive list) and see if fixing them corrects the problem.

Keith has no time for this on my SpartanXL design now.  It's pretty 
much done and meets speed (hardware even works!) without moving the 
registers into the IOBs, even if it takes between 1.5 and 7 hours to 
run PAR. I'll have to keep this in mind with the Virtex-E.  I'm going 
to need all the speed I can get there.  

> XILINX: 
> 1) You could improve the MAP diagnostics to say why flops couldn't be
> mapped ... e.g. 
> <pin>: ENBFF - not mapped into IOB, shared enable signal.
> <pin>: OUTFF - not mapped into IOB, shared output signal.
> etc...

Amen! If I explicitly tell it I want FFs swept into IOB and explicitly 
code them, I sure want to know, *in neon*, if it can't or won't do what 
I tell it.
 
> Synthesis vendors: you could improve the behaviour (or at least
> diagnostics) to attributes/constraints (preserve_signal) etc. I have had
> mixed luck with these attrributes, and never quite gotten to the bottom
> of why. (somehow, the signal I was preserving was optimised away anyway.
> Do you need both "noopt" and "preserve_signal", or what?)

These tools are expensive.  I wouldn't have expected this.  In fact I 
*know* my registers were making it into the IOBs at one point.  Many 
things have changed though and I didn't notice the were no longer 
there.  Having to check each little flop on each PAR pass is going to 
make the job impossible. :-(

----
  Keith


Article: 32548
Subject: Re: IOB FF in Synplicity
From: Keith R. Williams <krw@attglobal.net>
Date: Fri, 29 Jun 2001 14:46:38 -0400
Links: << >>  << T >>  << A >>
In article <3B3B855C.C261D61@andraka.com>, ray@andraka.com says...
> The HDL analyst is an invaluable tool for looking at what the synthesizer
> produces.  The "technology view will tell you at a glance if synthesis made
> an IOB break the rules.  Still, better reproting either in the synthesis or
> in the xilinx mapper would be good things.

I have HDL Analyst.  It's very useful, but could be better.

----
  Keith 

Article: 32549
Subject: Converting character to integer in VHDL
From: Miika Pekkarinen <miipekk@cc.jyu.fi>
Date: Fri, 29 Jun 2001 22:39:10 +0300
Links: << >>  << T >>  << A >>
Hi!

I have a problem with VHDL: I have looked FAQs and even found 
similar questions on the web. Still I can't find out how to convert 
(ascii)characters to integer (or to std_logic_vector).

For example I have following code:
...
signal c: character;

-- (This can be seven bit wide vector too).
signal byte_out: std_logic_vector (7 downto 0);
...

Here I should put the character c to byte_out but I don't know how to do 
it...

...

I hope if anybody could help me.
-- 
...   .................................................   ...
. Name   : Miika Pekkarinen    ¤ ICQ  : 45609012            .
. E-Mail : miipekk@cc.jyu.fi   ¤ WWW  : www.ihme.org        .
'''                                                       '''




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