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Messages from 32600

Article: 32600
Subject: Re: VHDL using Xilinx foundation
From: Andreas Purde <purde@emt.ei.tum.de>
Date: Mon, 02 Jul 2001 09:48:12 +0100
Links: << >>  << T >>  << A >>
Hi David,

I don't think that the bits are swept. If you assign a value to Init
like Init <= X"1234" the '1' is the least significant block. Try using
"65535 downto 0" instead of "0 to 65535".

Hope this helps.

Andreas


David Pariseau wrote:

> I'm in the process of teaching myself VHDL using Xilinx's
> Foundation software.  I've broken a larger design into
> smaller bits and am working on a baud rate generator at the
> moment and am perplexed by some strange behavior.
>
> The Vhdl program below checks out and synthesizes fine but
> when I run it through the simulator the Init to ICount
> assignment flips the lines around connecting Init[15] ->
> ICount[0] and swapping all the lines accordingly.
>
> I've tried various things to try and remedy this problem
> but have been unable to make it work out???
>
> I've also tried to use the ieee.std_logic_1164.all and
> work.std_arith.all libraries to get around it, but for
> some reason Xilinx can't find work.std_arith.all???
>
> Any thoughts?
>
> Thanks
> Dave Pariseau.
> -----------------
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity BaudCounter is
>     port (
>         Init:  in  integer range 0 to 65535;
>         Load:  in  bit;
>         Reset: in  bit;
>         Clki:  in  bit;
>         Clko:  out bit;
>         Clko2: out bit
>     );
> end BaudCounter;
>
> architecture BaudCounter_arch of BaudCounter is
> signal ICount : integer range 0 to 65535;
> signal BCount : integer range 0 to 65535;
> signal HalfOn : bit;
> begin
>         process
>         begin
>                 wait until (Clki'event and Clki = '1');
>
>                 if Load = '1' then
>                         ICount <= Init;
>                 elsif Reset = '1' then
>                         BCount <= ICount;
>                         HalfOn <= '0';
>                 elsif BCount = 0 then
>                         if HalfOn = '0' then
>                                 HalfOn <= '1';
>                         else
>                                 HalfOn <= '0';
>                                 Clko   <= '1';
>                         end if;
>                         Clko2  <= '1';
>                         BCount <= ICount;
>                 else
>                         Clko   <= '0';
>                         Clko2  <= '0';
>                         BCount <= BCount -1;
>                 end if;
>
>         end process;
> end BaudCounter_arch;


Article: 32601
Subject: Re: IOB FF in Synplicity
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Mon, 02 Jul 2001 11:14:55 +0100
Links: << >>  << T >>  << A >>
On Sun, 1 Jul 2001 11:51:08 -0400, Keith R. Williams <krw@attglobal.net>
wrote:

>In article <upgrjt0auhdc19kfi5ek8iorvcqs1rg47u@4ax.com>, 
>brian@shapes.demon.co.uk says...
>> On Fri, 29 Jun 2001 14:44:27 -0400, Keith R. Williams
>> <krw@attglobal.net> wrote:

>> >> map -pr b doesn't always map IOB flops.

>> Of course... you already know that map.mrp tells you what has and hasn't
>> been migrated, at the level of each pin. Just not why...
>
>Why not why?  Now that I'm looking I can easily see that it's not doing 
>what I told it to.  

Xilinx? ... Peter?

- Brian


Article: 32602
Subject: Re: Xillinx WebPack PAR problem
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 02 Jul 2001 12:42:20 +0200
Links: << >>  << T >>  << A >>
"Leon Heller" <leon_heller@hotmail.com> writes:

> I've downloaded the Xilinx WebPack software, and am having problems with PAR
> for Spartan-II:
[snip]
> Has anyone else had this problem?

No, but we had similar problems. It seems like we lost some bytes
while downloading WebPack (without any kind of notification). I think
Xilinx should include a md5sum or similar, either on the server or in
the installation program itself..

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 32603
Subject: Re: Converting character to integer in VHDL
From: Edwin Naroska <edwin@ds.e-technik.uni-dortmund.de>
Date: Mon, 02 Jul 2001 13:22:22 +0200
Links: << >>  << T >>  << A >>
Hi,

Miika Pekkarinen wrote:

> Hi!
>
> I have a problem with VHDL: I have looked FAQs and even found
> similar questions on the web. Still I can't find out how to convert
> (ascii)characters to integer (or to std_logic_vector).
>
> For example I have following code:
> ...
> signal c: character;
>
> -- (This can be seven bit wide vector too).
> signal byte_out: std_logic_vector (7 downto 0);
> ...
>
> Here I should put the character c to byte_out but I don't know how to do
> it...
>

You may try:

    byte_out <= std_logic_vector(to_unsigned(character'pos(c), 8));

Note that you have in include "use ieee.numeric_std.all" to make
"to_unsigned" visible. See the VHDL FAQ

    http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#enum_integer

and

    http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#integer_bit_vector

for more info about the conversion.

--
Edwin





Article: 32604
Subject: Xilinx Foundation vs Foundation ISE?
From: "Andrew Bridger" <andrew.bridger@xtra.co.nz>
Date: Mon, 2 Jul 2001 23:38:28 +1200
Links: << >>  << T >>  << A >>
Hi,
I'm currently doing a design that targets an XCV400E FPGA.  Our company has
the Xilinx Foundation Express software(FPGA express synthesis) and the
Xilinx Foundation Base Express ISE software(FPGA express synthesis and XST
synthesis).  I would like to hear opinion on which toolset would be most
appropriate? which toolset(and compilier) do people prefer?

My understanding is that ISE is recommended for new designs.  Unfortunately
base express ISE does not support the XCV400E device so we would have to
purchase Xilinx Foundation Express ISE.  This is not necessarily a problem
but I will need to have some good reasons to go to management with given
that our 'non-ISE' tools already support the XCV400E.

I notice that foundation ISE can be command line driven but foundation
cannot.

Are there any really important differences?

Thanks
Andrew





Article: 32605
Subject: Re: Asynchronous design in Virtex FPGA => sleepless nights
From: "Hans Summers" <HansSummers@HotMail.Com>
Date: Mon, 2 Jul 2001 13:01:26 +0100
Links: << >>  << T >>  << A >>

Andreas, Asynchronous design is an interesting area. Unconventional but
interesting, and I think in some circumstances possibly superior results
could reward the perserverence required. Are you against asynchronous design
in general or the particular way Michael is considering implementing it in
an FPGA? If the latter, do you have any web links about how to successfully
do asynchronous design for FPGA's?

------------------
Hans Summers
http://www.HansSummers.Com



Article: 32606
Subject: Re: Converting character to integer in VHDL
From: "Randy" <randy.robinson@xilinx.com>
Date: Mon, 2 Jul 2001 08:37:35 -0600
Links: << >>  << T >>  << A >>
I was working on something several weeks ago, and realized how limited my
VHDL knowledge really is.  What is a good way to code up character strings
that you want to send to an LCD display?  The display has the ASCII
character set already stored, so the character strings are simply ASCII
strings.  Nothing I tried seemed to work.

I would like to define the alphanumeric strings somewhere is my VHDL, and
send the strings out to the display when appropriate.

RR

"Miika Pekkarinen" <miipekk@cc.jyu.fi> wrote in message
news:9hikn8$ovn$1@mordred.cc.jyu.fi...
> Hi!
>
> I have a problem with VHDL: I have looked FAQs and even found
> similar questions on the web. Still I can't find out how to convert
> (ascii)characters to integer (or to std_logic_vector).
>
> For example I have following code:
> ...
> signal c: character;
>
> -- (This can be seven bit wide vector too).
> signal byte_out: std_logic_vector (7 downto 0);
> ...
>
> Here I should put the character c to byte_out but I don't know how to do
> it...
>
> ...
>
> I hope if anybody could help me.
> --
> ...   .................................................   ...
> . Name   : Miika Pekkarinen     ICQ  : 45609012            .
> . E-Mail : miipekk@cc.jyu.fi    WWW  : www.ihme.org        .
> '''                                                       '''
>



Article: 32607
Subject: Re: Xilink WebPACK keeps removing a pin I want to keep.
From: hess@cs.indiana.edu (Caleb Hess)
Date: 2 Jul 2001 14:48:40 GMT
Links: << >>  << T >>  << A >>
In article <3b3f3669.292265555@news.zip.com.au>,
Dean <www@plexus-technologies.com> wrote:
>Just finishing my first design and using an XC9572-PC84. I have a clock
>input (PHI) which goes to a bufg primitive, and then that feeds a couple of
>AND gates. Problem is, when I run the software to get a file to burn, I get
>the following message:
>
>WARNING:nd201 - Removing unused input(s) 'phi'.  The input(s) are unused
>after optimization.
>
What are you using the AND gate outputs for? If the output is unconnected,
or simplifies to a logical don't care, then everything in front of it is
unused. If you want to retain the inputs, try adding the KEEP attribute to
them.

-- 
Caleb Hess						hess@cs.indiana.edu


Article: 32608
Subject: Re: Converting character to integer in VHDL
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Mon, 2 Jul 2001 17:08:30 +0100
Links: << >>  << T >>  << A >>
In article <9hq0va$3kd1@cliff.xsj.xilinx.com>, Randy
<randy.robinson@xilinx.com> writes
>I was working on something several weeks ago, and realized how limited my
>VHDL knowledge really is.  What is a good way to code up character strings
>that you want to send to an LCD display?  The display has the ASCII
>character set already stored, so the character strings are simply ASCII
>strings.  Nothing I tried seemed to work.
>
>I would like to define the alphanumeric strings somewhere is my VHDL, and
>send the strings out to the display when appropriate.

I may be missing the point here, but it seems to me that you can simply
send the ASCII values of the characters, one by one, to your display
or whatever.

This is easy if you have some way to convert a VHDL character into its
ASCII integer equivalent.  Fortunately, the designers of VHDL set up
the "character" data type so that this is rather easy:  just use the
'POS attribute.  Something like this:

function ASCII_byte(c: character) return std_logic_vector is
  variable ASCII_code: natural range 0 to 255;
begin
  -- Get the integer character code for the chosen character
  ASCII_code := character'POS(c);
  -- Now bash it into a hardware byte
  return std_logic_vector(to_unsigned(ASCII_code, 8));
end;

The 'POS function should be essentially "free" in synthesis, since
the characters will be represented as their ASCII codes anyhow.

HOWEVER, I just tried out some of this stuff in Leonardo Spectrum
and found there are some other considerations:

(1) Spectrum is quite happy for ports and signals to be of type
    character.  However, it won't swallow the obvious conversion
    in function ASCII_byte (above) on the grounds that it doesn't
    implement 'POS for variable arguments.
(2) So I got around this by building a table.  It's a bit of a 
    business, because the table has to be a constant that's
    initialised by a function;  the guts of it is

       type T_ASCII_Table is array character of natural;

       function makeTable return T_ASCII_TABLE is
         variable t: T_ASCII_TABLE;
       begin
         for c in character loop
           t(c) := character'POS(c);  -- OK because c is constant here
         end loop;
         return t;
       end;

       constant ASCII_Table: T_ASCII_Table := maketable;

(3) And then I could build a converter based on lookup in this
    constant table;  and Leo Spectrum happily synthesised it to
    eight wires, as required.  You need nerves of steel, because the
    RTL schematic shows a horrific lookup table thing; but since the
    table has data==address everywhere, the optimiser fixes it all OK.

Details are left as an exercise :-), and anyway someone else will
surely find a more elegant solution.  But it *is* possible.
Other synthesis tools may choke on different things - I don't have 
time to do an exhaustive trial.
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 32609
Subject: Re: Closest Xilinx equivalent to Altera EPF10KE?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 02 Jul 2001 18:27:46 +0200
Links: << >>  << T >>  << A >>
Paul Taylor schrieb:
> 
> Hello. Does anyone happen to know what the closest Xilinx
> alternative is to the Altera EPF10K100E FPGA?

Hmm, I would thinks something around SpartanXL or Spartan 2.

-- 
MFG
Falk



Article: 32610
Subject: Re: Xilink WebPACK keeps removing a pin I want to keep.
From: root@plexus-technologies.com (Dean Malandris)
Date: Mon, 02 Jul 2001 16:34:08 GMT
Links: << >>  << T >>  << A >>
On 2 Jul 2001 14:48:40 GMT, hess@cs.indiana.edu (Caleb Hess) wrote:

>What are you using the AND gate outputs for? If the output is unconnected,
>or simplifies to a logical don't care, then everything in front of it is
>unused. If you want to retain the inputs, try adding the KEEP attribute to
>them.

The outputs of the AND gates fed two lots of 24-bit counters. Oddly
enough, when I modified another (unrelated) part of the circuit, the
problem went away. I was using v3.2 of the software. I've since
upgraded to v3.3 just in case.

Article: 32611
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: Jan Tjernberg <jan.tjernberg@xilinx.com>
Date: Mon, 02 Jul 2001 09:54:14 -0700
Links: << >>  << T >>  << A >>
There used to be a way of keeping part of your credit
history when moving from Europe to the US.
It worked back in 1985, and perhaps it still works today.

If you have an American Express card (which is not
tied to a particular bank), you don't need to reapply for the
card when you change country. You make an address change instead,
and just  pay your card bill to a new address in the new country
in the new currency.

A while after moving to the US, my American credit records showed
that I had been an American Express customer for several years,
including my years as a cardholder in Sweden.

/ Jan


Phil James-Roxby wrote:

> > However you WILL
> > get a credit card from your US bank which is often set at 10% of your
> > income, or $5000, whichever is the lesser. Believe me, trying to do
> > business expenses on that kind of limit is a right pain in the arse.
> > Treat that card very carefully, dont go over 75% of the limit and
> > always pay the balance off. That will help to establish your credit
> > faster.
>
> > 5 - Due to (4) your chances of getting a fair rate mortgage seem to be
> > very low unless you put a SIGNIFICANT deposit down
>
> I have to disagree with Stuart on this point (but only this one)
> Stuarts reply should be regarded as a FAQ, though I think shed is a bit
> harsh :-)
> My US bank would not give me a credit card after being here for a year,
> but they would give me a fair rate mortgate without a huge deposit after
> we had been here for 2 months (the same bank!).  Similarly, I easily got
> a car lease without any fuss after we had been here less than a month!
> I guess my advice would be that all things are possible when it comes to
> finance, but it depends on getting the right person who is prepared to
> do a little more donkey work for you than the average Joe/Joanne.  This
> is more luck than judgement admittedly, but by talking to other ex-pats,
> you get to hear about these people.  Since they've jumped through the
> considerable hoops more than once, they seem happy to do it again.
> And wives/partners can work, they just can't get paid.  So voluntary
> work at the local dog pound etc. is still possible.  Its not like
> spouses _have_ to sit in the 'shed' all day.
> Phil
>
> --
> ---------------------------------------------------------------------
>  __
> / /\/  Dr Phil James-Roxby         Direct Dial: 303-544-5545
> \ \    Staff Software Engineer     Fax: Unreliable use email :-)
> / /    Loki/DARPA                  Email: phil.james-roxby@xilinx.com
> \_\/\  Xilinx Boulder
> ---------------------------------------------------------------------


Article: 32612
Subject: Re: Digital PLL, frequency multiplication: looking for problem : )
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Mon, 2 Jul 2001 19:45:48 +0200
Links: << >>  << T >>  << A >>
If you can get your ratio to something in the order of 1:20000000, then I'll
have an application for it.

Adrian

Thomas Lehner <thomas.lehner@contec.at> wrote in message
news:3b3c382c$1@e-post.inode.at...
> Something new:
>  I already _have_ the solution and am looking for a suitable problem now.
>
>  I found a way to multiply the frequency of a rectangular signal by any
> rational value. It works _continuously_ from 0 to say 100 MHz.
>
> Contiously means, that there is no lock-in range or similar behaviour. The
> output signal simply tracks the input as fast as possible.
>
> The output frequency can be higher or lower than the input frequency.
>
> Additionally a software filter can remove jitter present in the input
> signal.
>
>
>
> Currently I use it to write a pattern with variable resolution into a
> rotating role with a laser.
>
> A sensor gives 5000 pulses per revolution. My hardware enables the
customer
> to choose the resolution of the pattern freely. It can be e.g. 128312
pulses
> per revolution.
>
> The surface speed of the role is 20 m/sec and the accuracy of the points
is
> as high as 500 nm !! So the quality of the output signal is really very
> good.
>
>
>
> Unfortunately my customer sells his machines in a niche market.
>
> So I am looking for new applications.
>
>
>
> There _must_ be people out there having the same or a similar problem.
>
>
>
> Here some additional specs:
>
>
>
> Ratio : can be chosen by software between 1000000 : 1 and  1 : 1000000
> (integral steps)
>
> Output jitter: depends on hardware but can be as low as 1 ns.
>
> Reaction time: 10 us
>
>
>
>
>
> Do you know any applications for this technology ?
>
>
>
> Any help would be appreciated.
>
>
>
> With kind regards
>
>
>
>
> Thomas
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>



Article: 32613
Subject: High Speed Logic Board Designer needed
From: heather@cooperjohnson.com (Heather Cooper)
Date: 2 Jul 2001 13:22:02 -0700
Links: << >>  << T >>  << A >>
Location: Silicon Valley
Duration: Full Time
Salary: DOE
Contact: Heather Cooper
         Cooper | Johnson Recruiting, Inc.
-         415-257-4242
Company Bio:

This client is a leading developer of next-generation equipment for
network service providers.  Their goal is to solve the bandwidth
bottleneck found in today's metropolitan area networks by creating
carrier-class 10-gigabit Ethernet solutions.

Responsibilities:
Design and implement high speed logic boards for packet switch and
routing systems.


Education/Experience:

-10 years experience
-Familiar with memories including DDR SDRAM, SSRAM, and specialized
memories.
-Experience with pin I/O signaling of LVDS, LVPECL, HSTL, SSTL2. 
-Experience designing high speed circuits. 
-Experience with EMI issues and solutions. 
-Familiar with dense, high pin count connectors. 
-Knowledge of controlled impedance PCB design and materials. 
-Familiar with DC-DC power converters. 
-Experience with dense logic cell FPGAs. 
-Familiar with Verilog testbenches. 
-BSEE or equivalent experience
-SpectraQwest or HyperLynx, Cadence Concept, Allegro, Verilog

Article: 32614
Subject: FPGA Design
From: heather@cooperjohnson.com (Heather Cooper)
Date: 2 Jul 2001 13:23:22 -0700
Links: << >>  << T >>  << A >>
Location: Silicon Valley
Duration: Full Time
Salary: DOE
Contact: Heather Cooper
         Cooper | Johnson Recruiting, Inc.
-         415-257-4242
FPGA Design 


Company Bio:

This client is a leading developer of next-generation equipment for
network service providers.  Their goal is to solve the bandwidth
bottleneck found in today's metropolitan area networks by creating
carrier-class 10-gigabit Ethernet solutions.

Responsibilities:
Design and implement FPGA base logic to interface high speed switch
backplane to SONET.

Experience/Education:

-5+ years Experience designing with high density FPGA such as Altera
or Xilinx (Virtex).
-Experience with FPGA design tools including Verilog (preferred) or
VHDL, Synplicity, Exemplar, or Design Compiler, and vendor specific
Place and Route toolchains.
-Experience with packet based communications systems &#8211; LAN or
WAN.
-BSEE or equivalent

Article: 32615
Subject: Re: Xilinx Foundation vs Foundation ISE?
From: Tom Fischaber <Tom.Fischaber@xilinx.com>
Date: Mon, 02 Jul 2001 15:28:05 -0600
Links: << >>  << T >>  << A >>
Hi Andrew,

Here is my take on this... As you mentioned, one of the differences is that
Foundation ISE provides two synthesis tools (Express and XST), while Foundation
Express only provides FPGA Express. It is sometimes nice to run the same code
through different tools, as you will probably be surprised at how much results
can vary between synthesis tools. Additionally,  Foundation ISE focuses
specifically on the HDL flow (although it does have a built in schematic
capture tool), whereas the Foundation environment is really meant more for the
schematic flow (although it does have a synthesis flow built in). ISE is
recommended for all new designs, primarily because this will be the main GUI
going forward. Also note that the Xilinx 'back-end' tools (ngdbuild, map, par)
are the same in either case, and both tools have similar command line options
(just pull up a dos prompt and run your scripts that way). It really comes down
to a matter of what your design flow is. For example, Foundation comes with a
gate-level simulator, which is nice for schematic designs, but makes debugging
HDL difficult. ISE has a built in hook directly to Modelsim (which means you
would have to have a version of Modelsim or some other HDL simulator - or use
MXE), as well as a number of other features which makes doing HDL designs
easier.

Cheers,
Tom

Andrew Bridger wrote:

> Hi,
> I'm currently doing a design that targets an XCV400E FPGA.  Our company has
> the Xilinx Foundation Express software(FPGA express synthesis) and the
> Xilinx Foundation Base Express ISE software(FPGA express synthesis and XST
> synthesis).  I would like to hear opinion on which toolset would be most
> appropriate? which toolset(and compilier) do people prefer?
>
> My understanding is that ISE is recommended for new designs.  Unfortunately
> base express ISE does not support the XCV400E device so we would have to
> purchase Xilinx Foundation Express ISE.  This is not necessarily a problem
> but I will need to have some good reasons to go to management with given
> that our 'non-ISE' tools already support the XCV400E.
>
> I notice that foundation ISE can be command line driven but foundation
> cannot.
>
> Are there any really important differences?
>
> Thanks
> Andrew


Article: 32616
Subject: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 02 Jul 2001 22:57:29 +0100
Links: << >>  << T >>  << A >>


Magnus Homann wrote:

> Please don't post HTML.
>
> Homann
> --
> Magnus Homann, M.Sc. CS & E
> d0asta@dtek.chalmers.se

Oh I don't know, the text at least was a beautiful lavender colour even
if it was v. hard to read.



Article: 32617
Subject: Re: IOB FF in Synplicity
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 02 Jul 2001 23:04:30 +0100
Links: << >>  << T >>  << A >>


"Keith R. Williams" wrote:> XILINX:

> > 1) You could improve the MAP diagnostics to say why flops couldn't be
> > mapped ... e.g.
> > <pin>: ENBFF - not mapped into IOB, shared enable signal.
> > <pin>: OUTFF - not mapped into IOB, shared output signal.
> > etc...
>
> Amen! If I explicitly tell it I want FFs swept into IOB and explicitly
> code them, I sure want to know, *in neon*, if it can't or won't do what
> I tell it.
>
> > Synthesis vendors: you could improve the behaviour (or at least
> > diagnostics) to attributes/constraints (preserve_signal) etc. I have had
> > mixed luck with these attrributes, and never quite gotten to the bottom
> > of why. (somehow, the signal I was preserving was optimised away anyway.
> > Do you need both "noopt" and "preserve_signal", or what?)
>
> These tools are expensive.  I wouldn't have expected this.  In fact I
> *know* my registers were making it into the IOBs at one point.  Many
> things have changed though and I didn't notice the were no longer
> there.  Having to check each little flop on each PAR pass is going to
> make the job impossible. :-(
>
> ----
>   Keith

I've been working around this for some time by maintaining a list of what I
expect to see in the IOBs
and using a perl script to compare that with the last section of the MAP
report. The list, in fact, holds exceptions to the rule that everything is
registered onto & off the chip i.e. the default is to see INFF/OUTFF on an
input/output (or both on a bidir - the script parses the top level module to
get a list of the IOs).




Article: 32618
Subject: Re: Modelsim waveform
From: "Jason T. Wright" <Jason.T.Wright@Boeing.com>
Date: Mon, 2 Jul 2001 22:12:47 GMT
Links: << >>  << T >>  << A >>
I'm not familiar with the MaxPlus simulator, but for any VHDL or verilog
simulator, you can input text i/o in your test bench.  If your current
files are not in a usable format, you can script (or write a program) to
translate them into a format usable by the language.

Jason T. Wright

Clark Pope wrote:
> 
> I have just started using the ModelSim XE evaluation version. I am used to
> using MaxPlus for simulation. Is there an easy way to import "vector" files
> to act as stimulus for the modelsim simulator? I've written .m files to
> generate and read back .vec and .tbl files from Altera but I don't see any
> way to do this with Modelsim.
> 
> Alternatively, is there another way to get waveforms from matlab through
> Modelsim and back into matlab?
> 
> Thanks in advance,
> Clark Pope

-- 
Jason T. Wright

The opinions I express are my own ...
    unless otherwise indicated!

Article: 32619
Subject: Undocumemted Xilinx Tools
From: "Steve Casselman" <sc@vcc.com>
Date: Mon, 2 Jul 2001 16:41:51 -0700
Links: << >>  << T >>  << A >>
If you look in the Xilinx bin (xilinx/bin/nt on windows machines) directory
you'll find some undocumented tools. The ones I'm interested in are all the
blif tools. Is there any way to use these? Is there any documentation that
shows how to use these tools?

Thanks
Steve



Article: 32620
Subject: IPAD primitive is broken in exemplar xilinx verilog libraries?
From: husby_d@yahoo.com (Don Husby)
Date: 2 Jul 2001 17:44:45 -0700
Links: << >>  << T >>  << A >>
When I compile the following, I get warning messages
from exemplar:
"XX.v",line 4: Warning, N is never assigned a value.
"XX.v",line 3: Warning, P is never assigned a value.

Probably becuse IPAD is defined as having an input pin
instead of an output pin.  The reulting design gets
optimized away, even with the KEEP attributes.

Is there a fix for this?
Or is there another way to instantiate pads in lower
levels of a design heirarchy?


======== Source code ======

module IN_LVDS(I);
  output I;
  wire   P;  //exemplar attribute P KEEP
  wire   N;  //exemplar attribute N KEEP
  IPAD   P_Pad(P);
  IPAD   N_Pad(N);
  IBUFDS Buf(.O(I), .I(P), .IB(N)); //exemplar attribute Buf LVDS_25 
endmodule

module OUT_LVDS(O);
  input O;
  wire  P, N;
  OBUFDS Buf(.I(O), .O(P), .OB(N)); //exemplar attribute Buf LVDS_25
  OPAD   P_Pad(P);
  OPAD   N_Pad(N);
endmodule

module Top();
  wire  xyzzy;
  IN_LVDS  In_Pad(xyzzy);
  OUT_LVDS Out_Pad(xyzzy);
endmodule

============================

Article: 32621
Subject: Re: Asynchronous design in Virtex FPGA => sleepless nights
From: Ray Andraka <ray@andraka.com>
Date: Tue, 03 Jul 2001 00:48:53 GMT
Links: << >>  << T >>  << A >>
Properly done async logic doesn't depend on the delay differences between
signals, but then I have seen very few people that know how to do this
correctly.  With that in mind, a properly done async design can be accomplished
in an FPGA, but it requires circumventing the tools so that they don't do things
like removing cover terms (BTW, the whole concept of cover terms has different
meaning in an FPGA, since the cover terms have to be in physically separate
LUTs).  The design really has to be done on a LUT basis rather than on a gate
basis to adequately address the static and dynamic hazards.  The tools do not
directly support this.

The more common async designs, those done by well meaning but yet to be really
bitten engineers, generally have logic that depends on differential delays to
resolve race conditions.  These circuits are downright dangerous in FPGAs
because the routing represents a large share of the overall signal propagation
delay, and that routing changes depending on the circuit, the pinouts, and a
random seed.  These reace condition dependent circuits also can fall victim to
changes in circuit speeds due to process changes or variations from part to
part.

The timing analysis tools are also designed for synchronous logic, in fact they
purposely break combinatorial loops before beginning the analysis.  This means
that you need to do your timing analysis by hand in order to verify the timng of
your design.  Additionally, there is considerably more analysis required to
adequately verify an async design.  Synchronous design has the advantage of
eliminating such trouble spots as race conditions and logic hazards, which all
need to be properly analyzed for an async design.

So, async design can be done in an FPGA, but you should make darn sure that 1)
you know what you are doing, and 2) that you have enough time built into your
schedule to do the proper analyses on your design.




Hans Summers wrote:

> Andreas, Asynchronous design is an interesting area. Unconventional but
> interesting, and I think in some circumstances possibly superior results
> could reward the perserverence required. Are you against asynchronous design
> in general or the particular way Michael is considering implementing it in
> an FPGA? If the latter, do you have any web links about how to successfully
> do asynchronous design for FPGA's?
>
> ------------------
> Hans Summers
> http://www.HansSummers.Com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 32622
Subject: poor man's floating point...
From: dpariseau@compuserve.com (David Pariseau)
Date: 2 Jul 2001 17:58:11 -0700
Links: << >>  << T >>  << A >>
I'm using the Xilinx Foundation tools which don't
support floating point and I need to do simple
floating point conversion of a timer output in order
to pack it into a smaller number of output bits w/o
losing resolution at the low end.

Specifically I want to take a 27 bit counter and
pack it into a 16 bit output (4 bits of exponent
and 12 bits of mantissa).

Basically what I want to do is look at the highest
order bit set in the 27 bit counter and then set
the 4 bits in the output accordingly and shift and
copy the 27 bit value into the 12 bits based on
which bit is set.

Basically I want to achieve something like what I've
outlined below.  Is there a way to do this?  I've tried
all kinds of combinations and variations unsuccessfully
thus far.

Thanks for any help or insight.

Dave Pariseau
----------------------
entity FloatTime is
    port (
        Calc:  in  std_logic;			-- Calc new time
        BTime: in  unsigned(26 downto 0);	-- Binary time in
        FOut:  out unsigned(15 downto 0)	-- Floating point time out
    );
end FloatTime;

architecture FloatTime_arch of FloatTime is
begin
	process
	begin
		wait until (Calc'event and Calc = '1');

		FOut <= 0;
		case BTime'(highest bit set) is
		when 26 =>
			Fout <= x"F000" & (BTime shift -> 15);
		when 25 =>
			Fout <= x"E000" & (BTime shift -> 14);
		etc...		
		when others =>
			Fout <= x"0000" & (BTime shift -> 0);
		end case;
				
	end process;	
end FloatTime_arch;

Article: 32623
Subject: Re: XC9500 drive capability
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 03 Jul 2001 07:22:36 +0100
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> Yes, it works. All these output structures are almost the same.
> The issue is to what extent the current divides equally between
> the two drivers. And if they have the same basic characteristic,
> and are adjacent on the die, they track very well.
>
> Peter Alfke, Xilinx Applications
>
> Vitali wrote:
>
> > Hello,
> >
> > can I double current sink capability by tying two output pins?
> > I know it runs on FPGAs (on "senior" XC4000s). How about CPLDs?
> >
> > Thanks
> >
> > Vitali.

How can you tell which IOs are next to each other on the die for an
XC95K part ? For Virtex devices you can get this info from a .par report
file.


Article: 32624
Subject: Re: poor man's floating point...
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Tue, 03 Jul 2001 06:55:02 GMT
Links: << >>  << T >>  << A >>
On 2 Jul 2001 17:58:11 -0700, dpariseau@compuserve.com (David
Pariseau) wrote:

>Basically what I want to do is look at the highest
>order bit set in the 27 bit counter and then set
>the 4 bits in the output accordingly and shift and
>copy the 27 bit value into the 12 bits based on
>which bit is set.
>
>Basically I want to achieve something like what I've
>outlined below.  Is there a way to do this?  I've tried
>all kinds of combinations and variations unsuccessfully
>thus far.

There is no reason why you shouldn't be able to do what you want. I
think your problem is with specification, or lack thereof. I am not
clear on what you want and I think neither are you. If you can write
what you want to happen to bits in a detailed way step by step, you
can implement it. Forget VHDL; document what you want in any notation
you are comfortable with and then convert to VHDL. If you need help at
that time, ask in c.l.vhdl.

PS what you want sounds like A-law or U-law companding in voice
communications. Check them out.

PPS remember that floating point can not represent all numbers in its
range. Some integers in the 27 bit range will be missed in the 16 bit
format. Make sure that you can handle that case.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com



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