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For the normalization, as Philip points out, you'll want to follow a straight binary counter with a normalizing barrel shift. A normalizing barrel shift doesn't need a priority encoder at all, provided you do the shifting in steps using an optimal merged tree architecture. Instead of a priority encoder, you arrange the barrel shift as multiple layers of 2:1 shifts so that the first layer either passes the input unchanged or shifts it up (in your case) by 8 bits depending on whether any of the top 8 bits are set or not. The next layer either passes the result from the previous stage unchanged or shifts it up by 4 bits, depending on whether any of the top 4 bits presented to this shift stage are set or not. The following two stages shift by 2 and 1 respectively looking at the bits from the previous stage for controlling the shift. This structure consists of 23 2:1 muxes plus an 8 input (you actually only need 4 inputs if you trim the tree correctly) OR gate in the first layer, 19 2:1 muxes plus a 4 input OR in the second, 17 2:1's and a 2 input OR in the 3rd, and 16 2:1's in the 4th. If you need the exponent as well (the number of bit positions you shifted), you just take the mux controls (the shift decisions) from each layer to form a 4 bit exponent. Viola, no explicit priority encode, about 80% of the LUTs needed for just the 16 12:1 muxes you'd have otherwise, plus it is easily pipelined. The 16 12:1 muxes would take up 3 virtex slices each, assuming you use the f5 muxes, totalling 48 slices just for the muxes, compared with about 39 slices total for the merged tree using no F5 muxes. Philip Freidin wrote: > So the function you are asking for is called normalization. Using the > restricted resolution (in your case, 12 bits) to represent the largest > range ( in your case 0 .. (2^28)-1 ) with the most acuracy . For > numbers between 0 .. 4095 you get all integers, for numbers > between 4096 .. 8191 you get every second integer. For > the numbers between 8192 .. 16383 you get every 4th, .. etc. > > The structures you need are a circuit to find the position of the > first bit set, starting at the MSB of the 27 bit input. A common circuit > for this is a priority encoder. > > For the selection operation (you call it a shift), you could implement > this with 12 multiplexers, each with 16 inputs. All the muxes have > their select code coming from the priority encoder. This structure is > usually called a barrel shifter. > > Note that there is a common optimization, that assumes that since > you are always shifting the number so that the most sig 1 in the 27 > bit number ends up in the MSB of your 12 bit mantissa, the result of > normalization will always have that bit set. therefore, shift 1 extra > bit position, and throw away the '1' . You effectively end up with > a 13 bit mantissa, using 12 bits. This is called the hidden '1' > normalization. In your case, you would lose the ability to store > the numbers 2047 .. 1. '0' is usually special cased. > > Philip Freidin > > On 3 Jul 2001 11:11:40 -0700, dpariseau@compuserve.com (David Pariseau) wrote: > >Actually I do know exactly what I want to do but I probably didn't > >do a great job of explaining it. It's somewhat similar to companding > >but it's exactly floating point notation. > > > >I want to start with a value that's 27 bits wide... > > BTime <something>(26 downto 0) > >and stuff the manipulated value into a value that's 16 bits wide... > > FOut <something>(15 downto 0) > > > >The upper 4 bits of FOut specify the resolution of the LSB > >1111 FOut lsb is bit 15 of BTime > >1110 FOut lsb is bit 14 of BTime > >... > >0001 FOut lsb is bit 1 of BTime > >0000 FOut lsb is bit 0 of BTime > > > >The lower 12 bits of FOut start at the bit selected above and > >work up for 11 more bits (the msb of this 12 bit value will > >always be set except when the exponent is 0000 giving us the > >maximum resolution for any value represented, w/o needing all > >the bits, which for my purpose I really only need at the bottom > >end). > > > >So technically what I want to do is find the highest bit set in > >BTime, then set the exponent in FOut (upper 4 bits) accordingly > >and shift BTime the appropriate bits right before copying the > >lower 12 bits into the bottom of FOut (or the equivalent, a shift > >isn't probably the way to do it). > > > >Any thoughts? > > > >Dave. > > Philip Freidin > Fliptronics -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32651
No, self timed is a special case. A ripple counter does meet my criteria of not depending on differential delays. It, as you know, uses outputs from one stage as a clock to the next. FPGAs do support this construction, but again, timing analysis of it can be a nightmare. There are times when it makes sense, especially when striving for ultra low power. Back in the days of the xc2000, I used ripple counters quite a bit because of the small size of those arrays and because they did not have a carry chain like the new devices do. Note that the ripple counter is not just a ripple carry...it uses the q of one bit to clock the next (this is quite different than a ripple carry, which is the construction of the carry chains in current devices). glen herrmannsfeldt wrote: > Ray Andraka <ray@andraka.com> writes: > > >Properly done async logic doesn't depend on the delay differences between > >signals, but then I have seen very few people that know how to do this > >correctly. With that in mind, a properly done async design can be > >accomplished in an FPGA, but it requires circumventing the tools so > >that they don't do things like removing cover terms. > > I think what you mean is also called self-timed logic. While I like > the term asynchronous logic, it does have other meanings. For > example, the common counter with ripple carry is called an > asynchronous counter, but it not what you are trying to describe. > > It might be that such asynchronous logic is a lost art by now. > > -- glen -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32652
50%+ for routing delays is fairly typical. You can reduce that substantially by judicious floorplanning and watching the fanout. In the case of the coregen multipliers, a floorplan change can net a small improvement of about 5-10%, and a logic change to reduce the fan-in can do alot more at the cost of area. The multiplier has connections from the A input to 6 gated adders, which is to say a fairly high fanout into carry chain logic (which is usually the critical path). The layout puts these input adders next to each other and the adder tree fairly far away. As a first step, register the multiplicands immediately before the multiplier, and then floorplan it to put those registers for the A inputs vertically next to the input adders in the multiplier, and the B input registers under the columns they drive. You can unbind the mutliplier macro in the floorplanner too, which will let you get the A registers closer to the input adders. Phil Hays wrote: > David Nyarko wrote: > > > > Hi, > > I used the Xilinx system generator to implement > > a 12 bit by 12 bit signed multiplier with no pipelining > > or latencies. > > I then used Synplify, the P&R tools and the Timing analyzer, > > > > The only constraint entered in synplify was a clock speed > > of 50Mhz. > > > > The Timing analyzer indicated a maximum delay (maximum combinational > > path delay) of 19.935ns on a path containing 13 levels of logic. > > This time consists of 10.038ns logic and 9.897ns route. > > > > Does route mean the routing (connections between LUTs)? > > If this is true, is it typically that high (in this case > > it is 49.6% of the total time delay). > > 60% or more route delay isn't uncommon on the worst case path, especially in a > non-floorplanned design of significant size. It's interesting to me that this > has not changed much over the past decade, even as the parts have gotten much > bigger, much faster, and have more routing resources. > > -- > Phil Hays -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32653
"Jamie Sanderson" <jhks@earthling.net> wrote in message news:Wmv07.87397$Mf5.25048793@news3.rdc1.on.home.com... > I'm amazed no one has taken Stuart to task for this comment. I wonder how > his co-workers at Synopsys feel about it? My apologies, I've just remembered I mixed up Synopsys with Mentor Graphics (Exemplar). Cheers, JamieArticle: 32654
>And I agree with Eric that I don't think you can copyright an >instruction set architecture. I think I remember a discussion about copyrighting the mnenomics for the instructions. I forget the context. Makes sense though. (But I'm not a lawyer.) -- These are my opinions, not necessarily my employeers. I hate spam.Article: 32655
VhdlCohen wrote: > Posted for Clifford E. Cummings > --- > The arguments for and against permitting initializing with initial blocks > in synthesizable code are nicely laid out in Ben's e-mail message. > > GENERAL CASE > Initial blocks should NOT be synthesizable. Some synthesis tools, like > Synplicity, ignore initial blocks. This is almost criminal! An ignored > initial block means that the initial block is providing information to the > simulator that is ignored by the synthesis tool. This can cause a mismatch > between pre- and post-synthesis simulations. > > All initial blocks should be flagged as errors by synthesis tools > (possible alternative discussed below). Users of any synthesis tool that > ignores initial blocks should bitterly complain to their tool vendor. > The Verilog LRM defines `initial' as an `optional-abort' construct: "The following constructs may cause simulation and synthesis models to mismatch. If the tool determines such a situation it must abort rather than generate output ..." So Synplify's behaviour is a violation of the existing spec. - but try convincing the support line of this! <snip> Regarding your comments re power-on initialisation. Nice though it is I feel its actually very dangerous since it presents a hidden gotcha if you want to go from FPGA to ASIC. Xilinx: One for the wish list - Please give me some way of disabling this e.g. tying the GSR input of the STARTUP block to 0.Article: 32656
Hal Murray wrote: > >And I agree with Eric that I don't think you can copyright an > >instruction set architecture. > > I think I remember a discussion about copyrighting the mnenomics > for the instructions. I forget the context. Makes sense though. > (But I'm not a lawyer.) But enforcing a copyright on the mnenomics of the assembler means that there will be no gnu compiler for the architechture. Would be a bad idea for someone like MIPS. And you would still be able to builld a processor for ISA protected like that by doing any of the following: - port your own compilier suite and use different mnemonics. - have your users buy the original compiler suite. - find a mnenomic that was used by someone else first (like ADD ;-) and license it. Then you can try to enfore this copyright and settle the case by exchanging licenses. Kolja SulimmaArticle: 32657
Rick Filipkiewicz <rick@algor.co.uk> writes: > Magnus Homann wrote: > > > Please don't post HTML. > > > > Homann > > -- > > Magnus Homann, M.Sc. CS & E > > d0asta@dtek.chalmers.se > > Oh I don't know, the text at least was a beautiful lavender colour even > if it was v. hard to read. Well, my newsreader don't understand HTML, so I couldn't read it at all. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 32658
Greetings Third issue of Chip-Guru online design magazine is ready. Please visit http://chip-guru.com/ to read it. Add your comments and accolades in feedback section. A new section on technical cartoons is added in this issue. Please send me a brief summary of your article/paper if you wish to contribute to this magazine. Regards Rajesh Bawankule rajesh52@hotmail.comArticle: 32659
Hi,
Gonzalo Arana wrote:
> Hi,
>
> Does anybody has, knows who has a RS232 UART coded in VHDL?
> Thanks in advance,
>
You may take a look at the VHDL FAQ at
http://www.vhdl.org/comp.lang.vhdl/ .
Section 4.9 (part 1) lists a couple of VHDL models (including some UART
designs).
--
Edwin
Article: 32660Hi, try www.opencores.org michael strothjohannArticle: 32661
Hi All, I have a problem with verification of configuration of ACEX 1K (or APEX) Altera devices. The problem is that device after configuration is submitted to different enviromental stresses (eg. radiation or EMI), and I need to evaluate the probability of disconfiguration in particular conditions. I can do that by varifying the configuration eg. each minute. Unfortunately, I was unable to find anything (eg. in AN39 or AN116) about the reading of SRAM device configuration. There is "ACTION READ" instruction in STAPL specification, but is it supported by ACEX and APEX Alteras? Thank you in advance Wojciech Zabolotny wzab@ise.pw.edu.pl http://freehdl.seul.org Check the FREE VHDL simulator...Article: 32662
Thanks to Nicholas and Jonathan I've managed to get my module working by
putting all the statements that would control one output into the same
process. By the way I also found out that I could not use the function
"rising_edge()" twice in the same process. An example is shown below:
process (A, B) is
begin
if rising_edge(A) then -- line A
-- do something here
end if;
if rising_edge(B) then -- line B
-- do something here
end if;
end process;
My workaround was to replace line "A" and "B" with "if A = '1' then" and "if
B = '1' then. Is this a limitation of Foundation 1.5 or its a physical
limitation?
Article: 32663
In article <3B42E9BA.6A04B1E8@le.ac.uk>, Royan Ong <hlro1@le.ac.uk>
writes
>Thanks to Nicholas and Jonathan I've managed to get my module working by
>putting all the statements that would control one output into the same
>process. By the way I also found out that I could not use the function
>"rising_edge()" twice in the same process. An example is shown below:
>
>process (A, B) is
> begin
> if rising_edge(A) then -- line A
> -- do something here
> end if;
>
> if rising_edge(B) then -- line B
> -- do something here
> end if;
>end process;
>
>My workaround was to replace line "A" and "B" with "if A = '1' then" and "if
>B = '1' then. Is this a limitation of Foundation 1.5 or its a physical
>limitation?
AARGH!
It's about the way synthesis interprets a process; and it's also
about the way hardware works.
Are you seriously trying to tell me that your RS FF is truly
edge triggered? If so, please publish your proposed schematic
double-quick, but I suggest that you patent it first....
Think very carefully about what will happen in the following
situations: (these are timing diagrams, if you'll accept them)...
First, let's look at the easy case. First A goes high, clearing Q;
then, separately, B goes high, setting it:
A 000111000000000
B 000000000111000
Q xxx000000111111
This would have worked the same way regardless of whether it's edge
or level triggered. But what happens if both are active together?
In your code, input B takes precedence. So...
A 00001111100000
B 00001100000000
a b
Q 000011????????
At point "a", you have rising edges and high levels on both A and B;
B wins, so Q is set.
At point "b", you have A only asserted; but NO rising edges anywhere.
Do you want A to kick in at this point, and do the reset? I guess so.
In which case, your "rising_edge" formulation wouldn't work.
So it isn't just Foundation (actually Synopsys FPGA Express) being
bolshie; it's right! There is a "limitation": no synthesis tool
that I'm aware of knows how to create flip-flops that are triggered
by more than one sort of clock edge, mainly because it's pretty
tough to find any such technology.
Your test for A='1' or whatever, as I outlined before, is right.
Get a copy of "VHDL for Logic Synthesis" by Andrew Rushton, or else
Mark Zwolinski's book on VHDL (can't remember the name right now,
but a search for the author name should find it easily) and find out
about "synthesisable process templates".
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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the addressee only. If you are not the intended recipient please delete it
from your system, any use, disclosure, or copying of this document is
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are not the views of Doulos Ltd., unless specifically stated.
Article: 32664> Are you seriously trying to tell me that your RS FF is truly > edge triggered? If so, please publish your proposed schematic > double-quick, but I suggest that you patent it first.... Well its not that hard really... just put an edge detector at the inputs and you can trigger the RS FF at the rising or falling or both clock edges only. I've done it and it only uses a couple of extra logic gates. > This would have worked the same way regardless of whether it's edge > or level triggered. But what happens if both are active together? > In your code, input B takes precedence. So... > > A 00001111100000 > B 00001100000000 > a b > Q 000011???????? > > At point "a", you have rising edges and high levels on both A and B; > B wins, so Q is set. > At point "b", you have A only asserted; but NO rising edges anywhere. > Do you want A to kick in at this point, and do the reset? I guess so. > In which case, your "rising_edge" formulation wouldn't work. Well honestly I did not think of this situation... but it was not necessary cause A and B can never change state at the same time and both A and B are pulses that are always only lo (but I'm well aware of race conditions with FF and so on). Anyway I created my circuit from schematic before trying to describe it in VHDL! I'm new to VHDL but have been designing schematics for quite a while. Thanks for your advice on the books too and I'll get it ASAP.Article: 32665
Hi I have Xilinx Student Edition 2.1 and am lookung for some VHDL projects to build for practic and to learn. Any good project with VHDL code and circuit board schematics would be appreciated. They could me E-mailed to mpbrown@magma.ca ThanksArticle: 32666
Hi all,
In "VHDL reference manual"/1/ is printed an example to use resolution
functions for WIRED AND. This example will not work correct .
Simulator print out the follwing warning:
Warning 9242: More then one normal (Totem_Pole) output in the
following node:
NODE: C0.O, C1.O, C2.I, N_Y.
This warning can be eliminated with an flip-flop at signal 'Z'. The
result of this code is listed in follwing table:
x y | z
-----+---
0 0 | 0
0 1 | 1
1 0 | 0
1 1 | 1
When the input is also latched, the synthesis will print out the
following error:
Error: The net '/ver1/c' has more than one driver. (FPGA-CHECK-5)
I coded the same function as follows and it works:
u1: pullup port map(c);
c <='0' when a='0' else 'Z';
c <='0' when b='0' else 'Z';
Where is the Problem? I think its the same function, only an other
description.
Sven
I use Xilinx Foundation 3.3i
/1/ FPGA express/FPGA compiler ii VHDL Referenz Manual
/express/help/vhdlref.pdf
Article: 32667I notice that some of the development boards e.g. xess and burched use the 8031 microcontroller. I am wondering why the older 8031 is used instead of the 8051?? I personally would like to learn to assembly program for the 8051 instead so would it be a waste to order one of these boards and end up knowing code for the inferior 8031? Maybe its not too bad if the 8031 is used widely in industry, how widely used is the 8031? How good are these boards versus the ones from xilinx? From an education standpoint, i.e. to learn fpga design, are they adequate? or should I just pay the extra cash and get the ones from xilinx? ThanxArticle: 32668
On 4 Jul 2001 07:49:54 -0700, throne7@my-deja.com (SN) wrote: >I notice that some of the development boards e.g. xess and burched >use the 8031 microcontroller. I am wondering why the older 8031 is >used >instead of the 8051?? I personally would like to learn to assembly >program >for the 8051 instead so would it be a waste to order one of these >boards >and end up knowing code for the inferior 8031? Maybe its not too bad >if the 8031 is used widely in industry, how widely used is the 8031? > >How good are these boards versus the ones from xilinx? From an >education standpoint, i.e. to learn fpga design, are they adequate? or >should I just pay the extra cash and get the ones from xilinx? Thanx The 8031 and the 8051 have the same architecture. The differences won't be significant for your application (unless you can change the program in a mask rom ;-) I believe that you'll find that the boards that have "8051" parts on them actually have 8031 chips. Read the 8051 FAQ: http://www.faqs.org/faqs/microcontroller-faq/8051/ Regards, Allan.Article: 32669
In article <c2ec2c5b.0107040649.522dca1e@posting.google.com>, throne7 @my-deja.com says... > I notice that some of the development boards e.g. xess and burched > use the 8031 microcontroller. I am wondering why the older 8031 is > used > instead of the 8051?? I personally would like to learn to assembly > program > for the 8051 instead so would it be a waste to order one of these > boards > and end up knowing code for the inferior 8031? Maybe its not too bad > if the 8031 is used widely in industry, how widely used is the 8031? The 8031 is an 8051 with no (or disabled) on board code memory. They're the same processor, same instruction set. ---- KeithArticle: 32670
> I'm amazed no one has taken Stuart to task for this comment. I wonder how
> his co-workers at Synopsys feel about it?
Jamie,
Why not just let Stuart blither and talk? Let him get it out of his
system. Soon enough he'll find out that there are damn good and damn bad
engineers on each side of the ocean. If he continues, then he'll be doing
just what Cornwallis was doing on his way to Yorktown.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
Article: 32671In comp.arch.fpga SN <throne7@my-deja.com> wrote: > I notice that some of the development boards e.g. xess and burched > use the 8031 microcontroller. I am wondering why the older 8031 is An 8031 is a ROM-less 8051, the core is the same. ;-) Maybe you are thinking of the predecessor to the 8031/51- the MCS-48 (8035, 8039, 8048, 8049). Best regards, -- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Spehro Pefhany --"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com Contributions invited->The AVR-gcc FAQ is at: http://www.BlueCollarLinux.com =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=Article: 32672
Hi, if a='0' and b='0',C will be written twice at the same time,which is not allowable.C is like the bus signal,each time only one driver can talk to the bus.Otherwise it will result in chaosity. Use if else can avoid such problems. sincerely ------------- Kuan Zhou ECSE department On 4 Jul 2001, Sven Blankenberg wrote: > Hi all, > > In "VHDL reference manual"/1/ is printed an example to use resolution > functions for WIRED AND. This example will not work correct . > > Simulator print out the follwing warning: > > Warning 9242: More then one normal (Totem_Pole) output in the > following node: > NODE: C0.O, C1.O, C2.I, N_Y. > > This warning can be eliminated with an flip-flop at signal 'Z'. The > result of this code is listed in follwing table: > > x y | z > -----+--- > 0 0 | 0 > 0 1 | 1 > 1 0 | 0 > 1 1 | 1 > > When the input is also latched, the synthesis will print out the > following error: > > Error: The net '/ver1/c' has more than one driver. (FPGA-CHECK-5) > > I coded the same function as follows and it works: > > u1: pullup port map(c); > > c <='0' when a='0' else 'Z'; > c <='0' when b='0' else 'Z'; > > Where is the Problem? I think its the same function, only an other > description. > > Sven > > I use Xilinx Foundation 3.3i > > /1/ FPGA express/FPGA compiler ii VHDL Referenz Manual > /express/help/vhdlref.pdf > >Article: 32673
Has anybody used a programmable clock frequency synthesizer to generate the clock signal for an FPGA ? Required range 20 - 100 MHz. Any recommendations or "hands off" ? Manfred --Article: 32674
[ Not certain if this is the most appropriate group to post this message, could only find this fpga related newsgroup ] I have Xlilinx XCV50E for which I have bitstream file (.XBN), that I want to download. I am using a ALTERA CPLD to send this bitstream to the FPGA. Platform is running Linux (2.4.2) on Motorola 860 processor. I am writing a driver to send this file to the FPGA The basic quesiton I have is, when I am clocking this bitstream to the FPGA, as I read the byte from a file, should I be shifting the bits MSB first or LSB first? Also is there a .h file that describes format of bitstream header? i.e. not the entire bitstream just the header of the bitstream. BTW is there Linux driver already to send bitstream to a Xilinx Virtex FPGA? /Subodh Nijsure
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