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Messages from 32675

Article: 32675
Subject: How to estimate the number of CLBs ?
From: vhdl <vhdluser@MailAndNews.com>
Date: Wed, 4 Jul 2001 14:44:00 -0400
Links: << >>  << T >>  << A >>
I'm targeting Virtex II, I need to have an estimate for my design.
I didnot entered in Xilinx tools. But I want to know
like an adder 12bits, a multiplier 12x12 bits, a flip-flop
How many CLBs they use ? is there a data book/sheet with
estimate of chip area used by library element ?

VhdlUser


Article: 32676
(removed)


Article: 32677
Subject: Re: Downloading FPGA (XBN) bitstream to XCV50E
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Wed, 4 Jul 2001 19:59:58 +0100
Links: << >>  << T >>  << A >>
You should be able to generate a 'rawbits' file
which will show you the bits which need to be
downloaded, in the correct order.

"Subodh Nijsure" <subodh@best.com> wrote in message
news:9hvnd9$vnb$1@nntp1.ba.best.com...
> [ Not certain if this is the most appropriate group to post this message,
> could only find this fpga related newsgroup ]
>
> I have Xlilinx XCV50E for which I have bitstream file (.XBN), that I want to
> download. I am using a ALTERA CPLD to send this bitstream to the FPGA.
> Platform is running Linux (2.4.2) on Motorola 860  processor. I am writing
> a driver to send this file to the FPGA
>
> The basic quesiton I have is, when I am clocking this bitstream to the
> FPGA, as I read the byte from a file, should I be shifting the bits
> MSB first or LSB first?
>
> Also is there a .h file that describes format of bitstream header?
> i.e. not the entire bitstream just the header of the bitstream.
>
> BTW is there Linux driver already to send bitstream to a Xilinx Virtex FPGA?
>
> /Subodh Nijsure



Article: 32678
Subject: Re: How to estimate the number of CLBs ?
From: Kuan Zhou <zhouk@rpi.edu>
Date: Wed, 4 Jul 2001 15:06:12 -0400
Links: << >>  << T >>  << A >>
Hi,
   Use the floorplanner in Foundation 3.1

sincerely
-------------
Kuan Zhou
ECSE department


On Wed, 4 Jul 2001, vhdl wrote:

> I'm targeting Virtex II, I need to have an estimate for my design.
> I didnot entered in Xilinx tools. But I want to know
> like an adder 12bits, a multiplier 12x12 bits, a flip-flop
> How many CLBs they use ? is there a data book/sheet with
> estimate of chip area used by library element ?
> 
> VhdlUser
> 
> 
> 


Article: 32679
Subject: Re: Problem with resolution functions
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Wed, 4 Jul 2001 20:06:24 +0100
Links: << >>  << T >>  << A >>
As I read your post:
  1. the example in the reference manual does not work.
  2. this recode does work:
          c <='0' when a='0' else 'Z';
          c <='0' when b='0' else 'Z';

Can you post the reference manual example?

"Sven Blankenberg" <s.blankenberg@hs-zigr.de> wrote in message
news:79f58899.0107040647.4a700191@posting.google.com...
> Hi all,
>
> In "VHDL reference manual"/1/ is printed an example to use resolution
> functions for WIRED AND. This example will not work correct .
>
> Simulator print out the follwing warning:
>
> Warning 9242: More then one normal (Totem_Pole) output in the
> following node:
>    NODE: C0.O, C1.O, C2.I, N_Y.
>
> This warning can be eliminated with an flip-flop at signal 'Z'. The
> result of this code is listed in follwing table:
>
>  x y | z
> -----+---
>  0 0 | 0
>  0 1 | 1
>  1 0 | 0
>  1 1 | 1
>
> When the input is also latched, the synthesis will print out the
> following error:
>
> Error: The net '/ver1/c' has more than one driver. (FPGA-CHECK-5)
>
> I coded the same function as follows and it works:
>
> u1: pullup port map(c);
>
> c <='0' when a='0' else 'Z';
> c <='0' when b='0' else 'Z';
>
> Where is the Problem? I think its the same function, only an other
> description.
>
> Sven
>
> I use Xilinx Foundation 3.3i
>
> /1/ FPGA express/FPGA compiler ii VHDL Referenz Manual
>     /express/help/vhdlref.pdf



Article: 32680
Subject: RE: How to estimate the number of CLBs ?
From: vhdl <vhdluser@MailAndNews.com>
Date: Wed, 4 Jul 2001 15:25:44 -0400
Links: << >>  << T >>  << A >>
I didnot entered in the foundation. I want to make estimates 
from drawings on a piece of paper.

VhdlUser
>===== Original Message From Kuan Zhou <zhouk@rpi.edu> =====
>Hi,
>   Use the floorplanner in Foundation 3.1
>
>sincerely
>-------------
>Kuan Zhou
>ECSE department
>
>
>On Wed, 4 Jul 2001, vhdl wrote:
>
>> I'm targeting Virtex II, I need to have an estimate for my design.
>> I didnot entered in Xilinx tools. But I want to know
>> like an adder 12bits, a multiplier 12x12 bits, a flip-flop
>> How many CLBs they use ? is there a data book/sheet with
>> estimate of chip area used by library element ?
>>
>> VhdlUser
>>
>>
>>


Article: 32681
(removed)


Article: 32682
Subject: Re: uart rs232? (for free)
From: vhdlcohen@aol.com (VhdlCohen)
Date: 04 Jul 2001 20:13:58 GMT
Links: << >>  << T >>  << A >>
My book "Component Design by Example ... a Step-by-Step Process Using 
  VHDL with UART as Vehicle" has a complete UART model with error detection and
interrupts, along with the requirements and a transaction based testbench with
textIO and reuse of the parser. 

--------------------------------------------------------------------------
------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Component Design by Example ... a Step-by-Step Process Using 
  VHDL with UART as Vehicle",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
--------------------------------------------------------------------------
------------------------------------------

Article: 32683
(removed)


Article: 32684
(removed)


Article: 32685
Subject: Re: clock frequency synthesizer for FPGA
From: Kolja Sulimma <kolja@sulimma.de>
Date: Thu, 05 Jul 2001 01:07:05 +0200
Links: << >>  << T >>  << A >>
We use a ICS525-01 quite successfully.They are quite easy to get. Even
in germany.
For those chips the frequency of up to 160 MHz is selected by applying
binary values to 17 I/O Pins.
In our prototyping boards we use DIP switches to select the frequency.
For production boards you can connect the pins to VCC/GND.

For production systems PLL chips with in system programmable frequencies
are probably better, because you can change the frequency in the field
with a minimum I/O count.

Kolja


Manfred Kraus wrote:

> Has anybody used a programmable clock frequency synthesizer
> to generate the clock signal for an FPGA ?
> Required range 20 - 100 MHz.
> Any recommendations  or "hands off" ?
>
> Manfred
> --


Article: 32686
Subject: Glitch hunting.
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Wed, 04 Jul 2001 17:15:28 -0600
Links: << >>  << T >>  << A >>
I am using altera's 10k10 FPGA's block ram in asynchronous mode.
Is there any way to cleanly gate write enable with the clock.
Right now I am using WE = ~ CLK & WRITE_ENABLE however my address
for the ram is changed on the rising edge of the same clock.
The software does not report a timing problem. Is there any glitches
or problems that could happen. I would like to gate write enable on
the active high clock segment but I can't think of any glitch
free way to do it that does not mess up the STUPID timing calculations.
Any ideas with out adding another clock cycle for hold times?
Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 32687
Subject: Re: How to estimate the number of CLBs ?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 05 Jul 2001 00:46:37 GMT
Links: << >>  << T >>  << A >>
Look at the structure of the chip.  Each CLB contains 2 slices, each of
which has 2 flip-flops, 2 4 input look-up tables,  and a dedicated carry
chain each running through both LUTs.  Fi you have simple shift
registers, you implement them in the LUT at 16 bits per LUT with the
restriction that the input and output are serial (although you can
dynamically select the output tap).   adders/subtractors/counters and
other carry chain logic gets 2 bits per "slice", and have to be stacked
vertically.  Multipliers consist of a carry chain for each 2xN partial
product and m-1 adders to combine the partial products.  The coregen
data sheets have utilization numbers for some representative
multipliers.  I'm not sure the adder core data sheet has utilization,
but those are easy to figure: just divide the number of bits by two,
rounding up to get the number of slices.

vhdl wrote:

> I'm targeting Virtex II, I need to have an estimate for my design.
> I didnot entered in Xilinx tools. But I want to know
> like an adder 12bits, a multiplier 12x12 bits, a flip-flop
> How many CLBs they use ? is there a data book/sheet with
> estimate of chip area used by library element ?
>
> VhdlUser

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 32688
Subject: Re: 8031 microcontroller on FPGA development board :-(
From: "Tony Burch" <tony@BurchED.com.au>
Date: Thu, 5 Jul 2001 11:16:33 +1000
Links: << >>  << T >>  << A >>
Hi,

"SN" <throne7@my-deja.com> wrote in message
news:c2ec2c5b.0107040649.522dca1e@posting.google.com...
> I notice that some of the development boards e.g. xess and burched
> use the 8031 microcontroller.  I am wondering why the older 8031 is
> used

The BurchED board does not have an 8031, or any CPU, on it.  It just
has the FPGA (plus regulators for IO and core voltages, a 1-100MHz
header programmable PLL oscillator, a single LED, and tactile switch).

However, because the BurchED board has a 200K gate Spartan2
device on it, you have plenty of gates to implement one of the
free CPUs - using only the gates on the FPGA itself, and you
will have plenty of gates left over for other logic, peripherals etc.

Koay Kah Hoe has implemented an 8051 on a BurchED board:
http://www1.mmu1.edu.my/~khkoay/8051core.htm

There are other free CPUs also.
There is a list of free CPU cores at the Free IP Directory:
http://perso.cybercable.fr/alaimo/ipdirectory.html
Opencores:
http://www.opencores.org/cores/minirisc/
http://www.opencores.org/projects.shtml
Free-ip:
http://www.free-ip.com/
http://www.free-ip.com/risc8/index.html

> instead of the 8051??  I personally would like to learn to assembly
> program
> for the 8051 instead so would it be a waste to order one of these
> boards
> and end up knowing code for the inferior 8031?  Maybe its not too bad
> if the 8031 is used widely in industry, how widely used is the 8031?
>
> How good are these boards versus the ones from xilinx?  From an
> education standpoint, i.e. to learn fpga design, are they adequate? or
> should I just pay the extra cash and get the ones from xilinx?  Thanx

My biassed opinion is that you can't go past the value of the
BurchED board for education or prototyping - The B3-SPARTAN2+
board is less than US$120 !  And it has the 200K gate Spartan2 device !

The average cost to users is low, because generally they buy
the B3-SPARTAN2+ core board, and then any plug-on modules
(such as SRAM, DIP switches, 7-segments, PC periperal connectors etc.)
that they wish.  The idea being that you only buy what you
want - "mix and match" the components you want, or just
use the core board in your own proto system.

Hope my biassed opinion is of some help:)

Best regards
Tony Burch
http://www.BurchED.com.au
Lowest cost, easy-to-use
FPGA prototyping kits!




Article: 32689
Subject: Xilinx J Drive
From: cameron@semiconductor-technologies.com.au (Cameron Watt)
Date: Thu, 05 Jul 2001 03:47:39 GMT
Links: << >>  << T >>  << A >>
Hi all,

I would like to know if anyone has tried Xilinx's JDrive tool with
Spartan 2.

I note that 1532 BDSL files are available for Virtex, VirtexE and 18
series config mem. As the Spartan 2 is a Virtex derivative, can the
Virtex BDSL be used with the Spartan 2 (in particular XC2S200-PQ208).

Thanks for any help that you can offer,

Cameron Watt

Article: 32690
Subject: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
From: bhicks02@tampabay.rr.com (Mike Hicks)
Date: Thu, 05 Jul 2001 04:02:09 GMT
Links: << >>  << T >>  << A >>
This Tcl/Tk based VHDL testbench generator, like everything else,
could probably use some improvement, but it works well enough to keep
you from retyping all those port entity names everytime you create a
new testbench. It's been tested on Windoz and SuSE Linux so far. If
you improve it, please post your improvement for the rest of us.
	Mike Hicks
	Computer Design Matrix
	mrmikehicks[at]yahoo.com

Article: 32691
Subject: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
From: bhicks02@tampabay.rr.com (Mike Hicks)
Date: Thu, 05 Jul 2001 04:02:10 GMT
Links: << >>  << T >>  << A >>
begin 644 tb_gen.tcl
M.R,M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+3L-"CLC('1B7V=E
M;BYT8VP@8GD@36EK92!(:6-K<R`@("`@("`@("`@("`@("`@("`@("`@("`@
M("`@("`@("`@("`@("`@("`@("`@("`@("`[#0H[(R`@("`@("`@("`@("`@
M("`@("`@("`@("`@("`@("`@("`@("`@("`@("`@("`@("`@("`@("`@("`@
M("`@("`@("`@("`@("`@("`@.PT*.R,@5&AI<R!T8VP@<V-R:7!T(&=E;F5R
M871E<R!A(%9(1$P@=&5S=&)E;F-H(&9I;&4@)V9N86UE7W1B+G9H9"<@=&%R
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M+B`[#0H[(R!!;B!A9&1I=&EO;F%L(&-O;6UA;F0@9FEL92`G9FYA;65?=&(N
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M<G1S('5S:6YG('=I<V@@7`T*97AE8R!W:7-H("(D,"(@(B1`(B`M+0T*.R,M
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM.PT*.R,@4V5T('1H92!7
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/97)?:61]#0I]#0H-"@T*
`
end

Article: 32692
Subject: Altera ACEX
From: "Marco" <curgan@t-online.de>
Date: Thu, 5 Jul 2001 08:01:20 +0200
Links: << >>  << T >>  << A >>
Hello everybody,

i am developing with an ACEX EP1K30.
My question:  Do anybody know the best configuration device for that device?
i only know the EPC1 and EPC2. Are there some form other manufacturers ?

Have anyone some schematics with the ACEX ????

Thank you very much.

Best regards

Marco




Article: 32693
Subject: Re: Downloading FPGA (XBN) bitstream to XCV50E
From: "Felix Bertram" <fbertram@gmx.net>
Date: Thu, 5 Jul 2001 08:23:10 +0200
Links: << >>  << T >>  << A >>
> The basic quesiton I have is, when I am clocking this bitstream to the
> FPGA, as I read the byte from a file, should I be shifting the bits
> MSB first or LSB first?

MSB first.

> Also is there a .h file that describes format of bitstream header?
> i.e. not the entire bitstream just the header of the bitstream.

See the code snippet below for further details. I am using this code to
program AT17LV512 devices from the Xilinx .bit files.

Hope this helps,
best regards

Felix Bertram
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 49 39 755
Fax.: +49 (0) 5223 48 945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de

//--------------------------------------------------------------------------
----
static long unsigned int GetInteger(istream& is, int len)
{ ASSERT(len<=4); // can't handle lengths greater than 32 bits

 long unsigned int lui = 0;
 for(int i=0; i<len; i++)
 { // process hex digits starting from MSDigit
  unsigned char digit;
  is.read(&digit,1);
  ASSERT(is.eof()==0);
  lui = lui*256 + (long unsigned int)digit;
 }
 return lui;
}

//--------------------------------------------------------------------------
----
static int GetType(istream& is)
{ unsigned char type;
 is.read(&type,1);
 ASSERT(is.eof()==0);
 return type;
}

//--------------------------------------------------------------------------
----
static unsigned int ParseHeader(istream& is)
{ // jump over the first field of the BIT file
 unsigned int l1= GetInteger(is, 2);
 ASSERT(l1!=0);
 is.ignore(l1);

 unsigned int l2= GetInteger(is, 2);
 ASSERT(l2== 1);

 while(1)
 { unsigned char id= GetType(is);

  if (id== Bitstream) break;

  switch(id)
  { case DesignName:  cerr << "Design: "; break;
   case TargetDevice: cerr << "Target: "; break;
   case CreationDate: cerr << "Date:   "; break;
   case CreationTime: cerr << "Time:   "; break;
  }

  unsigned int len= GetInteger(is, 2);

  char buf[256];
  if (len< sizeof(buf))
  { is.read(buf, len);
   cerr << buf;
   cerr << endl;
  }
 }

 // now we are at the start of the configuration bits
 unsigned int BitstreamLength= GetInteger(is,4);
 return BitstreamLength;
}
//--------------------------------------------------------------------------
----




Article: 32694
Subject: Driven clocks balancing
From: rotemg@mysticom.com (Rotem Gazit)
Date: 5 Jul 2001 00:09:41 -0700
Links: << >>  << T >>  << A >>
Hi,

I need to drive 4 identical clocks out of my Virtex-E FPGA.
I have to align the 4 pins on the same side of the chip, where 2 of
those pins are at the corners and 2 of those pins are in the middle.
Because of other logic on the FPGA I can spare only one or two DLLs
for driving the 4 clocks .
The clocks are related to data , also driven from the FPGA,  so I
cannot use tricks like dividing clkx2 near the output pines.
Is there any way to balance the routing delay inside the FPGA ,from
the DLL to the 4 output pins ?
After the routing has been balanced can it be fixed , so it will not
change when the design will be re-implemented ?

Thanks,

Rotem Gazit
MystiCom LTD

mailto:rotemg@mysticom.com
http://www.mysticom.com/

Article: 32695
Subject: Re: Altera ACEX
From: martin.j.thompson@trw.com
Date: 05 Jul 2001 08:51:19 +0100
Links: << >>  << T >>  << A >>
"Marco" <curgan@t-online.de> writes:

> Hello everybody,
> 
> i am developing with an ACEX EP1K30.
> My question:  Do anybody know the best configuration device for that device?
> i only know the EPC1 and EPC2. Are there some form other manufacturers ?
> 

As far as I know, they are the only easy ones to use.  IIRC Atmel may
make some semi-compatible devices - I admit I didn;t look far, we just
used the EPC2.  I would recommend the EPC2 over the EPC1 unless you
don't mind the EPC1 beign OTP of course.

> Have anyone some schematics with the ACEX ????
> 

Altera have an appnote number 116 which talks about configuring 10,
6000 and 20K devices.  The ACEK 1K family are almost (but not quite)
idenitical to the 10Ks.  AFAIK from a configuration POV they are the same.

> Thank you very much.
> 

Hope it helps!

Cheers,
Martin

-- 
Martin Thompson MIEE C.Eng.
martin.j.thompson@trw.com


Article: 32696
Subject: Re: How to estimate the number of CLBs ?
From: Alan Fitch <alan.fitch@doulos.com>
Date: Thu, 5 Jul 2001 09:10:43 +0100
Links: << >>  << T >>  << A >>
In article <3B43B901.B4BA324@andraka.com>, Ray Andraka <ray@andraka.com>
writes
>Look at the structure of the chip.  Each CLB contains 2 slices, each of
>which has 2 flip-flops, 2 4 input look-up tables,  and a dedicated carry
>chain each running through both LUTs.  Fi you have simple shift
>registers, you implement them in the LUT at 16 bits per LUT with the
>restriction that the input and output are serial (although you can
>dynamically select the output tap).   adders/subtractors/counters and
>other carry chain logic gets 2 bits per "slice", and have to be stacked
>vertically.  Multipliers consist of a carry chain for each 2xN partial
>product and m-1 adders to combine the partial products.  The coregen
>data sheets have utilization numbers for some representative
>multipliers.  I'm not sure the adder core data sheet has utilization,
>but those are easy to figure: just divide the number of bits by two,
>rounding up to get the number of slices.
>
>vhdl wrote:
>
>> I'm targeting Virtex II, I need to have an estimate for my design.
>> I didnot entered in Xilinx tools. But I want to know
>> like an adder 12bits, a multiplier 12x12 bits, a flip-flop
>> How many CLBs they use ? is there a data book/sheet with
>> estimate of chip area used by library element ?
>>
>> VhdlUser
>

Also there's information in each of the coregen blocks - sometimes in
the data sheet, otherwise you have to run coregen itself. So you could
find a coregen block that's equivalent to what you're doing and use its
size as an estimate.

Of course this won't help if you can't run the Xilinx tools at all. 

kind regards
Alan
-- 
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                           Email: alan.fitch@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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Article: 32697
Subject: Re: Problem with resolution functions
From: s.blankenberg@hs-zigr.de (Sven Blankenberg)
Date: 5 Jul 2001 01:47:20 -0700
Links: << >>  << T >>  << A >>
"Tim" <tim@rockylogic.com.nospam.com> wrote in message > As I read your post:
>   1. the example in the reference manual does not work.
>   2. this recode does work:
>           c <='0' when a='0' else 'Z';
>           c <='0' when b='0' else 'Z';
> 
> Can you post the reference manual example?

of course, i' can.

-- copy from Manual
package RES_PACK is
 function RES_FUNC(DATA: in BIT_VECTOR) return BIT;
 subtype RESOLVED_BIT is RES_FUNC BIT;
end;

package body RES_PACK is
  function RES_FUNC(DATA: in BIT_VECTOR) return BIT is
  -- synopsys resolution_method wired_and
  begin
    -- The code in this function is ignored by the program
    -- but parsed for correct VHDL syntax
   for I in DATA'range loop
     if DATA(I) = '0' then
       return '0';
     end if;
   end loop;
   return '1';
  end;

end;

use work.RES_PACK.all;

entity WAND_VHDL is
  port(X, Y: in BIT; Z: out RESOLVED_BIT);
end WAND_VHDL;

architecture WAND_VHDL of WAND_VHDL is

begin

Z <= X;
Z <= Y;

end WAND_VHDL;

-- and my changes for use internal signals

use work.RES_PACK.all;

entity WAND_VHDL2 is
  port(clk, X, Y: in BIT; Z: out BIT);
end WAND_VHDL2;

architecture WAND_VHDL of WAND_VHDL2 is

signal a,b : BIT;
signal c   : RESOLVED_BIT;

begin

process(clk)
begin
  if clk'event and clk='1' then
    a <= X;
    b <= Y;
  end if;
end process;

c <= a;
c <= b;

process(clk)
begin
  if clk'event and clk='1' then
    Z <= c;
  end if;
end process;

end WAND_VHDL2;

Sven

Article: 32698
Subject: Re: 8031 microcontroller on FPGA development board :-(
From: Niki Steenkamp <steenkmp@ing.sun.ac.za>
Date: Thu, 05 Jul 2001 11:05:14 +0200
Links: << >>  << T >>  << A >>


"Keith R. Williams" wrote:
> 
> In article <c2ec2c5b.0107040649.522dca1e@posting.google.com>, throne7
> @my-deja.com says...
> > I notice that some of the development boards e.g. xess and burched
> > use the 8031 microcontroller.  I am wondering why the older 8031 is
> > used
> > instead of the 8051??  I personally would like to learn to assembly
> > program
> > for the 8051 instead so would it be a waste to order one of these
> > boards
> > and end up knowing code for the inferior 8031?  Maybe its not too bad
> > if the 8031 is used widely in industry, how widely used is the 8031?
> 
> The 8031 is an 8051 with no (or disabled) on board code memory. They're
> the same processor, same instruction set.
The only significant difference, besides the on board code memory, is
that the 8031 has 128 bytes of RAM while the 8051 has 256.  Also, AFAIK,
the 8051 also has one additional timer (timer 2).

Niki

-- 
.........-----====**====-----.........
Niki Steenkamp
Electronic Systems Laboratory (ESL)
University of Stellenbosch
South Africa
Tel. +27 21 8084934
http://sunsat.ee.sun.ac.za
--------------------------------------

Article: 32699
Subject: Re: Problem with resolution functions
From: s.blankenberg@hs-zigr.de (Sven Blankenberg)
Date: 5 Jul 2001 02:33:17 -0700
Links: << >>  << T >>  << A >>
Kuan Zhou <zhouk@rpi.edu> wrote in message news:<Pine.SOL.3.96.1010704123305.13606B-100000@rcs-sun1.rcs.rpi.edu>...
> Hi,
>    if a='0' and b='0',C will be written twice at the same time,which is
> not allowable.C is like the bus signal,each time only one driver can 
> talk to the bus.Otherwise it will result in chaosity.
>    Use if else can avoid such problems.
>    

Hi,

thanks for your answer. 

In this case is the usage of simple combinatory equals not reasonable.
I have more than 15 inputs for my AND function. That means 3 or more
CLB's. When i can use the three state buffers at an output of CLB,
save this for later use.

But the primary problem is, the possibility to use the resolution
function.

best regards

sven



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