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Messages from 32900

Article: 32900
Subject: Re: Virtex2: Is it possible to place distributed DPRAM
From: Goran Bilski <goran@xilinx.com>
Date: Wed, 11 Jul 2001 07:59:30 -0700
Links: << >>  << T >>  << A >>
Hi all,

For VII, the coordinate system has changed.
In Virtex, the origin was at the upper left corner.
In VirtexII, the origin is at the lower left corner.
In Virtex, you address using RxCy.S(0/1) where the x,y is the coordinate for the CLB
and S is which slice within that CLB
In VirtexII, you address using XxYy, which the x,y is the coordinate for a slice.
So the RLOCing scheme has changed for VirtexII.

What I have done with my designs is to using the new VII scheme and have a function
which translate
that into Virtex scheme. That function is stored in a package which every module
that need RLOCing is calling.
The function is:  (TARGET_FAMILY_TYPE is just an enumurate type which has VIRTEX and
VIRTEXII as members)

  function Get_RLOC_Name (Target : TARGET_FAMILY_TYPE;
                                              Y        : integer;
                                              X        : integer) return string is
    variable Col   : integer;
    variable Row : integer;
    variable S      : integer;
  begin
    if Target = VIRTEX then
      Row := -Y;
      Col := X/2;
      S   := 1 - (X mod 2);
      return 'R' & itoa(Row) &
             'C' & itoa(Col) &
             ".S" & itoa(S);
    elsif Target = VIRTEX2 then
      return 'X' & itoa(X) & 'Y' & itoa(Y);
    end if;
  end function Get_RLOC_Name;


and a calling is looking like this:

  constant RLOC_PLACE : string := Get_RLOC_Name(Target => C_TARGET,

Y         => C_Y,

X         => C_X);

  attribute RLOC of I_ALU_LUT  : label is RLOC_Place;


By using this approach I have a RLOCing schem which works with both VirtexII and
Virtex.

For the distributed RAM, the placement within a CLB is totally changed in VII, this
has to be done in order
to get upto 128x1S and 64x1D primitives.
I will come back with more information. I have only placed 32x1D primitives using
the new approach.

Göran Bilski


Ray Andraka wrote:

> I didn't realize this was a VirtexII.  I have had near zero luck with RLOCs in
> virtexII so far.  I'm glad someone like you is debugging it before it becomes my
> critical path ;->
>
> Philip Freidin wrote:
>
> > Warning. I have found that RLOCs dont work for Virtex-II . While there are
> > some trivial test cases which do work, really complex stuff like putting
> > two flip-flops in the same slice dont work, and are ignored, with no error
> > message. (I.e. silently ignored)
> > Since flip flops are too hard, I wouldn't expect anything else to work either.
> >
> > I am using 3.3.8i
> >
> > I have filed a case. No result yet.
> >
> > Philip Freidin
> >
> > (I can't tell you how much I enjoy creating test cases and documenting
> >  failure modes for stuff that it is hard to believe was ever tested :-(   )
> >
> > On Wed, 11 Jul 2001 01:10:28 GMT, Ray Andraka <ray@andraka.com> wrote:
> > >The floorplanner essentially puts LOCs on it (it treats the design as
> > >flat).  Have you tried putting RLOCs on by embedding the RLOCs in your
> > >source using user attributes rather than the mapping directives (you
> > >need to instantiate the RAM16x1D primitive to do that)?  I have had no
> > >problem using embedded RLOCs with the floorplanner.  I had had numerous
> > >problems with the synthesis vendor's RLOC directives...enough so that I
> > >stopped trying to use them some time ago.
> > >
> > >If the RLOC is being ignored, it is generally because it is being
> > >applied to a macro which does not have RLOCs on the primitives.  It
> > >sounds like perhaps your synthesis tool is constructing the RAM16x1D out
> > >of other primitives rather than instantiating the RAM16x1D primitive.
> > >Try instantiating it as a black box and putting and RLOC attribute on
> > >it.  Make sure the generics are not visible to the synthesis or it will
> > >screw it up.
> > >
> > >Don Husby wrote:
> > >
> > >> I've been beating my head against this for several hours.
> > >> I've tried LOC, RLOC, and floorplanning.  It doesn't seem
> > >> to be possible to place distributed dual-port RAMs.
> > >>
> > >> Placing a LOC on a RAM16X1D results in an error message that says
> > >> you can't place the SP and DP part of a RAM in the same block.
> > >>
> > >> An RLOC is silently ignored.
> > >>
> > >> The floorplanner lets you place things wherever you want, but
> > >> the mapper complains about various things.  Also, mapping
> > >> directives in the HDL files are incompatible with using the
> > >> floorplanner: You can use one or the other, but not both.
> > >>
> > >> Anyone?
> >
> > Philip Freidin
> > Fliptronics
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com


Article: 32901
Subject: Re: Need to speed up VHDL accumulator on Xilinx
From: Goran Bilski <goran@xilinx.com>
Date: Wed, 11 Jul 2001 08:11:52 -0700
Links: << >>  << T >>  << A >>
Hi,

If you would to use the clear signal to the flipflops as Ray mentioned and also
consider
using the MULT_AND component you would be able to get the reqested speed.
The MULT_AND would remove the need of the extra multiplexor.

The problem is that you would have to instanciated
LUT4
MULT_AND
MUXCY
XORCY
FDRE
components.
It would reach you goals but the code would be specific for the FPGA
implementation.
If you want maximum speed out of a FPGA, you need to write specific code for it.

/Göran


fred wrote:

> All Ray said plus:
>
> If you want to work out if you stand any chance at all of getting this sort
> of speed, write the accumulator without the muxes (load and clear) - the
> fastest inferrable structure:
>
> process(clk)
> begin
> if clk'event and clk='1' then
> theta <= freq_word+theta;
> end if;
> end process;
>
> If this wont go at the speed you want then you'll need to find another way.
>
> Whatever you do I think you'll need to get rid of those muxes get clear from
> the register's direct synchronous clear and the load from 'clear' followed
> by first accumulate.
>
> BTW: for vtx1000e-6 (I don't have Virtex parts loaded) I got 128M for your
> code, 158M for the bare bones - 2speed grades up & still not quite there.
>
> Fred


Article: 32902
Subject: emergency consumption reduction for Spartan II
From: catherine_gyselinck@srtelecom.com (C. Gyselinck)
Date: 11 Jul 2001 08:13:50 -0700
Links: << >>  << T >>  << A >>
In a thermal emergency, I need to trim card power consumption.  I can
afford to loose my Spartan II FPGA. Can anyone tell me approximately
what the power consumption of the chip would be if I pull /PROGRAM low
and hold it low?

Is there a better way to bring the chip consumption down? (The chip
contains lots of odds and ends: I cannot simply turn off a clock.)

Thank you

Article: 32903
Subject: Re: Virtex2: Is it possible to place distributed DPRAM
From: husby_d@yahoo.com (Don Husby)
Date: 11 Jul 2001 08:50:17 -0700
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> :
>...
>  Have you tried putting RLOCs on by embedding the RLOCs in your
> source using user attributes rather than the mapping directives (you
> need to instantiate the RAM16x1D primitive to do that)?

Yes.  I attached them directly to the RAM primitives. No effect.

The problem seems to be related to way DP RAM is implemented
in virtex2 vs. virtex.  In Virtex, the two LUTs of a DPRAM 
share the same slice.  In Virtex2, it appears that the two
LUTs must be in two different slices side by side.  Some of
the tools (e.g. floorplanner) want to map it the old way,
some want to map it the new way.

Article: 32904
Subject: Re: Need to speed up VHDL accumulator on Xilinx
From: John_H <johnhandwork@mail.com>
Date: Wed, 11 Jul 2001 16:06:54 GMT
Links: << >>  << T >>  << A >>
I don't see Ray's message yet so you may have all your answers.
I'm Verilog instead of VHDL but I know the virtex architecture wrt accumulators.

If your synthesizer can do a good job, you can get your load, clear, and accumulate
into one stage without sacrificing the ability to map nicely into an ASIC.

Since you want at most 4 elements going into each LUT in your accumulator chain,
arrange the logic in the following form (I'll let you figure out the translation to
VHDL):

   reg_theta <= ( !clearn | load ? 0 : theta )
              + ( !clearn ? 0 : freq_word );

Here the tricks are to use the inverted "clearn" signal instead of clear so the
MULT_AND xilinx primitive can feed the direct input to the carry chain MUXCY inputs.
The uninverted signal adds another level of logic.

The synthesis tool should be able to merge the signals nicely together so the 3 inputs
on the one side of the "+" and the two inputs on the other can come together in one LUT
thanks to the MULT_AND's ability to apply the two-term element directly to the carry
chain.

One level of logic in one chain.  Damn fast.

Happy accumulating!
- John


Article: 32905
Subject: Re: Online threshold limit counter
From: John_H <johnhandwork@mail.com>
Date: Wed, 11 Jul 2001 16:15:00 GMT
Links: << >>  << T >>  << A >>
AND
  If you need your divider to be "exact" such that a divide by 79 will sometimes divide
by 78 in a DDS with a ratio of 13/1024, you can use an adjustment every time the
accumulator rolls over to add 10 instead of 13 to "effectively" get a ratio of 13/1027
(the one-time adjustment shows up in the denominator) which is exactly a divide-by 79.

You'd get your instant rate change without a phase slip.

Ain't these techniques grand?
- John

Ray Andraka wrote:

> Another thought.  If you do need to change the count modulus on the fly and have it
> take effect immediately, you could use a DDS (aka phase accumulator).  In this case,
> you change the increment value in a fixed count field.  The msb out is at a
> frequency determined by the increment value.  If you need a count then, you could
> detect the rising edge of the msb and use that to reset a counter.
>
> SO many ways to skin a cat!


Article: 32906
Subject: Re: 8031 microcontroller on FPGA development board :-)
From: "Steven J. Ackerman" <sja@gte.net>
Date: Wed, 11 Jul 2001 16:24:29 GMT
Links: << >>  << T >>  << A >>
> However, ROMless 8031/32 are still very cheap, well under $1, so soft
> cores have a way to go yet :-)

Here's some ballpark pricing, 1K to 5K quantities:

>
> o Dallas DS89C420 = 50 MIPS, 8052 core, 16K FLASH, 1K XRAM, 2 UART 5V ~
$$$
> o Winbond W77LE58 = 6-10 MIPS, 8052 core, 32K FLASH, 1K XRAM, 3-5V ~ $
> o Temic T89C51RD2 = 5 MIPS, 8052 Core, 64K Flash, 2KEE, 1K RAM, 3-5V ~ $
>
> Not a 'std' 40/44 package, but interesting is
> o Dallas 80C400 = 10 Mips, Ethernet, CAN, TCP/IP in ROM, QFP100 ~ $$$$
>

Anything 'Dallas/Maxim' is major bucks.

Philips 89C51RD2 - 5 MIPS, 8052 Core, 64K Flash, 1K RAM, 3-5V ~ $3.50

> Also not a standard 40- or 44-pin package but also potentially
> interesting are the Triscend E5 Configurable System-on-Chip (CSoC)
> devices.  All four family members contain the following.
>
> TE502:  8Kx8 XRAM,  256 CSL cells = ~3,200 gates, 52 to 76 user-I/O = ?
> TE505: 16Kx8 XRAM,  512 CSL cells = ~6,400 gates, 60 to 124 user-I/O ~
$9.50
> TE512: 32Kx8 XRAM, 1152 CSL cells = ~14,400 gates, 60 to 150 user-I/O ~
$17.50
> TE520: 40Kx8 XRAM, 2048 CSL cells = ~25,600 gates, 126 to 252 user-I/O ~
$30.00

--
Steven J. Ackerman, Consultant
ACS, Sarasota, FL
http://www.acscontrol.com
steve@acscontrol.com
sja@gte.net





Article: 32907
Subject: Re: Handel-C
From: anamax@earthlink.net (Andy Freeman)
Date: 11 Jul 2001 09:25:18 -0700
Links: << >>  << T >>  << A >>
Magnus Homann <d0asta@licia.dtek.chalmers.se> wrote in message 
> Your posts about using a C as a hardware language are interesting. Do
> you have any example with using C-code and storage elements?

Those of you who have written cycle-accurate simulators may have
seen something like this before.  (The first design in C that I saw/
worked on started out as a cycle-accurate simulator.)

Suppose that you want to build a system consisting of two modules.
To keep things well behaved, I'm going to use flip-flops and
a single clock, and ignore all other connections to the outside
world.  (Adding those connections should be obvious; latches
and tri-states are merely tedious.)  Of course, each module does
produce inputs needed by the other.

One can design with registered inputs, registered outputs, or
both, or neither (with combinatorial logic on both sides of
storage elements in a module).  I'm going to go with registered
inputs but it should be obvious how to do any of the others.

Unless one goes with "neither", each module can be expressed with
two procedures, so let's call the procedures for the first module
output_A and input_A and the procedures for the second module
output_B and input_B.

The names are intended to be a big give-away; the output_* procedures
read their module's storage elements, do any combinatorial operations,
and "return" the results.  The input_* procedures take inputs and a
clock, and, if the clock has the correct value, store those inputs
in their module's storage elements.  The input_* procedure's body can
look like:
    if( posedge(clock) ) {
        ff_1 = inp_1;
        ff_2 = inp_2;
    }

There are lots of ways to transfer values between these procedures.
Once you decide how you want to do it, you can build a system by
connecting them together appropriately.  For simulation, you call
the output_* procedures then the input_* procedures; output_A feeds
input_B and output_B feeds input_A.

You'll also need a mechanism for associating a module's procedures
and storage elements with each other.  If you also want to instantiate
a given module multiple times in a single design, you'll probably
decide to use C++ classes to express that association.  (Since you'll
probably want to use C++ classes for other things, you'll also need a
mechanism for distinguishing module classes from other classes.)

Of course, you'll want to use subroutines to keep things manageable
and to allow code reuse.  You'll also want some library support for
bit operations and arithmetic.  (I've mentioned that Frontier Design
did something interesting in this area.)

Module hierarchies are fairly straightforward.

-andy

Article: 32908
Subject: Re: 8031 microcontroller on FPGA development board :-)
From: emanuel stiebler <emu@ecubics.com>
Date: Wed, 11 Jul 2001 11:15:18 -0600
Links: << >>  << T >>  << A >>
"Steven J. Ackerman" wrote:
> 
> Philips 89C51RD2 - 5 MIPS, 8052 Core, 64K Flash, 1K RAM, 3-5V ~ $3.50

Looks like a nice replacement for the Xilinx PROMs. And even some spare
i/o.

cheers

Article: 32909
Subject: Re: emergency consumption reduction for Spartan II
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 11 Jul 2001 11:25:34 -0700
Links: << >>  << T >>  << A >>
Without too much research,

The current drops to a very low value (less than 10 mA typically).  There
are a few oscillators still running, and the bias generators (analog op
amps and band gap references).

For a real number, I would need to know the device (ie 2S100) so that I
could get the actual number for you.

In a thermal emergency, the number will be even lower, as hotter will mean
lower currents.

As long as the junction temperature stays below ~125 C, there will be no
damage to the device (not an operational condition for months or years
mind you! but perfectly acceptable for a day or a week).

The plastic packages start having problems above 135 C.

What is a thermal emergency?  It may be that you can afford to allow
continued operation as long as you do not exceed the absolute maximum
specifications in the data sheet (+125 C junction)?  The device will not
meet timing, yet you can predict its speed by using the simple rule that
you will lose (no more than) 15% speed from commercial to industrial (85C
to 100 C) and another (no more than) 15% from industrial to military (100
to 125 C).

By proper design, testing, and qualification, occasional thermal overloads
may be dealt with.  I had to do this for a road-side telecoms
applications, where in the worst case the case temperature was +85C for 72
hours, once a year (based on data from the phone company).  The junction
was going to be ~ 110 C for that time.  It was not allowed that the unit
stopped operating, but it was understood that this would shorten the
product life by a small amount.  Commercial parts were qualified to
operate at this temperature by the operating company testing laboratory
(sufficient timing margin on the Xilinx FPGA's, and error free operation),
and accepted into service.  Over thirty thousand units were shipped (large
order for this particular product).

Of course, we do not sell a military Spartan II (I find that a bit strange
-- the mascot is "Sparty" a warrior....).

Austin

"C. Gyselinck" wrote:

> In a thermal emergency, I need to trim card power consumption.  I can
> afford to loose my Spartan II FPGA. Can anyone tell me approximately
> what the power consumption of the chip would be if I pull /PROGRAM low
> and hold it low?
>
> Is there a better way to bring the chip consumption down? (The chip
> contains lots of odds and ends: I cannot simply turn off a clock.)
>
> Thank you


Article: 32910
Subject: Re: Need to speed up VHDL accumulator on Xilinx
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Wed, 11 Jul 2001 19:23:44 GMT
Links: << >>  << T >>  << A >>
Antonio,
I had to speed up an NCO once and I pipelined it by splitting it into
smaller adders.  A 32-bit adder can be split into 2 16-bit adders or even 32
2-bit adders for maximum speed.  The carries from each adder flow into the
next.

If "theta" changes then you also have to pipeline pieces of theta so that
they flow into the small adders at the right time, but you don't have to
worry about this if theta is set once and remains static.

If you are using this as an NCO, then you are probably just using the MSB of
the result.  If, however, you need to use all bits of the result, you will
have to pipeline delay the outputs of the lesser significant adders so they
match up with the more significant adders.

-Kevin

"Antonio" <dottavio@ised.it> wrote in message
news:fb35ea96.0107102335.24957728@posting.google.com...
> Good Morning,
> I've this accumulator that I would want to implement on a Xilinx
> XCV1000BG560-4 , the problem is that I need 165MHz and instead this
> may work only at 105MHz , have you in mind any modify that I could do
> to speed it up ??
>
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_signed.all;
>
>
> entity accumulatore is
> port ( freq_word : in std_logic_vector(31 downto 0);
> clk, load, clear : in std_logic;
> theta     : inout std_logic_vector(31 downto 0)
> );
> end accumulatore;
>
> architecture acc_arch of accumulatore is
> signal reg_theta : std_logic_vector(31 downto 0);
> begin
> process(load, clear, freq_word, theta)
> begin
> if load='1' then
> reg_theta <= freq_word;
> else if clear='1' then
> reg_theta <= "00000000000000000000000000000000";
> else
> reg_theta <= freq_word+theta;
> end if;
> end if;
> end process;
>
> process(clk)
> begin
> if clk'event and clk='1' then
> theta <= reg_theta;
> end if;
> end process;
> end acc_arch;
>
> The Accumulator is inside a Cordic NCO and I can't utilize Core
> Generator 'cause then the project will be mapped on ASIC, that I know
> is more speed but I want to implement the working project also on FPGA
> to simulate it accurately before of fitting on ASIC.
>
> thank you for your help ...
>
>     Antonio D'Ottavio
>



Article: 32911
Subject: Re: Simulation problems with BlockRAM's INIT values !
From: scote@hyperchip.com (s cote)
Date: 11 Jul 2001 13:12:24 -0700
Links: << >>  << T >>  << A >>
Instanciation also makes the synthesis runtime will drop considerably!

Article: 32912
Subject: Re: FPGA-based board vs bigger FPGA
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Wed, 11 Jul 2001 14:17:31 -0600
Links: << >>  << T >>  << A >>
jdiaz_pr wrote:
> 
> One friend of mine says that deal with FPGA-based boards is a waste of
> time. Suggesting that the millions-ever-increasing size FPGA will
> handle every possible design without any hassle.
> 
> What do you think?
I think you just have to shop carefully. Like buying a motor vehicle
you buying that fits the application. Just be careful with the salesman
sell as you may not need all the features needed like A/C,power windows
and 300 HP, if all you wanted was reliable operation.
I say get the software tools first and try them out and buy the FPGA later.
Only once you have completed the first revision of your design in hardware
will you have a good idea the size of the FPGA needed if you have time to
do this. A ballpark figure may be 1 logic cell for each gate,flip
flop,adder/counter cell & multiplexer input if you have your logic already.
Allow 25% more logic cells
for I/O and routing resources.
Ben. 
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 32913
Subject: Re: Altera synthesis tools WAS: What chip!?
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Wed, 11 Jul 2001 21:26:11 +0100
Links: << >>  << T >>  << A >>
Sorry was not clear enougth - I was talking about the Synthesis part - as the
rest of the tool(s) work fine, I known I use them every day.

Cyber_Spook_Man

Peter Ormsby wrote:

>
> > Good point - don't use MaxPlusII for this as thay never seamed to get it
> to work
> > right.
>
> MAX+PLUS II works well for a great majority of the designs out there.  Let's
> not confuse the synthesis part with the rest of the tool.  Altera's native
> VHDL
> synthesis has never been much more than OK (although its better than the
> native verilog synthesis).  The rest of the tool has always been fast,
> relatively
> easy to learn, and generally quite capable.  As for the synthesis, not only
> does
> Altera bundle Altera-specific versions of Synopsys' FPGA Express and
> Exemplar's
> Leonardo Spectrum with their tools subscription (as mentioned below), you
> can
> actually get these tools free from the Altera web site (along with the free
> version
> of MAX+PLUS II for the MAX and ACEX devices).
>
> -Pete-
>


Article: 32914
Subject: Re: Problems with JTAG on XC95144 was:Best JTAG H/W,...
From: arast@inficom.com (Alex Rast)
Date: Wed, 11 Jul 2001 20:43:56 GMT
Links: << >>  << T >>  << A >>
In article <1jlmkt0o5dqh8e4dpedhinb5ni4taug4dl@4ax.com>, philip@fliptronics.com wrote:
>Well ... Since you bypassed the Pericom part, and it works, and with
>the Pericom part in circuit it fails, it is modt likely that the Pericom part
>is doing something to your signal that is causing a problem .

Agreed. That's why I'm pretty puzzled, when, looking at the signals on the 
lines themselves, they *appear* OK. Maybe it requires sharper eyes...

>Except, are the signal lines that go between the CPLD and the Pericom
>part long, and your direct conection short? If so it might be the long traces.

Not especially long. I'd estimate that the difference in trace lengths is less 
than a factor of 2, and the total trace length is probably about 3 or 4 
inches.

>
>Otherwise, look at the rising AND falling edges of the signals at the CPLD.
..

I wonder about edge rates, which I admit I haven't looked at too hard, after 
noting that the edge transition times I was seeing were much, much less than 
the level hold time. But I'll take another look. The scope I was using was a 
TDS 684C - plenty of bandwidth.


>Another thing would be to check the timing of the clock and data signals.
>Xilinx may have made a mistake in the way it bit-bangs the JTAG lines...

Hmm. I'll look at that. Thanks for the thought.

>
>I guess you could short out the Pericom switches one at a time and see if
>that localizes the problem .
>

That sounds like a creative debugging idea. Since I've got the bypass roach 
wires soldered on anyway, I can just opt to connect the JTAG cables to the 
roach wire or switch input.

>Philip

Article: 32915
Subject: Re: need help implementing state diagram of a 2input mealy machine!
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 11 Jul 2001 13:48:21 -0700
Links: << >>  << T >>  << A >>
This homework assignment sounds much moore like a more state machine.

On Wed, 11 Jul 2001 15:31:33 -0700, "Chez" <yuugy09@bellsouth.net> wrote:
>  I'm trying to implement a 2-input Mealy machine that produces a 1 as its
>single output when the values of the 2 inputs differ at the time of the
>previous clock pulse.  Any help would be much appreciated!
>
>

Philip Freidin
Fliptronics

Article: 32916
Subject: WebPACK problem
From: Gonzalo Arana <gonzaloa@sinectis.com.ar>
Date: Wed, 11 Jul 2001 17:51:41 -0300
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Transfer-Encoding: 7bit

Hi,

I am writing a RS-232 UART, since I couln't find any sinthesizable one
with the ability to receive 7/8 data bits and check parity (even or
odd).  The transmitter works great, but the receiver has a problem: when
I try to translate it (with WebPACK) I get

Annotating constraints to design from file "uartrx.ucf" ...
ERROR:NgdBuild:397 - Could not find NET 'data_out' in design 'uartrx'. 
NET
   entry is 'NET "data_out" LOC = "p11";
   '
ERROR:NgdBuild:397 - Could not find NET 'estado' in design 'uartrx'. 
NET entry
   is 'NET "estado" LOC = "p17";

So, it seems that it trims somehow (and somewhat) the ports data_out and
estado.

My code (uartrx.vhd), the User Constraints File (uartrx.ucf) and the
sinthesis report (uartrx.plg) are attached to this post.

If I comment this lines in uartrx.ucf file, the entity uartrx gets
implemented (translated, maped and PARed) with no (??) problems.

Does anybody know what is going on?

Any help would be appreciated (is this how it is spelled?)

Thanks in advance,

Gonzalo Arana
--------------E9F3687F7A4CAA6C614FC7F9
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 filename="uartrx.vhd"

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

------------------------------------------------------------------------------------
-- UART RX (version 0.0):
--   Entidad que implementa la parte receptora de una UART RS-232.
--   El diagrama descriptivo que aparece a continuacion explica en forma detallada
-- como funciona (supone 7 bits de datos, sin paridad y solo se muestra un bit
-- de stop)
--
--        stt bit  bit 0  bit 1    bit 2   bit 3    bit 4  bit 5  bit 6    stp
-- ______         _______ _______ _______ _______ _______ _______ _______ _______ 
--       |       |       |       |       |       |       |       |       |
--       |       |       |       |       |       |       |       |       |
--       |_______|_______|_______|_______|_______|_______|_______|_______|
--
--   
--  IDLE        |STTBIT
--
--  El clock suministrado debe tener una frecuencia 8 veces mayor que la de bits.
--  Ej, si estamos a 9600 bits/s (9600 baudios), clock debe ser de 76800 Hz (8 x
--  76800).

--  Cuando termina de recibir un byte, pone el byte recibido en data_out y done en 1.
--  Cuando se termina de recibir el bit de start del proximo byte, done vuelve a 0.

-- crc_error: se puede utilizar como clock para un contador de la cantidad de errores
-- de crc.

entity uartrx is
  
  port (
    data_in  : in  std_logic;                      -- serial data in
    clock    : in  std_logic;                      -- clock
    bits7    : in  std_logic;                      -- si los datos vienen en 7 bits
    parity   : in  std_logic;                      -- si los datos vienen con paridad
    even     : in  std_logic;                      -- si vienen con paridad par
    reset    : in  std_logic;                      -- resetea el estado de la uartrx
    done     : out std_logic;                      -- done = '1' => data_out es valido
    data_out : out std_logic_vector(7 downto 0);   -- datos recibidos
    crc_error: out std_logic;           -- indica si hubo un error de crc
    estado   : out std_logic_vector(1 downto 0));  -- estado que muestro afuera

end uartrx;

architecture behavioral1 of uartrx is

  -- Cada bit se samplea 8 veces, pero se toma la decision del valor (0 o 1) en
  -- base a 3 muestras (primera, ultima y alguna del medio).
  -- Cuando toma el valor de un bit, lo pone en el shift register de salida.

  -- Necesito un shift register para ir guardando los datos que voy sacando.
  signal shift_register_data_out : std_logic_vector (8 downto 0);

  -- Ademas, tengo que ir contando la cantidad de bits que me han llegado
  signal shift_register_data_out_enable : std_logic_vector (8 downto 0);
  
  -- Otro shift register para ir guardando las muestras
  signal shift_register_samples : std_logic_vector (8 downto 0);

  -- Otro para ver que posiciones del shift register anterior tienen datos validos.
  signal shift_register_samples_enable : std_logic_vector(8 downto 0);

  -- Ademas, tengo que ver cuando termine de recibir un bit
--  signal finished_bit : std_logic;

  -- Si estoy recibiendo un byte o haciendo nada.
  signal receiving_byte : std_logic;

  -- De todas las muestras que tengo, de alguna forma tengo que decidir entre la
  -- mejor decicion
  signal bestchoice : std_logic;

  -- Paridad calculada para el byte recibido.
  signal pi7, pi8 : std_logic;          -- paridad impar de 7/8 bits de datos

begin  -- behavioral1

  pi7 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
         shift_register_data_out(3) xor shift_register_data_out(4) xor
         shift_register_data_out(5) xor shift_register_data_out(6) xor
         shift_register_data_out(7);

  pi8 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
         shift_register_data_out(3) xor shift_register_data_out(4) xor
         shift_register_data_out(5) xor shift_register_data_out(6) xor
         shift_register_data_out(7) xor shift_register_data_out(8);

  bestchoice <= (shift_register_samples(1) and shift_register_samples(3)) or
                (shift_register_samples(3) and shift_register_samples(7)) or
                (shift_register_samples(7) and shift_register_samples(1));

  -- purpose: Samplea y va generando el vector de salida shift_register_data_out
  -- type   : sequential
  -- inputs : clock, reset, data_in
  -- outputs: shift_register_data_out
  SampleAndRead: process (clock, reset)
  begin  -- process SampleAndRead
    if reset = '1' then                 -- asynchronous reset (active high)
      shift_register_data_out        <= "000000000";
      shift_register_data_out_enable <= "000000000";
      shift_register_samples_enable  <= "000000000";
      shift_register_samples         <= "000000000";
      receiving_byte <= '0';
      done           <= '0';
      crc_error      <= '0';
      estado         <= "11";
      data_out       <= "00000000";
    elsif clock'event and clock = '1' then  -- rising clock edge
      -- tomo la muestra de data_in
      shift_register_samples <= shift_register_samples(7 downto 0) & data_in;

      if receiving_byte = '0' then
        -- si todavia no recibi el bit de start
        if shift_register_samples_enable(8) = '1' and
          shift_register_samples = "100000000" then
          -- si acabo de recibir el bit de start. =>
          receiving_byte <= '1';
          shift_register_samples_enable  <= "000000001";
          shift_register_data_out_enable <= "000000000";
          shift_register_data_out <= shift_register_data_out (7 downto 0) & bestchoice;
          estado <= "00";
          crc_error <= '0';
        else
          shift_register_samples_enable <= shift_register_samples_enable(7 downto 0) & '1';
        end if;
      else
        -- si estoy recibiendo un byte, y recibi el ultimo bit (el bit pasado
        -- fue el ultimo)
        if (bits7 = '1' and parity = '0' and shift_register_data_out_enable (6) = '1') or
          (bits7 = '1' and parity = '1' and shift_register_data_out_enable (7) = '1') or
          (bits7 = '0' and parity = '1' and shift_register_data_out_enable (8) = '1') or
          (bits7 = '0' and parity = '0' and shift_register_data_out_enable (7) = '1') then
          receiving_byte <= '0';        -- ya termine de recibir el byte
          -- si no tengo errores de paridad, considero que vino sin problemas
          if (parity = '0') or (parity = '1' and
            ((bits7 = '0' and even = '0' and pi8 = shift_register_data_out(8)) or
             (bits7 = '0' and even = '1' and not pi8 = shift_register_data_out(8)) or
             (bits7 = '1' and even = '0' and pi7 = shift_register_data_out(7)) or
             (bits7 = '1' and even = '1' and not pi7 = shift_register_data_out(7))))
          then
            done <= '1';
            data_out <= shift_register_data_out(8 downto 1);
          else
            crc_error <= '1';
          end if;
        end if;
        -- si estoy recibiendo un byte, y termine con este bit => 
        if shift_register_samples_enable(7) = '1' then
          shift_register_data_out <= shift_register_data_out (7 downto 0) & bestchoice;
          shift_register_data_out_enable <= shift_register_data_out_enable(7 downto 0) & '1';
          shift_register_samples_enable <= "000000001";
          estado <= "10";
          done <= '0';
        else
          shift_register_samples_enable <= shift_register_samples_enable(7 downto 0) & '1';
        end if;
      end if;
    end if;
  end process SampleAndRead;

end behavioral1;

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NET "data_in" LOC = "p3";
NET "clock" LOC = "p92";
NET "bits7" LOC = "p5";
NET "parity" LOC = "p6";
NET "even" LOC = "p7";
NET "reset" LOC = "p9";
NET "done" LOC = "p10";
NET "data_out" LOC = "p11";
NET "crc_error" LOC = "p12";
NET "estado" LOC = "p17";


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 filename="uartrx.plg"


=========================================================================
----  Global Settings
Tmp directory                      : .
DUMPDIR                            : .
overwrite                          : YES

=========================================================================


XST D.22
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

--> Parameter TMPDIR set to .
 
--> Parameter DUMPDIR set to .
 
--> Parameter overwrite set to YES
 
--> =========================================================================
---- Source Parameters
Input File Name                    : uartrx.prj
Input Format                       : VHDL

---- Target Parameters
Output File Name                   : uartrx.edn
Output Format                      : EDIF

---- Source Options
Entity Name                        : uartrx
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
HDL Verbose Level                  : 1
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Resolution Style                   : WIRE_MS

---- FSM Options
FSM Flip-Flop Type                 : D

---- Target Options
Family                             : Xilinx_Virtex
Device                             : V300E-PQ240-6
Macro Generator                    : Macro+
Add IO Buffers                     : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Keep Hierarchy                     : NO

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Global Optimization                : AllClockNets
Incremental Synthesis              : NO

=========================================================================

Compiling vhdl file C:\Xilinx_WebPACK\data\webpack\genff.vhd in Library genff.
Entity <g_depc> (Architecture <behavioral>) compiled.
Entity <g_tpc> (Architecture <behavioral>) compiled.
Entity <g_latpc> (Architecture <behavioral>) compiled.
Compiling vhdl file E:\fiuba\TProf\Diseno\tests\xilinx\testrs232\uartrx.vhd in Library work.
Entity <uartrx> (Architecture <behavioral1>) compiled.

Analyzing Entity <uartrx> (Architecture <behavioral1>).
Entity <uartrx> analyzed. Unit <uartrx> generated.


Synthesizing Unit <uartrx>.
    Extracting 1-bit register for signal <shift_register_samples<8>>.
    Extracting 1-bit register for signal <shift_register_samples<7>>.
    Extracting 1-bit register for signal <shift_register_samples<6>>.
    Extracting 1-bit register for signal <shift_register_samples<5>>.
    Extracting 1-bit register for signal <shift_register_samples<4>>.
    Extracting 1-bit register for signal <shift_register_samples<3>>.
    Extracting 1-bit register for signal <shift_register_samples<2>>.
    Extracting 1-bit register for signal <shift_register_samples<1>>.
    Extracting 1-bit register for signal <shift_register_samples<0>>.
    Extracting 9-bit register for signal <shift_register_data_out>.
    Extracting 9-bit register for signal <shift_register_data_out_enable>.
    Extracting 9-bit register for signal <shift_register_samples_enable>.
    Extracting 1-bit register for signal <receiving_byte>.
    Extracting 1-bit register for signal <done>.
    Extracting 1-bit register for signal <crc_error>.
    Extracting 2-bit register for signal <estado>.
    Extracting 8-bit register for signal <data_out>.
    Extracting 1-bit 2-to-1 multiplexer for internal node.
    Extracting 1-bit xor7 for signal <pi7>.
    Extracting 1-bit xor2 for signal <pi8>.
    Extracting 1-bit xor2 for internal node.
    Extracting 1-bit xor2 for internal node.
    Extracting 1-bit xor2 for internal node.
    Extracting 1-bit xor2 for internal node.
    Summary:
	inferred  49 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   6 Xor(s).
Unit <uartrx> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 17
  1-bit register                   : 12
  9-bit register                   : 3
  2-bit register                   : 1
  8-bit register                   : 1
# Multiplexers                     : 1
  1-bit 2-to-1 multiplexer         : 1
# Xors                             : 6
  1-bit xor7                       : 1
  1-bit xor2                       : 5

=========================================================================


Starting low level synthesis...
Optimizing unit <LPM_XOR7_1> ...

Optimizing unit <uartrx> ...

Building and optimizing final netlist ...

FlipFlop receiving_byte has been replicated 1 time(s)
=========================================================================
Final Results
Top Level Output File Name         : uartrx.edn
Output Format                      : EDIF
crit                               : Speed
Users Target Library File Name     : Virtex
Keep Hierarchy                     : NO
Macro Generator                    : Macro+

Design Statistics
# IOs                              : 18

Cell Usage :
# BELS                             : 54
#      GND                         : 1
#      LUT1                        : 2
#      LUT2                        : 8
#      LUT3                        : 9
#      LUT4                        : 27
#      MUXF5                       : 6
#      VCC                         : 1
# FlipFlops/Latches                : 50
#      FDC                         : 18
#      FDCE                        : 30
#      FDPE                        : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 17
#      IBUF                        : 5
#      OBUF                        : 12
=========================================================================
 

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.329ns (Maximum Frequency: 88.269MHz)
   Minimum input arrival time before clock: 9.477ns
   Maximum output required time before clock: 6.887ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
   Path from Clock 'clock' rising to Clock 'clock' rising : 11.329ns
   (Slack: -11.329ns)
                            Gate     Net
Cell:in->out      fanout   Delay   Delay  Logical Name
----------------------------------------  ------------
FDCE:C->Q              5   1.065   1.566  shift_register_data_out_7
LUT3:I2->O             7   0.573   1.755  I18_I_Xo3
LUT3:I0->O             1   0.573   1.035  I_9_LUT_12
LUT4:I3->O             1   0.573   1.035  I_7_LUT_36_SW1
LUT3:I2->O             8   0.573   1.845  I__n0014
FDCE:CE                    0.736          I_data_out_3
----------------------------------------
Total                     11.329ns

-------------------------------------------------------------------------
   Path from Port 'parity' to Clock 'clock' rising : 9.477ns
   (Slack: -9.477ns)
                            Gate     Net
Cell:in->out      fanout   Delay   Delay  Logical Name
----------------------------------------  ------------
IBUF:I->O              9   0.768   1.908  parity_IBUF
LUT4:I2->O             1   0.573   0.000  I_XXL_157_G
MUXF5:I1->O            3   0.134   1.332  I_XXL_157
LUT4:I2->O             1   0.573   1.035  I_7_LUT_36_SW1
LUT3:I2->O             8   0.573   1.845  I__n0014
FDCE:CE                    0.736          I_data_out_3
----------------------------------------
Total                      9.477ns

-------------------------------------------------------------------------
   Path from Clock 'clock' rising to Port 'crc_error' : 6.887ns
    (Slack: -6.887ns)
                            Gate     Net
Cell:in->out      fanout   Delay   Delay  Logical Name
----------------------------------------  ------------
FDCE:C->Q              1   1.065   1.035  I_crc_error
OBUF:I->O                  4.787          crc_error_OBUF
----------------------------------------
Total                      6.887ns

=========================================================================
 
--> 

--------------E9F3687F7A4CAA6C614FC7F9--


Article: 32917
Subject: Re: need help implementing state diagram of a 2input mealy machine!
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 11 Jul 2001 21:57:54 +0100
Links: << >>  << T >>  << A >>


Chez wrote:

>   No...its a Mealy machine..either state diagram or asm.  I prefer the state
> diagram because its move understandable to me.
> "Philip Freidin" <philip@fliptronics.com> wrote in message
> news:mqepkts26scsqjkdliqiqasuikvpatvhqg@4ax.com...
> > This homework assignment sounds much moore like a more state machine.
> >
> > On Wed, 11 Jul 2001 15:31:33 -0700, "Chez" <yuugy09@bellsouth.net> wrote:
> > >  I'm trying to implement a 2-input Mealy machine that produces a 1 as
> its
> > >single output when the values of the 2 inputs differ at the time of the
> > >previous clock pulse.  Any help would be much appreciated!
> > >
> > >
> >
> > Philip Freidin
> > Fliptronics

... and some of them flip by unnoticed except for a discerning few.



Article: 32918
Subject: Re: need help implementing state diagram of a 2input mealy machine!
From: Kolja Sulimma <kolja@sulimma.de>
Date: Wed, 11 Jul 2001 23:10:33 +0200
Links: << >>  << T >>  << A >>
But as a mealy machine you need twice as many states as with a moore machine!
(two instead of one)

Kolja

Chez wrote:

>   No...its a Mealy machine..either state diagram or asm.  I prefer the state
> diagram because its move understandable to me.
> "Philip Freidin" <philip@fliptronics.com> wrote in message
> news:mqepkts26scsqjkdliqiqasuikvpatvhqg@4ax.com...
> > This homework assignment sounds much moore like a more state machine.
> >
> > On Wed, 11 Jul 2001 15:31:33 -0700, "Chez" <yuugy09@bellsouth.net> wrote:
> > >  I'm trying to implement a 2-input Mealy machine that produces a 1 as
> its
> > >single output when the values of the 2 inputs differ at the time of the
> > >previous clock pulse.  Any help would be much appreciated!
> > >
> > >
> >
> > Philip Freidin
> > Fliptronics


Article: 32919
Subject: Re: WebPACK problem
From: Jennifer Jenkins <jennifer.jenkins@xilinx.com>
Date: Wed, 11 Jul 2001 15:40:03 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------37E5A6B0998F2E7121A30E39
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Content-Transfer-Encoding: 7bit

Gonzalo,

It appears that the data_out and estado signals are specified as VHDL STD_LOGIC_VECTOR signals.
In the UCF, you need to assign each bit in the vector to a specific pin.  Try this syntax:

NET "estado[0] LOC = "p72";
NET "estado[1] LOC = "p71";
(These pin locations are for a XCR3128XL - VQ100 package)

For more help, check out XAPP352, here's the link:  http://www.xilinx.com/xapp/xapp352.pdf

Let me know if this doesn't help,
Jennifer

Gonzalo Arana wrote:

> Hi,
>
> I am writing a RS-232 UART, since I couln't find any sinthesizable one
> with the ability to receive 7/8 data bits and check parity (even or
> odd).  The transmitter works great, but the receiver has a problem: when
> I try to translate it (with WebPACK) I get
>
> Annotating constraints to design from file "uartrx.ucf" ...
> ERROR:NgdBuild:397 - Could not find NET 'data_out' in design 'uartrx'.
> NET
>    entry is 'NET "data_out" LOC = "p11";
>    '
> ERROR:NgdBuild:397 - Could not find NET 'estado' in design 'uartrx'.
> NET entry
>    is 'NET "estado" LOC = "p17";
>
> So, it seems that it trims somehow (and somewhat) the ports data_out and
> estado.
>
> My code (uartrx.vhd), the User Constraints File (uartrx.ucf) and the
> sinthesis report (uartrx.plg) are attached to this post.
>
> If I comment this lines in uartrx.ucf file, the entity uartrx gets
> implemented (translated, maped and PARed) with no (??) problems.
>
> Does anybody know what is going on?
>
> Any help would be appreciated (is this how it is spelled?)
>
> Thanks in advance,
>
> Gonzalo Arana
>
>   ------------------------------------------------------------------------
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.NUMERIC_STD.ALL;
>
> ------------------------------------------------------------------------------------
> -- UART RX (version 0.0):
> --   Entidad que implementa la parte receptora de una UART RS-232.
> --   El diagrama descriptivo que aparece a continuacion explica en forma detallada
> -- como funciona (supone 7 bits de datos, sin paridad y solo se muestra un bit
> -- de stop)
> --
> --        stt bit  bit 0  bit 1    bit 2   bit 3    bit 4  bit 5  bit 6    stp
> -- ______         _______ _______ _______ _______ _______ _______ _______ _______
> --       |       |       |       |       |       |       |       |       |
> --       |       |       |       |       |       |       |       |       |
> --       |_______|_______|_______|_______|_______|_______|_______|_______|
> --
> --
> --  IDLE        |STTBIT
> --
> --  El clock suministrado debe tener una frecuencia 8 veces mayor que la de bits.
> --  Ej, si estamos a 9600 bits/s (9600 baudios), clock debe ser de 76800 Hz (8 x
> --  76800).
>
> --  Cuando termina de recibir un byte, pone el byte recibido en data_out y done en 1.
> --  Cuando se termina de recibir el bit de start del proximo byte, done vuelve a 0.
>
> -- crc_error: se puede utilizar como clock para un contador de la cantidad de errores
> -- de crc.
>
> entity uartrx is
>
>   port (
>     data_in  : in  std_logic;                      -- serial data in
>     clock    : in  std_logic;                      -- clock
>     bits7    : in  std_logic;                      -- si los datos vienen en 7 bits
>     parity   : in  std_logic;                      -- si los datos vienen con paridad
>     even     : in  std_logic;                      -- si vienen con paridad par
>     reset    : in  std_logic;                      -- resetea el estado de la uartrx
>     done     : out std_logic;                      -- done = '1' => data_out es valido
>     data_out : out std_logic_vector(7 downto 0);   -- datos recibidos
>     crc_error: out std_logic;           -- indica si hubo un error de crc
>     estado   : out std_logic_vector(1 downto 0));  -- estado que muestro afuera
>
> end uartrx;
>
> architecture behavioral1 of uartrx is
>
>   -- Cada bit se samplea 8 veces, pero se toma la decision del valor (0 o 1) en
>   -- base a 3 muestras (primera, ultima y alguna del medio).
>   -- Cuando toma el valor de un bit, lo pone en el shift register de salida.
>
>   -- Necesito un shift register para ir guardando los datos que voy sacando.
>   signal shift_register_data_out : std_logic_vector (8 downto 0);
>
>   -- Ademas, tengo que ir contando la cantidad de bits que me han llegado
>   signal shift_register_data_out_enable : std_logic_vector (8 downto 0);
>
>   -- Otro shift register para ir guardando las muestras
>   signal shift_register_samples : std_logic_vector (8 downto 0);
>
>   -- Otro para ver que posiciones del shift register anterior tienen datos validos.
>   signal shift_register_samples_enable : std_logic_vector(8 downto 0);
>
>   -- Ademas, tengo que ver cuando termine de recibir un bit
> --  signal finished_bit : std_logic;
>
>   -- Si estoy recibiendo un byte o haciendo nada.
>   signal receiving_byte : std_logic;
>
>   -- De todas las muestras que tengo, de alguna forma tengo que decidir entre la
>   -- mejor decicion
>   signal bestchoice : std_logic;
>
>   -- Paridad calculada para el byte recibido.
>   signal pi7, pi8 : std_logic;          -- paridad impar de 7/8 bits de datos
>
> begin  -- behavioral1
>
>   pi7 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
>          shift_register_data_out(3) xor shift_register_data_out(4) xor
>          shift_register_data_out(5) xor shift_register_data_out(6) xor
>          shift_register_data_out(7);
>
>   pi8 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
>          shift_register_data_out(3) xor shift_register_data_out(4) xor
>          shift_register_data_out(5) xor shift_register_data_out(6) xor
>          shift_register_data_out(7) xor shift_register_data_out(8);
>
>   bestchoice <= (shift_register_samples(1) and shift_register_samples(3)) or
>                 (shift_register_samples(3) and shift_register_samples(7)) or
>                 (shift_register_samples(7) and shift_register_samples(1));
>
>   -- purpose: Samplea y va generando el vector de salida shift_register_data_out
>   -- type   : sequential
>   -- inputs : clock, reset, data_in
>   -- outputs: shift_register_data_out
>   SampleAndRead: process (clock, reset)
>   begin  -- process SampleAndRead
>     if reset = '1' then                 -- asynchronous reset (active high)
>       shift_register_data_out        <= "000000000";
>       shift_register_data_out_enable <= "000000000";
>       shift_register_samples_enable  <= "000000000";
>       shift_register_samples         <= "000000000";
>       receiving_byte <= '0';
>       done           <= '0';
>       crc_error      <= '0';
>       estado         <= "11";
>       data_out       <= "00000000";
>     elsif clock'event and clock = '1' then  -- rising clock edge
>       -- tomo la muestra de data_in
>       shift_register_samples <= shift_register_samples(7 downto 0) & data_in;
>
>       if receiving_byte = '0' then
>         -- si todavia no recibi el bit de start
>         if shift_register_samples_enable(8) = '1' and
>           shift_register_samples = "100000000" then
>           -- si acabo de recibir el bit de start. =>
>           receiving_byte <= '1';
>           shift_register_samples_enable  <= "000000001";
>           shift_register_data_out_enable <= "000000000";
>           shift_register_data_out <= shift_register_data_out (7 downto 0) & bestchoice;
>           estado <= "00";
>           crc_error <= '0';
>         else
>           shift_register_samples_enable <= shift_register_samples_enable(7 downto 0) & '1';
>         end if;
>       else
>         -- si estoy recibiendo un byte, y recibi el ultimo bit (el bit pasado
>         -- fue el ultimo)
>         if (bits7 = '1' and parity = '0' and shift_register_data_out_enable (6) = '1') or
>           (bits7 = '1' and parity = '1' and shift_register_data_out_enable (7) = '1') or
>           (bits7 = '0' and parity = '1' and shift_register_data_out_enable (8) = '1') or
>           (bits7 = '0' and parity = '0' and shift_register_data_out_enable (7) = '1') then
>           receiving_byte <= '0';        -- ya termine de recibir el byte
>           -- si no tengo errores de paridad, considero que vino sin problemas
>           if (parity = '0') or (parity = '1' and
>             ((bits7 = '0' and even = '0' and pi8 = shift_register_data_out(8)) or
>              (bits7 = '0' and even = '1' and not pi8 = shift_register_data_out(8)) or
>              (bits7 = '1' and even = '0' and pi7 = shift_register_data_out(7)) or
>              (bits7 = '1' and even = '1' and not pi7 = shift_register_data_out(7))))
>           then
>             done <= '1';
>             data_out <= shift_register_data_out(8 downto 1);
>           else
>             crc_error <= '1';
>           end if;
>         end if;
>         -- si estoy recibiendo un byte, y termine con este bit =>
>         if shift_register_samples_enable(7) = '1' then
>           shift_register_data_out <= shift_register_data_out (7 downto 0) & bestchoice;
>           shift_register_data_out_enable <= shift_register_data_out_enable(7 downto 0) & '1';
>           shift_register_samples_enable <= "000000001";
>           estado <= "10";
>           done <= '0';
>         else
>           shift_register_samples_enable <= shift_register_samples_enable(7 downto 0) & '1';
>         end if;
>       end if;
>     end if;
>   end process SampleAndRead;
>
> end behavioral1;
>
>   ------------------------------------------------------------------------
> NET "data_in" LOC = "p3";
> NET "clock" LOC = "p92";
> NET "bits7" LOC = "p5";
> NET "parity" LOC = "p6";
> NET "even" LOC = "p7";
> NET "reset" LOC = "p9";
> NET "done" LOC = "p10";
> NET "data_out" LOC = "p11";
> NET "crc_error" LOC = "p12";
> NET "estado" LOC = "p17";
>
>   ------------------------------------------------------------------------
>
> =========================================================================
> ----  Global Settings
> Tmp directory                      : .
> DUMPDIR                            : .
> overwrite                          : YES
>
> =========================================================================
>
> XST D.22
> Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.
>
> --> Parameter TMPDIR set to .
>
> --> Parameter DUMPDIR set to .
>
> --> Parameter overwrite set to YES
>
> --> =========================================================================
> ---- Source Parameters
> Input File Name                    : uartrx.prj
> Input Format                       : VHDL
>
> ---- Target Parameters
> Output File Name                   : uartrx.edn
> Output Format                      : EDIF
>
> ---- Source Options
> Entity Name                        : uartrx
> Automatic FSM Extraction           : YES
> FSM Encoding Algorithm             : Auto
> HDL Verbose Level                  : 1
> RAM Extraction                     : Yes
> RAM Style                          : Auto
> Mux Extraction                     : YES
> Mux Style                          : Auto
> Decoder Extraction                 : YES
> Priority Encoder Extraction        : YES
> Shift Register Extraction          : YES
> Logical Shifter Extraction         : YES
> XOR Collapsing                     : YES
> Resource Sharing                   : YES
> Complex Clock Enable Extraction    : YES
> Resolution Style                   : WIRE_MS
>
> ---- FSM Options
> FSM Flip-Flop Type                 : D
>
> ---- Target Options
> Family                             : Xilinx_Virtex
> Device                             : V300E-PQ240-6
> Macro Generator                    : Macro+
> Add IO Buffers                     : YES
> Add Generic Clock Buffer(BUFG)     : 4
> Global Maximum Fanout              : 100
> Keep Hierarchy                     : NO
>
> ---- General Options
> Optimization Criterion             : Speed
> Optimization Effort                : 1
> Global Optimization                : AllClockNets
> Incremental Synthesis              : NO
>
> =========================================================================
>
> Compiling vhdl file C:\Xilinx_WebPACK\data\webpack\genff.vhd in Library genff.
> Entity <g_depc> (Architecture <behavioral>) compiled.
> Entity <g_tpc> (Architecture <behavioral>) compiled.
> Entity <g_latpc> (Architecture <behavioral>) compiled.
> Compiling vhdl file E:\fiuba\TProf\Diseno\tests\xilinx\testrs232\uartrx.vhd in Library work.
> Entity <uartrx> (Architecture <behavioral1>) compiled.
>
> Analyzing Entity <uartrx> (Architecture <behavioral1>).
> Entity <uartrx> analyzed. Unit <uartrx> generated.
>
> Synthesizing Unit <uartrx>.
>     Extracting 1-bit register for signal <shift_register_samples<8>>.
>     Extracting 1-bit register for signal <shift_register_samples<7>>.
>     Extracting 1-bit register for signal <shift_register_samples<6>>.
>     Extracting 1-bit register for signal <shift_register_samples<5>>.
>     Extracting 1-bit register for signal <shift_register_samples<4>>.
>     Extracting 1-bit register for signal <shift_register_samples<3>>.
>     Extracting 1-bit register for signal <shift_register_samples<2>>.
>     Extracting 1-bit register for signal <shift_register_samples<1>>.
>     Extracting 1-bit register for signal <shift_register_samples<0>>.
>     Extracting 9-bit register for signal <shift_register_data_out>.
>     Extracting 9-bit register for signal <shift_register_data_out_enable>.
>     Extracting 9-bit register for signal <shift_register_samples_enable>.
>     Extracting 1-bit register for signal <receiving_byte>.
>     Extracting 1-bit register for signal <done>.
>     Extracting 1-bit register for signal <crc_error>.
>     Extracting 2-bit register for signal <estado>.
>     Extracting 8-bit register for signal <data_out>.
>     Extracting 1-bit 2-to-1 multiplexer for internal node.
>     Extracting 1-bit xor7 for signal <pi7>.
>     Extracting 1-bit xor2 for signal <pi8>.
>     Extracting 1-bit xor2 for internal node.
>     Extracting 1-bit xor2 for internal node.
>     Extracting 1-bit xor2 for internal node.
>     Extracting 1-bit xor2 for internal node.
>     Summary:
>         inferred  49 D-type flip-flop(s).
>         inferred   1 Multiplexer(s).
>         inferred   6 Xor(s).
> Unit <uartrx> synthesized.
>
> =========================================================================
> HDL Synthesis Report
>
> Macro Statistics
> # Registers                        : 17
>   1-bit register                   : 12
>   9-bit register                   : 3
>   2-bit register                   : 1
>   8-bit register                   : 1
> # Multiplexers                     : 1
>   1-bit 2-to-1 multiplexer         : 1
> # Xors                             : 6
>   1-bit xor7                       : 1
>   1-bit xor2                       : 5
>
> =========================================================================
>
> Starting low level synthesis...
> Optimizing unit <LPM_XOR7_1> ...
>
> Optimizing unit <uartrx> ...
>
> Building and optimizing final netlist ...
>
> FlipFlop receiving_byte has been replicated 1 time(s)
> =========================================================================
> Final Results
> Top Level Output File Name         : uartrx.edn
> Output Format                      : EDIF
> crit                               : Speed
> Users Target Library File Name     : Virtex
> Keep Hierarchy                     : NO
> Macro Generator                    : Macro+
>
> Design Statistics
> # IOs                              : 18
>
> Cell Usage :
> # BELS                             : 54
> #      GND                         : 1
> #      LUT1                        : 2
> #      LUT2                        : 8
> #      LUT3                        : 9
> #      LUT4                        : 27
> #      MUXF5                       : 6
> #      VCC                         : 1
> # FlipFlops/Latches                : 50
> #      FDC                         : 18
> #      FDCE                        : 30
> #      FDPE                        : 2
> # Clock Buffers                    : 1
> #      BUFGP                       : 1
> # IO Buffers                       : 17
> #      IBUF                        : 5
> #      OBUF                        : 12
> =========================================================================
>
>
> =========================================================================
> TIMING REPORT
>
> NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
>       FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
>       GENERATED AFTER PLACE-and-ROUTE.
>
> Timing Summary:
> ---------------
> Speed Grade: -6
>
>    Minimum period: 11.329ns (Maximum Frequency: 88.269MHz)
>    Minimum input arrival time before clock: 9.477ns
>    Maximum output required time before clock: 6.887ns
>    Maximum combinational path delay: No path found
>
> Timing Detail:
> --------------
> All values displayed in nanoseconds (ns)
>
> -------------------------------------------------------------------------
>    Path from Clock 'clock' rising to Clock 'clock' rising : 11.329ns
>    (Slack: -11.329ns)
>                             Gate     Net
> Cell:in->out      fanout   Delay   Delay  Logical Name
> ----------------------------------------  ------------
> FDCE:C->Q              5   1.065   1.566  shift_register_data_out_7
> LUT3:I2->O             7   0.573   1.755  I18_I_Xo3
> LUT3:I0->O             1   0.573   1.035  I_9_LUT_12
> LUT4:I3->O             1   0.573   1.035  I_7_LUT_36_SW1
> LUT3:I2->O             8   0.573   1.845  I__n0014
> FDCE:CE                    0.736          I_data_out_3
> ----------------------------------------
> Total                     11.329ns
>
> -------------------------------------------------------------------------
>    Path from Port 'parity' to Clock 'clock' rising : 9.477ns
>    (Slack: -9.477ns)
>                             Gate     Net
> Cell:in->out      fanout   Delay   Delay  Logical Name
> ----------------------------------------  ------------
> IBUF:I->O              9   0.768   1.908  parity_IBUF
> LUT4:I2->O             1   0.573   0.000  I_XXL_157_G
> MUXF5:I1->O            3   0.134   1.332  I_XXL_157
> LUT4:I2->O             1   0.573   1.035  I_7_LUT_36_SW1
> LUT3:I2->O             8   0.573   1.845  I__n0014
> FDCE:CE                    0.736          I_data_out_3
> ----------------------------------------
> Total                      9.477ns
>
> -------------------------------------------------------------------------
>    Path from Clock 'clock' rising to Port 'crc_error' : 6.887ns
>     (Slack: -6.887ns)
>                             Gate     Net
> Cell:in->out      fanout   Delay   Delay  Logical Name
> ----------------------------------------  ------------
> FDCE:C->Q              1   1.065   1.035  I_crc_error
> OBUF:I->O                  4.787          crc_error_OBUF
> ----------------------------------------
> Total                      6.887ns
>
> =========================================================================
>
> -->

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begin:vcard 
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tel;fax:(505) 858-3106
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url:http://www.xilinx.com
org:Xilinx CoolRunner CPLDs;<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx">
adr:;;7801 Jefferson St. NE;Albuquerque;New Mexico;87109;
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email;internet:Jennifer.Jenkins@xilinx.com
title:Applications Engineer
fn:Jennifer Jenkins
end:vcard

--------------37E5A6B0998F2E7121A30E39--


Article: 32920
Subject: need help implementing state diagram of a 2input mealy machine!
From: "Chez" <yuugy09@bellsouth.net>
Date: Wed, 11 Jul 2001 15:31:33 -0700
Links: << >>  << T >>  << A >>
  I'm trying to implement a 2-input Mealy machine that produces a 1 as its
single output when the values of the 2 inputs differ at the time of the
previous clock pulse.  Any help would be much appreciated!




Article: 32921
Subject: Re: need help implementing state diagram of a 2input mealy machine!
From: "Chez" <yuugy09@bellsouth.net>
Date: Wed, 11 Jul 2001 15:44:57 -0700
Links: << >>  << T >>  << A >>
  No...its a Mealy machine..either state diagram or asm.  I prefer the state
diagram because its move understandable to me.
"Philip Freidin" <philip@fliptronics.com> wrote in message
news:mqepkts26scsqjkdliqiqasuikvpatvhqg@4ax.com...
> This homework assignment sounds much moore like a more state machine.
>
> On Wed, 11 Jul 2001 15:31:33 -0700, "Chez" <yuugy09@bellsouth.net> wrote:
> >  I'm trying to implement a 2-input Mealy machine that produces a 1 as
its
> >single output when the values of the 2 inputs differ at the time of the
> >previous clock pulse.  Any help would be much appreciated!
> >
> >
>
> Philip Freidin
> Fliptronics




Article: 32922
Subject: Re: WebPACK problem
From: Gonzalo Arana <gonzaloa@sinectis.com.ar>
Date: Wed, 11 Jul 2001 21:00:46 -0300
Links: << >>  << T >>  << A >>
Jennifer,

Two words: "UPS!" and "crystal".
Thank you very much for your quick answer (and sory for my silly post),

Gonzalo

Jennifer Jenkins wrote:
> 
> Gonzalo,
> 
> It appears that the data_out and estado signals are specified as VHDL STD_LOGIC_VECTOR signals.
> In the UCF, you need to assign each bit in the vector to a specific pin.  Try this syntax:
> 
> NET "estado[0] LOC = "p72";
> NET "estado[1] LOC = "p71";
> (These pin locations are for a XCR3128XL - VQ100 package)
> 
> For more help, check out XAPP352, here's the link:  http://www.xilinx.com/xapp/xapp352.pdf
> 
> Let me know if this doesn't help,
> Jennifer
> 
> Gonzalo Arana wrote:
> 
> > Hi,
> >
> > I am writing a RS-232 UART, since I couln't find any sinthesizable one
> > with the ability to receive 7/8 data bits and check parity (even or
> > odd).  The transmitter works great, but the receiver has a problem: when
> > I try to translate it (with WebPACK) I get
> >
> > Annotating constraints to design from file "uartrx.ucf" ...
> > ERROR:NgdBuild:397 - Could not find NET 'data_out' in design 'uartrx'.
> > NET
> >    entry is 'NET "data_out" LOC = "p11";
> >    '
> > ERROR:NgdBuild:397 - Could not find NET 'estado' in design 'uartrx'.
> > NET entry
> >    is 'NET "estado" LOC = "p17";
> >
> > So, it seems that it trims somehow (and somewhat) the ports data_out and
> > estado.
> >
> > My code (uartrx.vhd), the User Constraints File (uartrx.ucf) and the
> > sinthesis report (uartrx.plg) are attached to this post.
> >
> > If I comment this lines in uartrx.ucf file, the entity uartrx gets
> > implemented (translated, maped and PARed) with no (??) problems.
> >
> > Does anybody know what is going on?
> >
> > Any help would be appreciated (is this how it is spelled?)
> >
> > Thanks in advance,
> >
> > Gonzalo Arana
> >
> >   ------------------------------------------------------------------------
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> > use IEEE.NUMERIC_STD.ALL;
> >
> > ------------------------------------------------------------------------------------
> > -- UART RX (version 0.0):
> > --   Entidad que implementa la parte receptora de una UART RS-232.
> > --   El diagrama descriptivo que aparece a continuacion explica en forma detallada
> > -- como funciona (supone 7 bits de datos, sin paridad y solo se muestra un bit
> > -- de stop)
> > --
> > --        stt bit  bit 0  bit 1    bit 2   bit 3    bit 4  bit 5  bit 6    stp
> > -- ______         _______ _______ _______ _______ _______ _______ _______ _______
> > --       |       |       |       |       |       |       |       |       |
> > --       |       |       |       |       |       |       |       |       |
> > --       |_______|_______|_______|_______|_______|_______|_______|_______|
> > --
> > --
> > --  IDLE        |STTBIT
> > --
> > --  El clock suministrado debe tener una frecuencia 8 veces mayor que la de bits.
> > --  Ej, si estamos a 9600 bits/s (9600 baudios), clock debe ser de 76800 Hz (8 x
> > --  76800).
> >
> > --  Cuando termina de recibir un byte, pone el byte recibido en data_out y done en 1.
> > --  Cuando se termina de recibir el bit de start del proximo byte, done vuelve a 0.
> >
> > -- crc_error: se puede utilizar como clock para un contador de la cantidad de errores
> > -- de crc.
> >
> > entity uartrx is
> >
> >   port (
> >     data_in  : in  std_logic;                      -- serial data in
> >     clock    : in  std_logic;                      -- clock
> >     bits7    : in  std_logic;                      -- si los datos vienen en 7 bits
> >     parity   : in  std_logic;                      -- si los datos vienen con paridad
> >     even     : in  std_logic;                      -- si vienen con paridad par
> >     reset    : in  std_logic;                      -- resetea el estado de la uartrx
> >     done     : out std_logic;                      -- done = '1' => data_out es valido
> >     data_out : out std_logic_vector(7 downto 0);   -- datos recibidos
> >     crc_error: out std_logic;           -- indica si hubo un error de crc
> >     estado   : out std_logic_vector(1 downto 0));  -- estado que muestro afuera
> >
> > end uartrx;
> >
> > architecture behavioral1 of uartrx is
> >
> >   -- Cada bit se samplea 8 veces, pero se toma la decision del valor (0 o 1) en
> >   -- base a 3 muestras (primera, ultima y alguna del medio).
> >   -- Cuando toma el valor de un bit, lo pone en el shift register de salida.
> >
> >   -- Necesito un shift register para ir guardando los datos que voy sacando.
> >   signal shift_register_data_out : std_logic_vector (8 downto 0);
> >
> >   -- Ademas, tengo que ir contando la cantidad de bits que me han llegado
> >   signal shift_register_data_out_enable : std_logic_vector (8 downto 0);
> >
> >   -- Otro shift register para ir guardando las muestras
> >   signal shift_register_samples : std_logic_vector (8 downto 0);
> >
> >   -- Otro para ver que posiciones del shift register anterior tienen datos validos.
> >   signal shift_register_samples_enable : std_logic_vector(8 downto 0);
> >
> >   -- Ademas, tengo que ver cuando termine de recibir un bit
> > --  signal finished_bit : std_logic;
> >
> >   -- Si estoy recibiendo un byte o haciendo nada.
> >   signal receiving_byte : std_logic;
> >
> >   -- De todas las muestras que tengo, de alguna forma tengo que decidir entre la
> >   -- mejor decicion
> >   signal bestchoice : std_logic;
> >
> >   -- Paridad calculada para el byte recibido.
> >   signal pi7, pi8 : std_logic;          -- paridad impar de 7/8 bits de datos
> >
> > begin  -- behavioral1
> >
> >   pi7 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
> >          shift_register_data_out(3) xor shift_register_data_out(4) xor
> >          shift_register_data_out(5) xor shift_register_data_out(6) xor
> >          shift_register_data_out(7);
> >
> >   pi8 <= shift_register_data_out(1) xor shift_register_data_out(2) xor
> >          shift_register_data_out(3) xor shift_register_data_out(4) xor
> >          shift_register_data_out(5) xor shift_register_data_out(6) xor
> >          shift_register_data_out(7) xor shift_register_data_out(8);
> >
> >   bestchoice <= (shift_register_samples(1) and shift_register_samples(3)) or
> >                 (shift_register_samples(3) and shift_register_samples(7)) or
> >                 (shift_register_samples(7) and shift_register_samples(1));
> >
> >   -- purpose: Samplea y va generando el vector de salida shift_register_data_out
> >   -- type   : sequential
> >   -- inputs : clock, reset, data_in
> >   -- outputs: shift_register_data_out
> >   SampleAndRead: process (clock, reset)
> >   begin  -- process SampleAndRead
> >     if reset = '1' then                 -- asynchronous reset (active high)
> >       shift_register_data_out        <= "000000000";
> >       shift_register_data_out_enable <= "000000000";
> >       shift_register_samples_enable  <= "000000000";
> >       shift_register_samples         <= "000000000";
> >       receiving_byte <= '0';
> >       done           <= '0';
> >       crc_error      <= '0';
> >       estado         <= "11";
> >       data_out       <= "00000000";
> >     elsif clock'event and clock = '1' then  -- rising clock edge
> >       -- tomo la muestra de data_in
> >       shift_register_samples <= shift_register_samples(7 downto 0) & data_in;
> >
> >       if receiving_byte = '0' then
> >         -- si todavia no recibi el bit de start
> >         if shift_register_samples_enable(8) = '1' and
> >           shift_register_samples = "100000000" then
> >           -- si acabo de recibir el bit de start. =>
> >           receiving_byte <= '1';
> >           shift_register_samples_enable  <= "000000001";
> >           shift_register_data_out_enable <= "000000000";
> >           shift_register_data_out <= shift_register_data_out (7 downto 0) & bestchoice;
> >           estado <= "00";
> >           crc_error <= '0';
> >         else
> >           shift_register_samples_enable <= shift_register_samples_enable(7 downto 0) & '1';
> >         end if;
> >       else
> >         -- si estoy recibiendo un byte, y recibi el ultimo bit (el bit pasado
> >         -- fue el ultimo)
> >         if (bits7 = '1' and parity = '0' and shift_register_data_out_enable (6) = '1') or
> >           (bits7 = '1' and parity = '1' and shift_register_data_out_enable (7) = '1') or
> >           (bits7 = '0' and parity = '1' and shift_register_data_out_enable (8) = '1') or
> >           (bits7 = '0' and parity = '0' and shift_register_data_out_enable (7) = '1') then
> >           receiving_byte <= '0';        -- ya termine de recibir el byte
> >           -- si no tengo errores de paridad, considero que vino sin problemas
> >           if (parity = '0') or (parity = '1' and
> >             ((bits7 = '0' and even = '0' and pi8 = shift_register_data_out(8)) or
> >              (bits7 = '0' and even = '1' and not pi8 = shift_register_data_out(8)) or
> >              (bits7 = '1' and even = '0' and pi7 = shift_register_data_out(7)) or
> >              (bits7 = '1' and even = '1' and not pi7 = shift_register_data_out(7))))
> >           then
> >             done <= '1';
> >             data_out <= shift_register_data_out(8 downto 1);
> >           else
> >             crc_error <= '1';
> >           end if;
> >         end if;
> >         -- si estoy recibiendo un byte, y termine con este bit =>
> >         if shift_register_samples_enable(7) = '1' then
> >           shift_register_data_out <= shift_register_data_out (7 downto 0) & bestchoice;
> >           shift_register_data_out_enable <= shift_register_data_out_enable(7 downto 0) & '1';
> >           shift_register_samples_enable <= "000000001";
> >           estado <= "10";
> >           done <= '0';
> >         else
> >           shift_register_samples_enable <= shift_register_samples_enable(7 downto 0) & '1';
> >         end if;
> >       end if;
> >     end if;
> >   end process SampleAndRead;
> >
> > end behavioral1;
> >
> >   ------------------------------------------------------------------------
> > NET "data_in" LOC = "p3";
> > NET "clock" LOC = "p92";
> > NET "bits7" LOC = "p5";
> > NET "parity" LOC = "p6";
> > NET "even" LOC = "p7";
> > NET "reset" LOC = "p9";
> > NET "done" LOC = "p10";
> > NET "data_out" LOC = "p11";
> > NET "crc_error" LOC = "p12";
> > NET "estado" LOC = "p17";
> >
> >   ------------------------------------------------------------------------
> >
> > =========================================================================
> > ----  Global Settings
> > Tmp directory                      : .
> > DUMPDIR                            : .
> > overwrite                          : YES
> >
> > =========================================================================
> >
> > XST D.22
> > Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.
> >
> > --> Parameter TMPDIR set to .
> >
> > --> Parameter DUMPDIR set to .
> >
> > --> Parameter overwrite set to YES
> >
> > --> =========================================================================
> > ---- Source Parameters
> > Input File Name                    : uartrx.prj
> > Input Format                       : VHDL
> >
> > ---- Target Parameters
> > Output File Name                   : uartrx.edn
> > Output Format                      : EDIF
> >
> > ---- Source Options
> > Entity Name                        : uartrx
> > Automatic FSM Extraction           : YES
> > FSM Encoding Algorithm             : Auto
> > HDL Verbose Level                  : 1
> > RAM Extraction                     : Yes
> > RAM Style                          : Auto
> > Mux Extraction                     : YES
> > Mux Style                          : Auto
> > Decoder Extraction                 : YES
> > Priority Encoder Extraction        : YES
> > Shift Register Extraction          : YES
> > Logical Shifter Extraction         : YES
> > XOR Collapsing                     : YES
> > Resource Sharing                   : YES
> > Complex Clock Enable Extraction    : YES
> > Resolution Style                   : WIRE_MS
> >
> > ---- FSM Options
> > FSM Flip-Flop Type                 : D
> >
> > ---- Target Options
> > Family                             : Xilinx_Virtex
> > Device                             : V300E-PQ240-6
> > Macro Generator                    : Macro+
> > Add IO Buffers                     : YES
> > Add Generic Clock Buffer(BUFG)     : 4
> > Global Maximum Fanout              : 100
> > Keep Hierarchy                     : NO
> >
> > ---- General Options
> > Optimization Criterion             : Speed
> > Optimization Effort                : 1
> > Global Optimization                : AllClockNets
> > Incremental Synthesis              : NO
> >
> > =========================================================================
> >
> > Compiling vhdl file C:\Xilinx_WebPACK\data\webpack\genff.vhd in Library genff.
> > Entity <g_depc> (Architecture <behavioral>) compiled.
> > Entity <g_tpc> (Architecture <behavioral>) compiled.
> > Entity <g_latpc> (Architecture <behavioral>) compiled.
> > Compiling vhdl file E:\fiuba\TProf\Diseno\tests\xilinx\testrs232\uartrx.vhd in Library work.
> > Entity <uartrx> (Architecture <behavioral1>) compiled.
> >
> > Analyzing Entity <uartrx> (Architecture <behavioral1>).
> > Entity <uartrx> analyzed. Unit <uartrx> generated.
> >
> > Synthesizing Unit <uartrx>.
> >     Extracting 1-bit register for signal <shift_register_samples<8>>.
> >     Extracting 1-bit register for signal <shift_register_samples<7>>.
> >     Extracting 1-bit register for signal <shift_register_samples<6>>.
> >     Extracting 1-bit register for signal <shift_register_samples<5>>.
> >     Extracting 1-bit register for signal <shift_register_samples<4>>.
> >     Extracting 1-bit register for signal <shift_register_samples<3>>.
> >     Extracting 1-bit register for signal <shift_register_samples<2>>.
> >     Extracting 1-bit register for signal <shift_register_samples<1>>.
> >     Extracting 1-bit register for signal <shift_register_samples<0>>.
> >     Extracting 9-bit register for signal <shift_register_data_out>.
> >     Extracting 9-bit register for signal <shift_register_data_out_enable>.
> >     Extracting 9-bit register for signal <shift_register_samples_enable>.
> >     Extracting 1-bit register for signal <receiving_byte>.
> >     Extracting 1-bit register for signal <done>.
> >     Extracting 1-bit register for signal <crc_error>.
> >     Extracting 2-bit register for signal <estado>.
> >     Extracting 8-bit register for signal <data_out>.
> >     Extracting 1-bit 2-to-1 multiplexer for internal node.
> >     Extracting 1-bit xor7 for signal <pi7>.
> >     Extracting 1-bit xor2 for signal <pi8>.
> >     Extracting 1-bit xor2 for internal node.
> >     Extracting 1-bit xor2 for internal node.
> >     Extracting 1-bit xor2 for internal node.
> >     Extracting 1-bit xor2 for internal node.
> >     Summary:
> >         inferred  49 D-type flip-flop(s).
> >         inferred   1 Multiplexer(s).
> >         inferred   6 Xor(s).
> > Unit <uartrx> synthesized.
> >
> > =========================================================================
> > HDL Synthesis Report
> >
> > Macro Statistics
> > # Registers                        : 17
> >   1-bit register                   : 12
> >   9-bit register                   : 3
> >   2-bit register                   : 1
> >   8-bit register                   : 1
> > # Multiplexers                     : 1
> >   1-bit 2-to-1 multiplexer         : 1
> > # Xors                             : 6
> >   1-bit xor7                       : 1
> >   1-bit xor2                       : 5
> >
> > =========================================================================
> >
> > Starting low level synthesis...
> > Optimizing unit <LPM_XOR7_1> ...
> >
> > Optimizing unit <uartrx> ...
> >
> > Building and optimizing final netlist ...
> >
> > FlipFlop receiving_byte has been replicated 1 time(s)
> > =========================================================================
> > Final Results
> > Top Level Output File Name         : uartrx.edn
> > Output Format                      : EDIF
> > crit                               : Speed
> > Users Target Library File Name     : Virtex
> > Keep Hierarchy                     : NO
> > Macro Generator                    : Macro+
> >
> > Design Statistics
> > # IOs                              : 18
> >
> > Cell Usage :
> > # BELS                             : 54
> > #      GND                         : 1
> > #      LUT1                        : 2
> > #      LUT2                        : 8
> > #      LUT3                        : 9
> > #      LUT4                        : 27
> > #      MUXF5                       : 6
> > #      VCC                         : 1
> > # FlipFlops/Latches                : 50
> > #      FDC                         : 18
> > #      FDCE                        : 30
> > #      FDPE                        : 2
> > # Clock Buffers                    : 1
> > #      BUFGP                       : 1
> > # IO Buffers                       : 17
> > #      IBUF                        : 5
> > #      OBUF                        : 12
> > =========================================================================
> >
> >
> > =========================================================================
> > TIMING REPORT
> >
> > NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
> >       FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
> >       GENERATED AFTER PLACE-and-ROUTE.
> >
> > Timing Summary:
> > ---------------
> > Speed Grade: -6
> >
> >    Minimum period: 11.329ns (Maximum Frequency: 88.269MHz)
> >    Minimum input arrival time before clock: 9.477ns
> >    Maximum output required time before clock: 6.887ns
> >    Maximum combinational path delay: No path found
> >
> > Timing Detail:
> > --------------
> > All values displayed in nanoseconds (ns)
> >
> > -------------------------------------------------------------------------
> >    Path from Clock 'clock' rising to Clock 'clock' rising : 11.329ns
> >    (Slack: -11.329ns)
> >                             Gate     Net
> > Cell:in->out      fanout   Delay   Delay  Logical Name
> > ----------------------------------------  ------------
> > FDCE:C->Q              5   1.065   1.566  shift_register_data_out_7
> > LUT3:I2->O             7   0.573   1.755  I18_I_Xo3
> > LUT3:I0->O             1   0.573   1.035  I_9_LUT_12
> > LUT4:I3->O             1   0.573   1.035  I_7_LUT_36_SW1
> > LUT3:I2->O             8   0.573   1.845  I__n0014
> > FDCE:CE                    0.736          I_data_out_3
> > ----------------------------------------
> > Total                     11.329ns
> >
> > -------------------------------------------------------------------------
> >    Path from Port 'parity' to Clock 'clock' rising : 9.477ns
> >    (Slack: -9.477ns)
> >                             Gate     Net
> > Cell:in->out      fanout   Delay   Delay  Logical Name
> > ----------------------------------------  ------------
> > IBUF:I->O              9   0.768   1.908  parity_IBUF
> > LUT4:I2->O             1   0.573   0.000  I_XXL_157_G
> > MUXF5:I1->O            3   0.134   1.332  I_XXL_157
> > LUT4:I2->O             1   0.573   1.035  I_7_LUT_36_SW1
> > LUT3:I2->O             8   0.573   1.845  I__n0014
> > FDCE:CE                    0.736          I_data_out_3
> > ----------------------------------------
> > Total                      9.477ns
> >
> > -------------------------------------------------------------------------
> >    Path from Clock 'clock' rising to Port 'crc_error' : 6.887ns
> >     (Slack: -6.887ns)
> >                             Gate     Net
> > Cell:in->out      fanout   Delay   Delay  Logical Name
> > ----------------------------------------  ------------
> > FDCE:C->Q              1   1.065   1.035  I_crc_error
> > OBUF:I->O                  4.787          crc_error_OBUF
> > ----------------------------------------
> > Total                      6.887ns
> >
> > =========================================================================
> >
> > -->

Article: 32923
Subject: Erasing Altera EPC-1441?
From: jbaker@halcyon.com (James Baker)
Date: Wed, 11 Jul 2001 18:49:29 -0700
Links: << >>  << T >>  << A >>
Does anyone know how to erase and Altera EPC-1441 configuration device
(serial EPROM)?  I have the Altera MP-6 (ISA card) and MPU programmer with
PLMJ-1213 adapter on loan from Altera, but I'll get or make different
programming/erasing hardware if I have to.

The literature says they're OTP but I know I've erased and reused them
before. I just can't remember how, and I'd like to reuse the several
thousand devices I have.

Thanks.

-- 
James Baker
Seattle, WA
jbaker@halcyon.com

Article: 32924
Subject: Xilinx makefile under RedHat
From: "Clyde R. Visser" <res05jpt@gte.net>
Date: Thu, 12 Jul 2001 01:53:04 GMT
Links: << >>  << T >>  << A >>

Someone some time back said that they do 95% of their
xilinx builds under RedHat and had a URL documenting it.
Anybody have the related URL?

crv





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