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Messages from 33025

Article: 33025
Subject: Re: Xilinx PCI development board
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Sun, 15 Jul 2001 18:19:11 -0500
Links: << >>  << T >>  << A >>
Also http://www.nallatech.com/
Ballynuey3: High Performance PCI DIME Motherboard With Xilinx VirtexT-II

http://www.nallatech.com/products/dime_professional/ballynuey3/index_en.htm




Article: 33026
Subject: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
From: Hong <lvhong@aol.com>
Date: Sun, 15 Jul 2001 16:57:28 -0700
Links: << >>  << T >>  << A >>
Hi Alex,
Solution for problem(1) and (2):
Inserting the tristate Buffers BUFT(x) to all the signals, which are connected to the BUS, then recompile it, you might see the warning messages like "WARNING : (HDL__0001). Signal <XXXX(y)>> has a multisource." Just ignore it, that's all.

BTW, which Xilinx Foundation are you using? V3.3i?

Hope this helps,
Hong

Article: 33027
Subject: Re: Which Chip Family?
From: cjwang_1225@hotmail.com (chris)
Date: 15 Jul 2001 17:15:05 -0700
Links: << >>  << T >>  << A >>
as far as i know, the the spartan-2 development board is one of the
best and cheapest i have seen (the one from burch electronic designs).
it sounds to me like you are worrying about too many details, when
instead, you should be writing code and making sure it will work
inside any fpga. if you are truly just starting, you should
concentrate on writing synthesizable code first, since this concept is
the hardest to understand for newbies. then, you should be able to
create a test platform to exercies your code, ie: testbench. if you
cannot get this far, then having the latest and greatest fpga, or even
cpld, etc... will be of no use to you. if you do write the code and
synthesize it, then there is still many things you need to do such as
place and route it, analyze the timing, constrain the design, and
finally the last step is the download. if you want to do a design,
know what you are designing. if you just want to do a networking
project, then be more specific than network switching, since network
switching is actually quite complex. anyways, the main point is the
downloading the fpga is the last thing you want to do in your design.
the bulk of the time is spent making it work in your simulation
environment since finding a bug in simulation is an order of magnitude
easier than debugging in the hardware environment. just do the design
and then you will know enough about fpgas to know what you want.
chris

Article: 33028
Subject: Re: Design entry
From: Keith R. Williams <krw@attglobal.net>
Date: Sun, 15 Jul 2001 20:47:34 -0400
Links: << >>  << T >>  << A >>
In article <3B51E407.80E2FE21@mail.com>, johnhandwork@mail.com 
says...
> Say, can we still buy TTL?  DTL?  RTL?

Sure.  Iv'e got some stuff with '72-'74 date codes on 'em... 
Wanna buy?  ;-)  

...other than that, it's the CMOS stuff and much of that is hard 
to come by.

----
  Keith

Article: 33029
Subject: Re: Which Chip Family?
From: "Tony Burch" <tony@BurchED.com.au>
Date: Mon, 16 Jul 2001 12:02:02 +1000
Links: << >>  << T >>  << A >>
Suhaib,

> I've seen your plug many times before! While it seems quite good, I

Thanks :)

> don't like the fact that it's all on ribbon cables. Specifically, I
> worry that the download cable bit will break. Does it include JTAG
> connections?
>

The cables are all really robust.  I have some units here that
have been used alot, will all kinds of pulling, twisting, plugging,
unplugging etc etc.  Not a single breakage or failure in all
that time.

The main B3-SPARTAN2+ board has two download
header connectors on it.  One for JTAG download, and one
for serial mode download.  So you can choose your
preferred download method, JTAG or serial mode.
The three download mode pins M0, M1 and M1
are jumper programmable on the board.

Best regards
Tony Burch
http://www.BurchED.com.au
Lowest cost, easy-to-use
FPGA prototyping kits!

> To everyone else:
>
> What is the difference between Spartan-II and Virtex-II, what
> different markets are they targeted at, and what are the different
> features? Why chose one over another?
>
> Thanks.
>
>
>
> "Tony Burch" <tony@BurchED.com.au> wrote in message
news:<3b50f1d9@news1.idx.com.au>...
> > Suhaib,
> >
> > You may wish to consider the low cost
> > SpartanII board from Burch Electronic Designs:
> > http://www.burched.com.au/bedspartan2.html
> >
> > It has a 200K gate SpartanII device, configuration
> > download pod and cable, a header programmable
> > PLL oscillator (1-100MHz), and it works with
> > the free Xilinx WebPACK design software.
> > All for less than US$120 !
> >
> > Best regards
> > Tony Burch
> > http://www.BurchED.com.au
> > Lowest cost, easy-to-use
> > FPGA prototyping kits!



Article: 33030
Subject: Re: FPGA Express search path
From: srinivasan_v@india.com (Srinivasan Venkataramanan)
Date: 15 Jul 2001 23:22:13 -0700
Links: << >>  << T >>  << A >>
Hi,

anilkateel@rediffmail.com (Anil) wrote in message news:<f1a78ec4.0107132313.518c8b1@posting.google.com>...
> There is no search path concept in FPGA Express/Compiler.
> 
> So when you include a verilog file using `include directive 
> you need to make sure that the file is in the same directoy 
> where as the original verilog file exists.
> 
> There are 3 solutions for this :-
> (1)If suppose u have a file /a/b/c/test.v which has a `include x.v
>    and if x.v is not there under /a/b/c/ DIRECTORY then just create 
>    a link to x.v under /a/b/c/ pointing it to it's original location.
>    link -s <original x.v path>/x.v /a/b/c/x.v
> (2)Copy x.v to /a/b/c/ directory. 
> (3)Just chnage `include x.v to `include <locattoin to x.v>/x.v (Hard to do !!!)
> 

  Is +incdir option supported by FPGAExpress? It is a defacto standard
option that directs the Verilog compilers where to look for the
included files.

Srini

Article: 33031
Subject: Polyphase filter question
From: dottavio@ised.it (Antonio)
Date: 15 Jul 2001 23:55:41 -0700
Links: << >>  << T >>  << A >>
Good Morning, my question is this  :
Matlab design for me a polyphase filter using the function rcosflt ,
the number of coefficient produced is function of the interpolation
rate (...why ??) in particular for interpolation 3 I've 19
coefficients, for interpolation 4 I've 25 coefficients and for
interpolation 6 I've 37 coefficients .
This means that I always have 1 fir with 7 taps and
(interpolation_rate -1) filters with 6 taps , so I had think to
produce only one polyphase filter that interpolate 6 and when I want
to interpolate 3 I use the first 3 FIR, when I want to interpolate 4 I
use the first 4 FIR and when I want interpolate & I use all 6 FIR ,
naturally the coefficients are programmable.
I would want to ask you if this is correct by your point of view ...

Thank you in any case ...


Antonio D'Ottavio

Article: 33032
(removed)


Article: 33033
Subject: DDS Xilinx Core
From: dottavio@ised.it (Antonio)
Date: 16 Jul 2001 00:03:46 -0700
Links: << >>  << T >>  << A >>
The DDS core is not in the evaluation CD but it is on the site that
tell me that I could have it with the evaluation CD, Do you know well
how can I have this core ?? Thanks in advance ..

                       Antonio D'Ottavio

Article: 33034
Subject: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
From: arast@qwest.net (Alex Rast)
Date: Mon, 16 Jul 2001 07:19:05 GMT
Links: << >>  << T >>  << A >>
In article <ee7173c.0@WebX.sUN8CHnE>, Hong <lvhong@aol.com> wrote:
>Hi Alex,
>Solution for problem(1) and (2):
>Inserting the tristate Buffers BUFT(x) to all the signals, which are connected
> to the BUS, then recompile it, you might see the warning messages like
> "WARNING : (HDL__0001). Signal <XXXX(y)>> has a multisource." Just ignore it,
> that's all.

Well, I would have thought that I should be able to ignore it, but the 
implementation refuses to compile, even though I have as you suggest tristate 
buffers at the outputs (how else, I wonder, would you *want* to implement a 
bus?) And it doensn't appear, through an examination of the log, that anything 
else is wrong. So it does at least seem as though Xilinx doesn't like it, 
regardless of what it should like. 

>
>BTW, which Xilinx Foundation are you using? V3.3i?

2.1i at the moment. We bugged our rep a while back to get us the 3.3i 
software, but so far it hasn't arrived. I have been on them a few times about 
this. It didn't help that the main FAE at our XIlinx dist'y moved on to 
another job. The new guy is going to take a while getting up to speed on what 
his customers need.

Alex Rast
arast@qwest.net
arast@inficom.com

Article: 33035
Subject: can not create a distributed Memory
From: bhamon@elios-informatique.fr (=?ISO-8859-1?Q?Beno=EEt?=)
Date: 16 Jul 2001 01:35:51 -0700
Links: << >>  << T >>  << A >>
Hi everyone,

I am using foundation 3.1 with service pack 8, and IP core4.

I can't create a distributed Memory4.1 (Memories & Storage
Elements/RAMs & ROMs) for a Virtex2.
ERROR: Unable to open file for Memory Initialization:
D:\Projets\memory.mif
ERROR: An internal error has occurred.  To resolve this error, please
consult the Answers Database at http://support.xilinx.com
ERROR: Sim has a problem implementing the selected core.
Implementation netlist will not be generated.
ERROR: SimGenerator: Failure of Sim to implement customization
parameters core memory
ERROR: Core memory did not generate EDIF implementation netlist (.EDN)
file.
ERROR: The .XSF symbol generation support file cannot be generated
because it requires an implementation netlist.
WARNING: Warnings and/or errors encountered while generating memory
(Distributed_Memory 4.1) All output products requested may not have
been generated.
ERROR: Elaboration failure for core Distributed_Memory
 
ERROR: Elaboration of core Distributed_Memory failed.

Does any body knowing way how to avoid that problem? 

Thanks

Benoit.

Article: 33036
Subject: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
From: "PYD" <pierre-yves.duniau@oceano-technologies.fr>
Date: Mon, 16 Jul 2001 11:13:03 +0200
Links: << >>  << T >>  << A >>
for information ...

http://www.freecore.com/nosupport/blaster.htm



Article: 33037
Subject: Book Recommendation (bit different)
From: safahmy@hotmail.com (SAF)
Date: 16 Jul 2001 02:30:00 -0700
Links: << >>  << T >>  << A >>
Ok,

I am looking for a good introductory book, not to VHDL, but more to
the whole shebang behind design of FPGAs. I've done courses in college
on Digital Electronics, and some practicals with Altera PLDs, but I'd
like a way of putting things together. Questions like:

-How to design with the target architecture in mind
-Good and bad practice
-Efficient use of HDL
-Interfacing with other devices
-Timing considerations

The more modern the book, the better. I'll probably be getting
Ashenden's "Designer's Guide to VHDL"/2e anyway, so I need something
which would be a good complement. If it covers Xilinx chips, even
better.

Also, what resources might I use to get in tune with my target
Architecture? Is it just a matter of data sheets and experience?

The sorts of terms puzzling me:
-Block RAM - how do you use these?
-Distributed RAM
-DLLs - what are they for?
-Cascade Chains
-Different types of clocks (I know wat a clock does, but what're all
the different types?)

As you can see these are the questions of an ignorant beginner. Hence
the sort of book I need.

Thanks all.

Article: 33038
Subject: Re: Design entry
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 16 Jul 2001 14:24:03 +0100
Links: << >>  << T >>  << A >>


"Keith R. Williams" wrote:

> In article <3B51E407.80E2FE21@mail.com>, johnhandwork@mail.com
> says...
> > Say, can we still buy TTL?  DTL?  RTL?
>
> Sure.  Iv'e got some stuff with '72-'74 date codes on 'em...
> Wanna buy?  ;-)
>

Maybe you should consider embedding them in perspex (plexiglass) and
selling them as charms to new age h/w designers to ward off the evil
metastability demon. I'd buy one to ward off s/w engineers who think a
critical path is the route to the nearest pub (bar).


Article: 33039
Subject: Re: Byteblasting an ACEX in running system?
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Mon, 16 Jul 2001 14:04:39 GMT
Links: << >>  << T >>  << A >>
Sould be no problem if the dsp has no problems with tri state pins.
But how are the config pins driven on the board original?
You could get a contention with the byte blaster.

Martin
--
Whant to see the evolution of a Java processor?

         http://www.jopdesign.com

"Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag
news:3B4D8E87.31046A07@iprimus.com.au...
> Hi all,
>
> I've got a dsp driving an altera ep1k30, and was wondering if its
> ok to reprogram that chip even tho the dsp is still driving it.
> I've got a byteblaster connected to it. I read somewhere that
> all(?) the pins go to tri-state when programming (passive serial).
>
> --
>    ___                                           ___
>   /  /\                                         /  /\
>  /  /__\                                       /  /\/\
> /__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
> \  \  /  Victoria, Australia, Down-Under      \  \/\/
>  \__\/                                         \__\/
>



Article: 33040
Subject: How to set an AHDL query pattern
From: "Abhimanyu Rastogi" <abhi_rastogi@hotmail.com>
Date: Mon, 16 Jul 2001 14:47:09 GMT
Links: << >>  << T >>  << A >>
Hi all,

To query if some peice of hardware is present :-
I need to write a known bit pattern of length n=8 to a card and read the
loop back from and if i get the same pattern back....that indicates the card
is present. if its not the same indicates the card is not there...

So, how should i go about this.....

Many thx for ur help....

--
Abhimanyu Rastogi
2nd year student
University of Ottawa
Canada



Article: 33041
Subject: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Tue, 17 Jul 2001 00:47:53 +1000
Links: << >>  << T >>  << A >>
That one's old hat with the 'LS244 and all...

PYD wrote:
> 
> for information ...
> 
> http://www.freecore.com/nosupport/blaster.htm

Article: 33042
Subject: Re: Downloading file to Xilinx (Vertex_E) FPGA.
From: Werner Dreher <dreher@informatik.uni-tuebingen.de>
Date: Mon, 16 Jul 2001 16:49:46 +0200
Links: << >>  << T >>  << A >>
Subodh Nijsure wrote:
> 
> 
> Now the DONE pin goes high, and I my FPGA is seems to be doing its job.
> But what I have observed is, as soon as checksum command words are sent
> for the last block /INIT pin goes low, but if ignore that error, DONE
> pin is still going high and FPGA seems to be working okay.
> 
> I haven't tried pulling /INIT high as was suggeseted earlier. Any hints
> on why /INIT goes low?
> 
> /Subodh Nijsure

just an idea:
INIT has a weak pullup before and while configuration (?). When
configuration
is done, INIT becomes a user I/O-pin, and the pullup is disabled (?).
As you don't use INIT as user I/O, the pin is at high impedance state.
Your scope probe forces it to low.

 Werner

Article: 33043
Subject: conditional expression optimization
From: pwomack@engage.com (bugbear)
Date: 16 Jul 2001 07:51:22 -0700
Links: << >>  << T >>  << A >>
This question seems to fall somewhere between circuit design
and compiler design, so I'm hoping the denizens of this group
may be able to address it.

This expression is "clearly" replaceable by a single "false"

(a eq 10 and a eq 30)

Is there a name for this optimisation?
Is it commonly implemented?

	BugBear

Article: 33044
Subject: Re: conditional expression optimization
From: Jon <jschneider@cix.ceeowe.ewekay>
Date: 16 Jul 2001 16:01:41 +0100
Links: << >>  << T >>  << A >>
pwomack@engage.com (bugbear) writes:

> (a eq 10 and a eq 30)
> 
> Is there a name for this optimisation?

Constant folding ?

Article: 33045
Subject: Re: Design entry
From: Keith R. Williams <krw@btv.ibm.com>
Date: Mon, 16 Jul 2001 11:53:08 -0400
Links: << >>  << T >>  << A >>
In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says...
> Noddy wrote:
> > 
> > This brings me to my question? Should I rather be
> > attempting to implement my designs in VHDL instead? 
> 
> Mix it !
> A top level schematic, the units below in VHDL, Verilog, etc..
> It's amazing, already magic how easy it is to explain what you're doing
> to somebody else, when you can see all functional units, data flow on
> one sheet.
> And, sometimes you see your own design more clearly ;-)

That certainly would be an advantage.  However, I understand that 
synthesis in a mixed environment doesn't work well.  The redundancy 
isn't squished out beyond the black boxes.  

> when you like to go to HDL only, just replace one sheet to a text page.

If I could do both schematics and (V)HDL with the same toolset with the 
flattening occurring before the "real" synthesis this would be nice.  
This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs 
wile remaining productive. Listening Synplicity? ;-)

----
  Keith

Article: 33046
Subject: Re: Which Chip Family?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 16 Jul 2001 18:33:18 +0200
Links: << >>  << T >>  << A >>
Ray Andraka schrieb:
> 
> but including Spartan II doesn't make sense.  For new designs, if you are

I think it makes sense, since the Spartan-II devices are cheaper.

> not in the Spartan II, I would go with the Virtex E right now.  The Virtex

As I said.

> design into space, you're stuck with Virtex.  Personally, I'd forgo the
> 4K/Spartan (original) architecture for new designs, as the cost per gate and
> speeds are better for the later families, and the later families have a

Yes, but there are lots of applications that dont need the Multi-million
gate FPGAs. If you have some small on-on boards which needs just some
glue logic, small fifos, some uC registers etc., Spartan(XL) is just
fine and cheap. Not everyone is working everyday on cutting edge,
breakthrough designs. ;-)

> longer time horizon until they become obsolete.

Yes.

--
MfG
Falk



Article: 33047
Subject: Re: Book Recommendation (bit different)
From: cjwang_1225@hotmail.com (chris)
Date: 16 Jul 2001 10:19:33 -0700
Links: << >>  << T >>  << A >>
sounds like you should probably go to xilinx support pages and check
out the library. download all the docs that you have questions about,
print them out, and go to your local coffee shop to study them. no
book i know of has the recent developments of the ins and outs of
fpgas, especially the newer xilinx ones. if you really must have a
book, probably get "Real World FPGA Design with Verilog", assuming you
don't mind learning verilog. that book is quite useful for the basics,
but it seems like fpgas have gone a long way since then.
chris

Article: 33048
Subject: Fixing routing in a Virtex FPGA
From: rotemg@mysticom.com (Rotem Gazit)
Date: 16 Jul 2001 10:44:58 -0700
Links: << >>  << T >>  << A >>
Hi,
Is there a simple way to fix manual or automatic routing so that on
the next PR cycle it would not change ?
The only way I know to do this is by instantiating predefined macro
and I am looking for an easier way.
Thanks,

Rotem.

Rotem Gazit
MystiCom LTD
mailto:rotemg@mysticom.com
http://www.mysticom.com/

Article: 33049
Subject: Xilinx .bit file format
From: "Dave Brown" <dbrown@novatel.ca>
Date: Mon, 16 Jul 2001 11:57:17 -0600
Links: << >>  << T >>  << A >>
I have a .bit file that I converted to a .hex file with PromGEN. When I look
at this .hex file, I noticed there is only one 32 bit dummy word before the
syncronization word. I read in XAPP176 (from the Xilinx website) that there
are supposed to be 2 32 bit dummy words. Has anyone else had similar
problems? Just curious, because we can't get this .bit file to load into the
FPGA. Is there a definitive description somewhere of the header that a .bit
file should have for a Spartan II?
Thanks,
Dave






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