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Messages from 33250

Article: 33250
Subject: Re: Modelsim and bidir ports?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 20 Jul 2001 08:55:00 -0700
Links: << >>  << T >>  << A >>
khiltrop@gesytec.de wrote:
> 
> Hi
> 
> My Modelsim XE 5.3d claims
>                Incompatible modes for port abc
> with port abc being an 'inout' port.
> Is there a special trick I do not know about? How can I simulate
> bidirectional ports?
> I am using XILINX ISE 3.1i

An INOUT design port can only be connected to 
another INOUT or IN port on the testbench.
Make sure you have an output enable control
on both sides
and that the inout ports drive data or all Z
based on that control.

 --Mike Treseler

Article: 33251
Subject: Re: Async RS flip-flop (was How to see ram contents in maxplus2 simulation?)
From: robert.schoerXghuber@hoXme.inXs.de
Date: Fri, 20 Jul 2001 15:59:50 GMT
Links: << >>  << T >>  << A >>
On Fri, 20 Jul 2001 20:47:25 +1000, Russell Shaw
<rjshaw@iprimus.com.au> wrote:

>Hi,
>
>I found the SRFF library component. Unfortunately, its useless
>because it needs a clock.
>
>I have a state machine controlled case statement that sets a flag:
>srff.s=vcc. However, srff.q only changes at the next clock edge
>which is also when the transition into the next state case-statement
>happens. But this is too late for another flip-flop which clocks in
>that flag to do something else.
>
>A clockless RS flip-flop wouldn't have that problem. Are asynchronous
>things like that bad for some reason?
[...]

Hi Russel, 
 asynch stuff is hard or impossible to simulate..

One workaround (have schematics only, so a text 
description must do it):

New macro 'PseudoLatch':

- Drop in one normal D flipflop plus one 2:1 multiplexer.

- Connections:

  - DATA input: connected to flipflop's D input and 
    multiplexer's #0 input

  - LATCH input: connected to flipflop's ClockEnable and
    multiplexer's #1 input

  - CLK input: connected to flipflop's CLK input

  - Q output: connected to multiplexer output.

With LATCH high, the multiplexer passes the data 
at DATA, and at the next clock edge, the data are 
stored. With LATCH low one gets these stored data 
from the FF.

HTH,
  Robert


Article: 33252
Subject: 2nd CFP: FPGA'2002
From: tessier@spock.ecs.umass.edu (Russell Tessier)
Date: 20 Jul 2001 18:51:05 GMT
Links: << >>  << T >>  << A >>
                   FPGA 2002: Call for Papers
Tenth ACM* International Symposium on Field-Programmable Gate Arrays

	             Monterey Beach Hotel
                     Monterey, California
                     February 24-26, 2002

Submissions due: September 28, 2001
web site: http://www.ecs.umass.edu/ece/fpga2002


The annual ACM/SIGDA International Symposium on Field-Programmable 
Gate Arrays is the premier conference for presentation of advances 
in all areas related to FPGA technology. For FPGA 2002, we are 
soliciting submissions describing novel research and developments 
in the following (and related) areas of interest:


* FPGA Architecture: Combined FPGA fabric with system blocks 
  (memory, processors, etc.), Logic block & routing architectures, 
  I/O structures and circuits, new commercial architectures, 
  Field-Programmable Interconnect Chips and Devices (FPIC/FPID), 
  Field-Programmable Analog Arrays (FPAA).
* CAD for FPGAs: Placement, routing, logic optimization, 
  technology mapping, system-level partitioning, logic generators, 
  testing and verification, CAD for FPGA-based accelerators.  
  Evaluation of sensitivity of tools used for architecture 
  evaluation (i.e. VPR).
* Applications: Innovative use of FPGAs, exploitation of FPGA 
  features, novel circuits, high-performance and 
  low-power/mission-critical applications, DSP techniques, 
  uses of reconfiguration, FPGA-based cores.
* FPGA-based and FPGA-like computing engines: Compiled 
  accelerators, reconfigurable computing, adaptive computing 
  devices, systems and software.
* Rapid-prototyping: Fast prototyping for system-level design, 
  Multi-Chip Modules (MCMs), logic emulation.

Authors are invited to submit English language PDF of their paper 
(12 pages maximum) and panel proposals by September 28, 2001 by 
E-mail to fpga2002@xilinx.com.  Notification of acceptance will 
be sent by November 21, 2001.  The authors of accepted papers will 
be required to submit the final camera-ready copy by December 5, 2001.  
A proceedings of the accepted papers will be published by ACM, and 
included in the Annual ACM/SIGDA CD-ROM Compendium publication.

Address questions to:

Steve Trimberger,  Program Chair, FPGA 2002
Xilinx Corporation,
2100 Logic Drive,
San Jose, CA  95124
phone: 408-879-5061
fax: 408-559-7168
Email: fpga2002@xilinx.com

General Chair: Martine Schlag, UCSC
Program Chair: Steve Trimberger, Xilinx
Publicity Chair: Russell Tessier, U. Mass.-Amherst
Finance Chair: Scott Hauck, U. of Washington
Panel Chair: Herman Schmit, CMU


Program Committee

Ray Andraka, Andraka Consulting		Tom Kean, Algotronix 
Mike Bershteyn, Cognigine		Arun Kundu, Actel 
Vaughn Betz, Altera			Miriam Leeser, Northeastern U. 
Richard Cliff, Altera			Wayne Luk, Imperial College 
Jason Cong, UCLA			Margaret Marek-Sadowska, UCSB 
Andre DeHon, Caltech			Martine Schlag, UCSC
Eugene Ding, Agere Systems		Herman Schmit, CMU
J.M. "Marty" Emmert, UNC-Charlotte	Russ Tessier, U. Mass.-Amherst 
Scott Hauck, U. Washington		Steve Trimberger, Xilinx 
Rajeev Jayaraman, Xilinx		Steve Wilton, U. British Columbia
Sinan Kaptanoglu, Adaptive Silicon	Martin Wong, U. Texas

Sponsored by ACM SIGDA, with support from industry.*
Please visit the web site <http://www.ecs.umass.edu/ece/fpga2002> for more information.

*Pending approval

Article: 33253
Subject: Re: regarding the constraints while writing VHDL code
From: "Andy Peters <andy [@] exponentmedia" <".> com">
Date: Fri, 20 Jul 2001 19:14:41 GMT
Links: << >>  << T >>  << A >>
You might want to pick up one of the several books on writing
synthesizable VHDL code, and read it carefully.  I like Bhaskar's book.

-andy

sandeep wrote:
> 
> Hello everybody,
>               Myself is Sandeep,and is a Post Graduate student and
> doing dissertation in JPEG baseline image compression using VLSI.
> I have written a code for 2-D DCT using VHDL and simulated it, but hte
> problem is that it is not fitting in any of the CPLD or FPGA. I have
> used Xilinx 2.1 tool.Is there any solution to this problem?????????/
> My doubt is that while writing the code is it necessary to take in to
> consideration the internal architecture of the FPGA or CPLD??? If yes
> then in which manner???????/
> 
> Thanking you in anticipation
> 
> Yours
> sandeep

Article: 33254
Subject: Schematic libraries in webpack ?
From: francis_mtl@hotmail.com (Francis)
Date: 20 Jul 2001 12:17:37 -0700
Links: << >>  << T >>  << A >>
Hi,

I downloaded the latest version of WebPack and, while the schematic
editor is present, I can't find the libraries (except for the 9500 
CPLD family that I don't plan to use anyway).

I thought it was a mistake, and tried to download/install it again
but the only schematics libraries that are included are the 9500 ones.

How comes the Spartan II libraries are left out ?

It is my understanding (I might be wrong) that the WebPack is supposed 
to be an introductory package, designed to attract peoples who are 
relatively new to FPGA design, and as such, being forced to learn
VHDL (seems to be a long, and somewhat frustrating/painful road) when 
schematic is (at least for me) much easier & a lot more natural to use, 
(at least for first / simple projects) looks like a nonsense.

I understand that the free package can't include all (else, who would 
buy the ISE software ?) and older or bigger devices are left out, but
schematic entry is a basic feature, and the fastest way someone new
to FPGA can evaluate Xilinx products. Putting it aside when the "A"
brand includes it in the free package seems odd.

I know this is becoming a HDL world (I might get into it later), but 
being forced to learn it upfront makes me pause, and I'm sure I'm not 
the only one.

Will we see the libraries in the next release ?
I really hope so.

Francis.

Article: 33255
Subject: Re: Working Design - Anyone
From: "Andy Peters <andy [@] exponentmedia" <".> com">
Date: Fri, 20 Jul 2001 20:42:06 GMT
Links: << >>  << T >>  << A >>
Ummmmm, people,

This guy's a troll.

Now, where's that killfile ...

David Wright wrote:
> 
> Has anyone had a working logic design in VHDL other than a few Cypress and
> Xilinx insiders?
> 
> Logic was never this complicated before!
> 
> What a total waste of human intelligence.
> 
> It is far easier to build with discrete MSI/LSI parts or code in computer
> language than get even something simple into a small CPLD or FPGA.

Article: 33256
Subject: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Fri, 20 Jul 2001 21:48:14 +0100
Links: << >>  << T >>  << A >>
Hi,

Rick Filipkiewicz wrote:

> My conclusion from this small sample is that the P&R tool speed is
> dominated by memory performance.

With this type of application (memory hugary!) the speed of the CPU is only
any good when it has the data to process. In other words a 450, 600 or 1.4
will just spend most of its time sitting on its "bum" waiting for memory.

This was proven when Cambridge Uni fitted 4Gb of SRAM (not DRAM) to a 40Mhz
386DX - Was the fastest thing you have ever seen!!

Cyber_Spook_Man


Article: 33257
Subject: Stopping the clock in Virtex
From: Duane Clark <dclark@akamail.com>
Date: Fri, 20 Jul 2001 14:30:18 -0700
Links: << >>  << T >>  << A >>
Howdy,

I believe some previous Xilinx chips had a restriction on stopping the 
clock, and in the DLL usage notes for the Virtex-E, there is a note that 
the clock should not be stopped for greater than 100uS. But if the DLL 
is not used, is there a restriction on stopping the clock to other parts 
of the circuitry? And specifically, I was wondering about stopping the 
clock to about 500 slices within a 600E.

Duane


Article: 33258
Subject: The PC and Software Museum
From: yohyyr@nowasia.net
Date: Fri, 20 Jul 2001 22:42:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
- Do you like OLD computers and software ?
- Would you like to download some OLD Windows Versions ?


   
** THE NUMBER 1 MUSEUM FOR PERSONAL COMPUTERS AND SOFTWARE **

///////////////////////////////////////
/           www.pcmuseum.8m.net       /
///////////////////////////////////////

Featuring:

* Personal Computers
* Terminals
* Dumb Terminal Support Center
* Software Section
* Trade & Buy Market
* and MORE !

                       http://www.pcmuseum.8m.net



rszfylondufqxckdmqlfwphcltrmrxqndgytvyh


Article: 33259
Subject: Re: Async RS flip-flop (was How to see ram contents in maxplus2
From: bob elkind <eteam@aracnet.com>
Date: Fri, 20 Jul 2001 16:36:36 -0700
Links: << >>  << T >>  << A >>
Assuming the S-R input pulses are asynchronous inputs:

If the S and R input pulses to the S-R FF are narrower than a single
clock cycle, then you need edge detectors (i.e. pulse stretchers).
The edge detector outputs must then be synchronised to the system
clock, and the sync'ed outputs then drive a clocked S-R FF.

If the input pulses are wider than a clock cycle, then you can safely
synchronise the inputs and the sync'ed outputs directly drive a
clocked S-R FF.

In either case, the inputs (or edge detector outputs, if needed) need to be
synchronised to the system clock to avoid metastable conditions,
and to ensure that multiple registers respond uniformly to the async
inputs.

If the S-R inputs are already synchronous, then there shouldn't be any
issue with using a clocked S-R FF (e.g. SRFF, SRFFE).

There are undoubtedly some situations where this doesn't apply, but
for most designs (e.g. clocked synchronous designs) the above is
(and should be) standard practice.

-- Bob Elkind

Russell Shaw wrote:

> Hi,
>
> I found the SRFF library component. Unfortunately, its useless
> because it needs a clock.
>
> I have a state machine controlled case statement that sets a flag:
> srff.s=vcc. However, srff.q only changes at the next clock edge
> which is also when the transition into the next state case-statement
> happens. But this is too late for another flip-flop which clocks in
> that flag to do something else.
>
> A clockless RS flip-flop wouldn't have that problem. Are asynchronous
> things like that bad for some reason?
>
> I could fix it by inserting extra states, but that just makes things
> slower. Maybe things like flags should work on a x2 or x4 clock?



Article: 33260
Subject: Re: regarding the constraints while writing VHDL code
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Sat, 21 Jul 2001 12:40:36 +1000
Links: << >>  << T >>  << A >>
What is 'synthesizable' code, as opposed to any other VHDL ?

"Andy Peters
> 
> You might want to pick up one of the several books on writing
> synthesizable VHDL code, and read it carefully.  I like Bhaskar's book.
> 
> -andy
> 
> sandeep wrote:
> >
> > Hello everybody,
> >               Myself is Sandeep,and is a Post Graduate student and
> > doing dissertation in JPEG baseline image compression using VLSI.
> > I have written a code for 2-D DCT using VHDL and simulated it, but hte
> > problem is that it is not fitting in any of the CPLD or FPGA. I have
> > used Xilinx 2.1 tool.Is there any solution to this problem?????????/
> > My doubt is that while writing the code is it necessary to take in to
> > consideration the internal architecture of the FPGA or CPLD??? If yes
> > then in which manner???????/
> >
> > Thanking you in anticipation
> >
> > Yours
> > sandeep

--Russell

Article: 33261
Subject: Re: Modulator Sizing Questions
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 20 Jul 2001 19:42:12 -0700
Links: << >>  << T >>  << A >>
dottavio@ised.it (Antonio) writes:
[...]
> -0.0015462472598948768
> -0.0090424537413504452
> -0.0103914189205138260
> by the way how you suggest me to implement these coefficients ??

If you need 16-bit signed coefficents (15 bits plus sign), multiply
them by 32768 (2^15).  Then round them to the nearest integer.  Don't
truncate.

Remember that each decimal place of precision you need becomes log2(10)
bits in binary.

Article: 33262
Subject: I needs a saturable adder.
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Sat, 21 Jul 2001 12:51:48 +1000
Links: << >>  << T >>  << A >>
Hi all,

I need a saturable adder like the ALU in DSPs.
I thought maybe you could just sign-extend the two input
busses, add them, then detect if the result has overflowed
the input bus width. If so, the result could be saturated
to max-neg or max-pos.

AHDL seems a bit limited for handling signed numbers. I'm
learning some VHDL because it seems to have more constructs
and knows about signed/unsigned numbers.

Are there any simpler ways of doing such an adder?

--Russell

Article: 33263
Subject: Re: regarding the constraints while writing VHDL code
From: Ray Andraka <ray@andraka.com>
Date: Sat, 21 Jul 2001 04:18:27 GMT
Links: << >>  << T >>  << A >>
VHDL was originally intended to document a design through an executable
document; 'D' stands for Description, not Design.  There are many features in
the full VHDL language that are not recognized by logic synthesizers, for
example signals of type real, wait for statements, etc.  Synthesizers
generally work by matching your VHDL code against templates to determine what
logic to put in for the code.  As a result, only a relatively small subset of
the language is recognized by the synthesis tools for creating hardware from
your code.  Code that fits within that subset is considered synthesizable
code, whereas behavioral code intended to model behavior, not gates, may not
fit the templates in the synthesis tool, or may use statements that have no
translation.  In that case, even though the code is grammatically correct, it
is not synthesizable.

Russell Shaw wrote:

> What is 'synthesizable' code, as opposed to any other VHDL ?
>
> "Andy Peters
> >
> > You might want to pick up one of the several books on writing
> > synthesizable VHDL code, and read it carefully.  I like Bhaskar's book.
> >
> > -andy
> >
> > sandeep wrote:
> > >
> > > Hello everybody,
> > >               Myself is Sandeep,and is a Post Graduate student and
> > > doing dissertation in JPEG baseline image compression using VLSI.
> > > I have written a code for 2-D DCT using VHDL and simulated it, but hte
> > > problem is that it is not fitting in any of the CPLD or FPGA. I have
> > > used Xilinx 2.1 tool.Is there any solution to this problem?????????/
> > > My doubt is that while writing the code is it necessary to take in to
> > > consideration the internal architecture of the FPGA or CPLD??? If yes
> > > then in which manner???????/
> > >
> > > Thanking you in anticipation
> > >
> > > Yours
> > > sandeep
>
> --Russell

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 33264
Subject: Re: Modulator Sizing Questions
From: Ray Andraka <ray@andraka.com>
Date: Sat, 21 Jul 2001 04:38:14 GMT
Links: << >>  << T >>  << A >>


Antonio wrote:

> Good Morning,
> I'm Producing a QPSK modulator using an NCO, I use the classical
> schema including 2 branches, each with a Polyphase
> SquareRootRaisedCosine Filter whose output go to a multiplier having
> on the other input the output of the NCO , the two branches then come
> to a adder, my question is about the number of bits in the different
> part of the circuit, for example :
>
> 1) How much bits I've to use for the coefficients of the polyphase
> filter ??

Depends on the required characteristics of the filter.  As a rule of
thumb, you'll get about 5db improvement to your noise floor per bit in the
coefficient.


>
> 2) the data arriving to the polyphase are 1 and -1 so the multiply is
> reduced to invert the coefficient or not, how much bits I've to
> consider at the output providing the coefficient are expressed in
> 2'complement and are -0.0103914189205138260
> -0.0090424537413504452
> -0.0015462472598948768
> 0.0104572775382219900
> 0.0225120416117039310
> 0.0285826337727227570
> 0.0233188590342006150
> 0.0046304157926415250
> -0.0244042584244363110
> -0.0551805195177435540
> -0.0751980048558142520
> -0.0714382299222202640
> -0.0345746562804935130
> 0.0373165930609706130
> 0.1368592502236164500
> 0.2481225405617600900
> 0.3500278381428516000
> 0.4215598203650190400
> 0.4472906424227021100
> 0.4215598203650190400
> 0.3500278381428516000
> 0.2481225405617600900
> 0.1368592502236164500
> 0.0373165930609706130
> -0.0345746562804935130
> -0.0714382299222202640
> -0.0751980048558142520
> -0.0551805195177435540
> -0.0244042584244363110
> 0.0046304157926415250
> 0.0233188590342006150
> 0.0285826337727227570
> 0.0225120416117039310
> 0.0104572775382219900
> -0.0015462472598948768
> -0.0090424537413504452
> -0.0103914189205138260

Again, it depends on how much quantization error (which translates to
limits on the filter response) you are willing to live with.  The
coefficients, assuming an FPGA implementation, are most likely going to be
implemented in fixed point arithmetic.  What this means, is that
everything has a fixed scale factor (a power of two generally) associated
with it.  You will express the fractions as fractional fixed point
numbers, where each bit has a power of 2 weighting.  For fractional fixed
point, the radix point is at the left, so the bit to the right of the
radix has weight 1/2, next has weight 1/4 etc.  If you want a 16 bit
fractional notation, then you can multiply all your coefficients by 2^16
to get the integer value, and just remember that there is a scale factor.

For example, to put the the last entry in 16 bit binary form for the
hardware,  mulitply it by 2^16, convert the result to 2's complement and
then put the binary radix point on the left.  -0.0103914189205138260 *
65536 => -681.01...   =>  1111110101010111, then divided by 2^16 you get
0.11111101010101111.  The binary point is always in the same position, so
we can just ignore it.  A floating point system sets aside a field within
your word to represent the position of the binary point in the word, which
has the effect of extending the dynamic range at the expense of precision.



>
> by the way how you suggest me to implement these coefficients ??
>
> 3) If for example one input of the multiplier is 10 bits, also the
> other must be ten bits ?? and how much for the output ???
>
> 4) By the way , it is important that the inputs of the multiplier have
> the same rate ??
>
> 5) if for example the input of the following adder are both 10 bits,
> how much bits I've to provide for the output.
>
> I know many of these question could be stupid , but, how I can say,
> I've not the answer so if you have some answer also only at some of
> them I'll be really happy if you tell it to me or also if you redirect
> me to some resource speaking strictly about these thinghs ...
>
> Antonio D'Ottavio

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 33265
Subject: Re: Modulator Sizing Questions
From: Ray Andraka <ray@andraka.com>
Date: Sat, 21 Jul 2001 04:51:30 GMT
Links: << >>  << T >>  << A >>
Oops, pushed the send too fast....

Antonio wrote:

> 3) If for example one input of the multiplier is 10 bits, also the
> other must be ten bits ?? and how much for the output ???

No, you can have both inputs have arbitrary sizes.  I believe the latest
Xilinx core generator allows you to set the widths of the inputs
independently.  In your case, you do not need multipliers: each
coefficient is a constant that you are either adding to or subtracting
from the sum of products (you are multiplying by either 1 or -1), so
instead, use adder/subtractors with the signal input controlling the a/s
control.  Since this is a filter, the signal is delayed in a tapped delay
queue.  You can transpose the delay to the output side of the filter,
which allows you to perform the adds in a chain, then the structure is a
chain of adder/subtractors that have one input connected to a constant
coefficient, and the other to the output of the previous adder in the
chain.

>
>
> 4) By the way , it is important that the inputs of the multiplier have
> the same rate ??

No, but they should both change as a result of transitions on the same
clock signal.  For example, one input can change on every clock cycle
while the other only changes every 4th cycle.  The multiplier in an FPGA
is generally deeply pipelined (takes several clocks before the product of
the inputs appears on the output).

>
>
> 5) if for example the input of the following adder are both 10 bits,
> how much bits I've to provide for the output.

In your case, you know the values at the input of the adders, since they
are constants.  From these, you can compute the maximum value at the
output of each adder, which in turn tells you how many bits of
significance you need at that node.  For example, the coefficient
mentioned above (previous post) could be represented with only 11 bits
instead of the 16 without loosing any more precision than the original
quantization.  If you add that with another coefficient of similar
magnitude, you will likely need 12 bits to represent the largest possible
sum without overflow.

>
>
> I know many of these question could be stupid , but, how I can say,
> I've not the answer so if you have some answer also only at some of
> them I'll be really happy if you tell it to me or also if you redirect
> me to some resource speaking strictly about these thinghs ...
>
> Antonio D'Ottavio

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 33266
Subject: Re: SystemC
From: go_stock_boy@yahoo.com (Jeanan Del)
Date: 20 Jul 2001 22:02:49 -0700
Links: << >>  << T >>  << A >>
I haven't used it but I know Synopsys has SystemC Compiler tool that
Xilinx and Altera are helping to make work well for SystemC to FPGA
flow.

http://www.eedesign.com/story/OEG20001110S0071

I saw a pointer on SystemC web page 

http://www.systemC.org/products.html

to synthesizable subset from for Synopsys under 

http://www.synopsys.com/products/sld/rtl_systemc.pdf

The other synthesis tools on that page are from CoWare (I/F synthesis
whatever that is) and Frontier Design (for DSP)

Article: 33267
Subject: Re: what tools run OK on windows 2000?
From: Expensimundo <expensimundo@cheapskates.net>
Date: Fri, 20 Jul 2001 22:18:39 -0700
Links: << >>  << T >>  << A >>
> Cadence - NCSim and other tools - US$5K (I think, the Cadence 
> web site is rather hard to use)

Umm...no.  NC-Verilog is around $44k (USD) per license.  

I just setup an 'experimental' Linux machine at work, to
investigate the feasibility of offloading some of our 
Verilog RTL functional simulations to 'cheap' x86-PCs.

For trivially small designs (i.e < 2000 lines), a
Pentium3-800 MHz (100MHz FSB, 1024MB PC100 SDRAM) seems 
to run almost twice as fast as an Sun 
Ultrasparc-60 2360 (360MHz)!

For more 'realistic' designs, say 200-400MB RAM 
footprint (on the x86), the Pentium3-800 feels about 
10-20% faster than the same Ultrasparc, which was very 
consistent with the expectations other engineers gave me.

This is with no dumpfile/$shm_probe, etc. (I.e., minimal
disk activity.)  I don't know how performance changes with
heavy disk activity.

My next attempt will be to run some SDF-annotated gate-level
Verilog netlists through the same setup.  Unfortunately,
one of our databases is large enough that it won't fit
within 1GB RAM.

I saw similar trends with Verilog-XL, benching the same
RTL code.

So far this has been very encouraging for me.  I'll definitely
up the CPU to a 1GHz Pentium3, then wait for those dual
Athlon DDR motherboards.

Article: 33268
Subject: Re: processor core
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Sat, 21 Jul 2001 04:21:09 -0400
Links: << >>  << T >>  << A >>
There's a basically free core (24 bit) at
http://www.birdcomputer.ca/SparrowSoC.html
SoC.zip at the bottom of the page.

Are there any specific requirements ? Data size ? Code size ? Do you need
additional tools eg compiler / assembler ?
I'm currently working on a thirty-two bit core, but it won't be ready for a
few months.

"John Smith" <xyz1625us@yahoo.com> wrote in message
news:8c835672.0107170405.224a2753@posting.google.com...
> I'm looking for a small processor core that fit in a 'cheap' fpga
> leaving some space for IO.
> Free or for little cost preferred.
>
> Thanks
> John



Article: 33269
Subject: free VHDL and/or Verilog tools?
From: Philipp Krause <pkk@spth.de>
Date: Sat, 21 Jul 2001 11:03:37 +0200
Links: << >>  << T >>  << A >>
Are there any free tools around? I'd like to learn VHDL, but don't want 
to spend money on commercial software since I don't know which chip 
family I'll use when it comes to implementing something.

Philipp Krause


Article: 33270
Subject: Soldering Ceramic BGA's
From: "Anthony Ellis" <xxxa.ellis@logicworks.co.za>
Date: Sat, 21 Jul 2001 11:17:27 +0200
Links: << >>  << T >>  << A >>
This is not an FPGA question but I guess many of you may have designed
FPGA's using similar technology and work for companies that have some advice
to part with.

We have a PCB designed for a 255 pin Ceramic BGA and are struggling to
solder this correctly.  Plastic BGA's are not an issue however.
Obviously the ceramic absorbs the reflow energy but we haven't been able to
find the correct technique to pre-heat the part. I guess we could measure
the pre-heated component temperature if we had some idea about it's required
value.

Any help please.

Thanks Anthony







Article: 33271
Subject: Re: Modulator Sizing Questions
From: allanherriman@hotmail.com (Allan Herriman)
Date: 21 Jul 2001 04:16:58 -0700
Links: << >>  << T >>  << A >>
dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0107200436.79d44289@posting.google.com>...
> Good Morning,
> I'm Producing a QPSK modulator using an NCO, I use the classical
> schema including 2 branches, each with a Polyphase
> SquareRootRaisedCosine Filter whose output go to a multiplier having
> on the other input the output of the NCO , the two branches then come
> to a adder, my question is about the number of bits in the different
> part of the circuit, for example :
> 
> 1) How much bits I've to use for the coefficients of the polyphase
> filter ??
> 2) the data arriving to the polyphase are 1 and -1 so the multiply is
> reduced to invert the coefficient or not, how much bits I've to
> consider at the output providing the coefficient are expressed in
> 2'complement and are -0.0103914189205138260
> -0.0090424537413504452
> -0.0015462472598948768
> 0.0104572775382219900
> 0.0225120416117039310
> 0.0285826337727227570
> 0.0233188590342006150
> 0.0046304157926415250
> -0.0244042584244363110
> -0.0551805195177435540
> -0.0751980048558142520
> -0.0714382299222202640
> -0.0345746562804935130
> 0.0373165930609706130
> 0.1368592502236164500
> 0.2481225405617600900
> 0.3500278381428516000
> 0.4215598203650190400
> 0.4472906424227021100
> 0.4215598203650190400
> 0.3500278381428516000
> 0.2481225405617600900
> 0.1368592502236164500
> 0.0373165930609706130
> -0.0345746562804935130
> -0.0714382299222202640
> -0.0751980048558142520
> -0.0551805195177435540
> -0.0244042584244363110
> 0.0046304157926415250
> 0.0233188590342006150
> 0.0285826337727227570
> 0.0225120416117039310
> 0.0104572775382219900
> -0.0015462472598948768
> -0.0090424537413504452
> -0.0103914189205138260
> by the way how you suggest me to implement these coefficients ??
> 
> 3) If for example one input of the multiplier is 10 bits, also the
> other must be ten bits ?? and how much for the output ???
> 
> 4) By the way , it is important that the inputs of the multiplier have
> the same rate ??
> 
> 5) if for example the input of the following adder are both 10 bits,
> how much bits I've to provide for the output.
> 
> 
> I know many of these question could be stupid , but, how I can say,
> I've not the answer so if you have some answer also only at some of
> them I'll be really happy if you tell it to me or also if you redirect
> me to some resource speaking strictly about these thinghs ...
> 
> Antonio D'Ottavio

The above FIR filter could also be implemented as a lookup table of
modest size.    (2k words assuming you're using 4x oversampling -
that's 6 virtex-e blockrams for a 12 bit output or 2 virtex-2 block
rams for a 16 bit output.)  This also avoids any roundoff problems in
intermediate values, as the lookup table stores the output values
directly.
This old comp.dsp post shows how:
http://groups.google.com/groups?selm=370f778d.12757251%40newshost

Regards,
Allan.

Article: 33272
Subject: Re: free VHDL and/or Verilog tools?
From: Dave Vanden Bout <devb@xess.com>
Date: Sat, 21 Jul 2001 08:12:33 -0400
Links: << >>  << T >>  << A >>
Philipp Krause wrote:

> Are there any free tools around? I'd like to learn VHDL, but don't want
> to spend money on commercial software since I don't know which chip
> family I'll use when it comes to implementing something.
>
> Philipp Krause

Download the free WebPACK tools from Xilinx or the free Maxplus2 tools from
Altera.  Both contain VHDL and Verilog synthesizers.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



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