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Messages from 33325

Article: 33325
Subject: Re: Synchronous output enable not supported?
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Mon, 23 Jul 2001 12:09:43 -0400
Links: << >>  << T >>  << A >>
"VhdlCohen" <vhdlcohen@aol.com> wrote in message
news:20010723114205.22055.00000763@ng-fx1.aol.com...
> What kind of Flip-flop would yield a 'Z' onto its output?
> What you need to do is use a regular FF that yields a '0' or '1' as
output.
> Follow that with a concurrent signal assignmet to infer a tri-state:
> D_Output <= Qvector_FF when tri_condition = '0' else
>                    (others => 'Z');

I've written code before which synchronously assigned 'Z' to a flip-flop
output. Synplify was smart enough to figure out to create another flip-flop
whose output goes to the tri-state control.

Sounds like the synthesis tool isn't being as intelligent as it could be. I
agree with your suggestion to try a different coding style, though.

Cheers,
Jamie



Article: 33326
Subject: Re: Measuring power consumption
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 23 Jul 2001 10:18:57 -0700
Links: << >>  << T >>  << A >>
Falk,

Recently we had the opportunity to get a specific customer design, do the
simulation, and calculate the power from the node analysis using Xpower.,
and compare with their actual power in their system.

Since the simulation uses WORST CASE numbers ( and the transition file),
the actual power in the customer's system was less than that predicted.
The conculsion was "this lousy tool!!??!!..." but that is the wrong
conclusion!

In the worst case, the power might be more, and more by the amount
predicted.

I seldom get in trouble for having engineers design a power supply bigger
than the actual load, and a heat removal system more capable than what is
required.

Good engineering practice uses safety factors of 2 or 3 or 4.  Of concern
is when each person in the chain applies their X2, leading to a over
engineering of the system (X2 X2, X2 ... X8???).

Of course, the simulation file (transitions) may be inaccurate, and as the
saying goes, "garbage in, garbage out" may be exactly what was happening.

I recommend a convenient 0 ohm shunt in line with the power supplies so
that current may be conveniently measured in the prototype system in
extreme cases.

The ultimate solution is the thermal one, as watts in, will result in watts
out, as heat.

Austin

Falk Brunner wrote:

> Hello everybody,
>
> I (and I suppose many other people in this group ;-) have the problem,
> that it is really difficult to estimate AND measure the power
> consumption of a FPGA design. I know that power consumption strongly
> depends on size of the design, clock frequency and, one of the most
> difficult to estimate parameters, average toggle rate. OK, we have the
> virtex power estimator, XPower and some nice application notes, but
> after all its just a very raw guess, then we add 100% security plus a
> layout to change the power supply easy on the prototype ;-)
> But what is VERY sad is the fact, that it is mostly impossible, to
> measure the power consumption on the real, working board :-(((
> There inst just one VCC pin, there are many, all connectet to the power
> plane. Cutting the power plane and feeding the whole power over a zero
> Ohm resistor is no good idea. Socket?? With BGAs?? Signal integrity??
> Damit!!!
>
> Whats your expirience with this?
> Any hints?
>
> --
> MFG
> Falk


Article: 33327
Subject: Re: Altera ISP - JTAG
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 23 Jul 2001 19:21:34 +0200
Links: << >>  << T >>  << A >>
Michael Wichmann schrieb:
> 
> Hey Everyone,
> 
> Does anyone know how to interface from the Altera software package
> programming output to jtag.
> Altera tries to sell its serial programming cable BitBlaster for around
> $500, which IMHO is a little  overpriced ;) (since we go from serial data to
> ... yep serial data, right??)

The is AFAIK a low cost programmer (bitblaster), schematics available on
the Altera website.

-- 
MFG
Falk


Article: 33328
Subject: Re: Soldering Ceramic BGA's
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Mon, 23 Jul 2001 17:35:09 GMT
Links: << >>  << T >>  << A >>
Back in the day, when I had to do a lot of soldering, I soldered BGAs
without a lot of specialized equipment.  I would set the BGA down where it
was supposed to go, and then superglue a "corral" of SMT resistors around it
so it wouldn't be able to move during reflow.  Then I would blast it with
one of those big red hot air guns that look like hair dryers until the
solder melted.  There was no subtle technique and no need to pre-heat.

"Anthony Ellis" <xxxa.ellis@logicworks.co.za> wrote in message
news:3b594878.0@news1.mweb.co.za...
> This is not an FPGA question but I guess many of you may have designed
> FPGA's using similar technology and work for companies that have some
advice
> to part with.
>
> We have a PCB designed for a 255 pin Ceramic BGA and are struggling to
> solder this correctly.  Plastic BGA's are not an issue however.
> Obviously the ceramic absorbs the reflow energy but we haven't been able
to
> find the correct technique to pre-heat the part. I guess we could measure
> the pre-heated component temperature if we had some idea about it's
required
> value.
>
> Any help please.
>
> Thanks Anthony
>
>
>
>
>
>
>



Article: 33329
Subject: Re: Maxplus II download sites
From: Leon_Heller@hotmail.com (Leon Heller)
Date: 23 Jul 2001 10:44:15 -0700
Links: << >>  << T >>  << A >>
"Andrew Gray" <andrewgray@iafrica.com> wrote in message news:<3b5aa232.0@news1.mweb.co.za>...
> Hi
> 
> Does anyone know if there is an alternate site to download Baseline 10.1 and
> Maxplus II from?
> The Altera FTP server does not seem to support resuming, and the files are
> too big to download in one go.

Get GoZilla from http://www.gozilla.com. It automatically resumes if
you have a problem downloading large files.

Leon

Article: 33330
(removed)


Article: 33331
Subject: Re: Synchronous output enable not supported?
From: vhdlcohen@aol.com (VhdlCohen)
Date: 23 Jul 2001 18:03:23 GMT
Links: << >>  << T >>  << A >>
>"VhdlCohen" <vhdlcohen@aol.com> wrote in message
>news:20010723114205.22055.00000763@ng-fx1.aol.com...
>> What kind of Flip-flop would yield a 'Z' onto its output?
>> What you need to do is use a regular FF that yields a '0' or '1' as
>output.
>> Follow that with a concurrent signal assignmet to infer a tri-state:
>> D_Output <= Qvector_FF when tri_condition = '0' else
>>                    (others => 'Z');
>
>I've written code before which synchronously assigned 'Z' to a flip-flop
>output. Synplify was smart enough to figure out to create another flip-flop
>whose output goes to the tri-state control.
>
>Sounds like the synthesis tool isn't being as intelligent as it could be. I
>agree with your suggestion to try a different coding style, though.
>

You're correct about Synplify on automatically inferring a FF for the
condition, with the output of the FF condition driving a tri-state buffer.  

Our IEEE P1076.6 spec  is not clear  on this point.  Thanks for brining it out.
 I'll bring this point to our VHDL and Verilog synthesis groups.  

--------------------------------------------------------------------------
----------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Component Design by Example ... a Step-by-Step Process Using 
  VHDL with UART as Vehicle",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
--------------------------------------------------------------------------
------------------------------------------


Article: 33332
Subject: HotII interrupts...
From: "Ken Kent" <ken@csc.uvic.ca>
Date: Mon, 23 Jul 2001 11:04:25 -0700
Links: << >>  << T >>  << A >>
Hey,
    I have a hotii-xl board from VCC and am trying to get the user interrupt
working, ie hardware generate an interrupt using the "userint" signal and a
user defined function in software handle the generated interrupt.  So far I
have had no luck in getting this to work.  Does anyone else have any
experiences with this?  Any examples of working code, or realization of
underlying problem(s)?

Thanks,
Ken



Article: 33333
Subject: Re: Measuring power consumption
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 23 Jul 2001 11:08:07 -0700
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
> Ray Andraka schrieb:
> >
> > Measure the differential power on the board between a configured and
> > running FPGA and one that is either unconfigured or loaded with a
> > placeholder static design.
> 
> Hmmm, this may be a first attempt. But I am afraid this won't work at all
. . .

It works very well for comparing alternate designs instances.
It can also tell you quickly when something is very wrong.
Better to tie up an ammeter than burn your thumb.

 --Mike Treseler

Article: 33334
Subject: Re: Altera ISP - JTAG
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Mon, 23 Jul 2001 19:13:21 +0100
Links: << >>  << T >>  << A >>
>
> Does anyone know how to interface from the Altera software package
> programming output to jtag.
> Altera tries to sell its serial programming cable BitBlaster for around
> $500, which IMHO is a little  overpriced ;) (since we go from serial data
to
> ... yep serial data, right??)

It's got a microcontroller in it. The ByteBlaster is a lot cheaper if you
have a printer port available, and it's easy to make your own.

Leon



Article: 33335
Subject: Re: EDN
From: johne@vcd.hp.com (John Eaton)
Date: 23 Jul 2001 19:28:38 GMT
Links: << >>  << T >>  << A >>
Michael Boehnel (boehnel@iti.tu-graz.ac.at) wrote:
: I am looking for an online description of the EDN netlist format. Does
: anybody know such a site?
: Is there free source code for the analysis of EDN-Files available?

: Michael

Do you mean EDIF?



Article: 33336
Subject: Re: free VHDL and/or Verilog tools?
From: Jennifer Jenkins <jennifer.jenkins@xilinx.com>
Date: Mon, 23 Jul 2001 14:06:17 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------CB1D2D4A90962111D83802A7
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

The Xilinx WebPACK software tools can be found here:

 http://www.xilinx.com/products/software/webpowered.htm

Dave Vanden Bout wrote:

> Philipp Krause wrote:
>
> > Are there any free tools around? I'd like to learn VHDL, but don't want
> > to spend money on commercial software since I don't know which chip
> > family I'll use when it comes to implementing something.
> >
> > Philipp Krause
>
> Download the free WebPACK tools from Xilinx or the free Maxplus2 tools from
> Altera.  Both contain VHDL and Verilog synthesizers.
>
> --
> || Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
> || devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
> || http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||

--------------CB1D2D4A90962111D83802A7
Content-Type: text/x-vcard; charset=us-ascii;
 name="jennifer.jenkins.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Jennifer Jenkins
Content-Disposition: attachment;
 filename="jennifer.jenkins.vcf"

begin:vcard 
n:Jenkins;Jennifer
tel;fax:(505) 858-3106
tel;work:(505) 798-4813
x-mozilla-html:FALSE
url:http://www.xilinx.com
org:Xilinx CoolRunner CPLDs;<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx">
adr:;;7801 Jefferson St. NE;Albuquerque;New Mexico;87109;
version:2.1
email;internet:Jennifer.Jenkins@xilinx.com
title:Applications Engineer
fn:Jennifer Jenkins
end:vcard

--------------CB1D2D4A90962111D83802A7--


Article: 33337
Subject: Re: Flex 10K10 prototyping system
From: Gary Morton <gary@alma.demon.co.uk>
Date: Mon, 23 Jul 2001 20:23:12 GMT
Links: << >>  << T >>  << A >>
Leon Heller wrote:
> 
> I've just built up a prototype of a simple prototyping system for the
> Altera Flex 10K10. If there is any interest, I'll get some more boards
> made. I'll be placing the design in the public domain, and making the
> Gerbers available for anyone who wants to get their own PCB made.
> 
> I've put a picture on my web site:
> 
>       http://www.geocities.com/leon_heller/flex.gif
> 
> Leon Heller

Leon,

   this sounds interesting, but the page is not found. There doesn't
appear to be a link from your home page either.

regards...

--Gary

Article: 33338
Subject: Re: Flex 10K10 prototyping system
From: Leon_Heller@hotmail.com (Leon Heller)
Date: 23 Jul 2001 13:56:45 -0700
Links: << >>  << T >>  << A >>
Ben Franchuk <bfranchuk@jetnet.ab.ca> wrote in message news:<3B5BC9A0.43FA581C@jetnet.ab.ca>...
> Leon Heller wrote:
> > 
> > I've just built up a prototype of a simple prototyping system for the
> > Altera Flex 10K10. If there is any interest, I'll get some more boards
> > made. I'll be placing the design in the public domain, and making the
> > Gerbers available for anyone who wants to get their own PCB made.
> > 
> > The PCB is four-layers, 80mm X 100mm (half Eurocard). Unregulated DC
> > (8-12V) needs to be provided from a suitable PS, like a wall-wart.
> > There is an 'idiot' diode to prevent damage if the supply is round the
> > wrong way. A socket is provided for a 14-pin crystal oscillator
> > module. The Flex chip is configured via a standard Byteblaster header,
> > there is no provision for a configuration device. Most of the Flex I/O
> > and +5V is available via a 64-way DIN41612 plug, to which a suitable
> > Eurocard prototyping board may be attached.
> > 
> > I've put a picture on my web site:
> > 
> >       http://www.geocities.com/leon_heller/flex.gif
> > 
> > Leon Heller
> Burch use to make a nice 10k10 FPGA board but they moved to bigger chips.
> Having the this board has me thinking about the few problems I have using this
> board - I can't interface it to to a large solderless breadboard. Rather than
> making another full sized PC board is make a FPGA adapter PCB's to fit a
> solderless breadboards. Ben.  
> PS. Your URL gives me a not found error.


Sorry, I should have uploaded it as a JPEG. Try

    http://www.geocities.com/leon_heller/flex.jpg

You could plug my board into a Eurocard board with the solderless
breadboard mounted on it. The chips are a bit big to put onto some
sort of DIL PCB, which could be plugged into a solderless breadboard
and there might be problems with decoupling


Leon

Article: 33339
Subject: Re: Soldering Ceramic BGA's
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Mon, 23 Jul 2001 22:03:00 +0100
Links: << >>  << T >>  << A >>
Good Luck is all I can say - these can be a real pain in the... But find a board
builder with experance to place your part (recommendation - so you can kick them
when it don't work) However I found the folloing help full. Keep the part
towards the center of the board, Don't flood fill too think or unless you realy
need to (this will all pull heat away). Now this I cant remember - somthing to
do with the pad, you get copper or pre solderd ones if I remember. I think the
copper ones were better? Get your stuff X-rayed and JTAGed afterwords - At this
point its realy worth rembering that complex designs can be a lot easyer to
fault find with lots of boudary scan devices on your board. We found corner pins
the biggest problem, would not flow or cracked during the cool down.

I the end we payed someone that knowns what they are doing - cost a lot less
that our own labour and time.

Cyber_Spook_Man



Anthony Ellis wrote:

> This is not an FPGA question but I guess many of you may have designed
> FPGA's using similar technology and work for companies that have some advice
> to part with.
>
> We have a PCB designed for a 255 pin Ceramic BGA and are struggling to
> solder this correctly.  Plastic BGA's are not an issue however.
> Obviously the ceramic absorbs the reflow energy but we haven't been able to
> find the correct technique to pre-heat the part. I guess we could measure
> the pre-heated component temperature if we had some idea about it's required
> value.
>
> Any help please.
>
> Thanks Anthony


Article: 33340
(removed)


Article: 33341
Subject: Re: free VHDL and/or Verilog tools?
From: nk <kitamura@facstaff.wisc.edu>
Date: Mon, 23 Jul 2001 16:39:16 -0700
Links: << >>  << T >>  << A >>
what are the limitations on the free webpack software?  which vhdl syntax are supported or not supported?  where can i find technical specifications? thanks.

Article: 33342
Subject: Re: Homemade Xilinx parallel cable problem
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 24 Jul 2001 00:54:10 +0100
Links: << >>  << T >>  << A >>


Daniel Hańczewski wrote:

> Hi,
>
> I have also made this cable and the only problem I met was cable length.
> Xilinx advices wire connection between JTAG header and Parallel III
> electronics to be "as short as possible" and between electronics and LPT
> port no longer than 2m. I have placed electronics inside standard DSUB25
> connector and according to Xilinx's schematic JTAG-electronics cable length
> musn't exceed 0,5m. Finally I got rid of all 100pF capacitors connected to
> JTAG signal lines and now my cable has 2m and works without reservation. I
> haven't tried to make it longer...
>
> Regards
> Daniel
>

No real criticism Daniel but I've heard this sort of thing a lot but I reckon
the length thing is basically voodoo. I've run 3x 3 meter Centronics extension
cables + the Parallel-3 & configured CPLDs with not problem (back in the early
days of the JTAG programmer when it didn't run on Win95 I had to do this to
reach the NT box on the far side of the office).

Now our boards have the Xilinx P-III h/w on them & it only takes 2 extension
cables.


Article: 33343
Subject: Re: Xilinx Software free
From: nk <kitamura@facstaff.wisc.edu>
Date: Mon, 23 Jul 2001 17:27:28 -0700
Links: << >>  << T >>  << A >>
I am wondering what exactly is meant by "full vhdl and verilog support", because i keep getting "...not supported" kind of error messages with the webpack software.

Article: 33344
Subject: Re: Silo-3 Demo Program Crashes onDell 4100
From: "Clark Pope" <cepope@mindspring.com>
Date: Mon, 23 Jul 2001 21:06:03 -0400
Links: << >>  << T >>  << A >>
I had this problem with the demo version that came with the book. The
problem was the design I was compiling was too big for the demo version.

"Dave Feustel" <dfeustel@mindspring.com> wrote in message
news:9jceos$guu$1@nntp9.atl.mindspring.net...
> I have the Silo-3 Demo from "Verilog HDL_ by Samir Palnitkar
> installed on two machines running Windows 2000 Pro.
> One is a Dell Dimension XPS Pro200n, the other is a Dell 4100.
> Silo runs on the XPS, but crashes with a memory access violation
> as soon as I attempt to run a simulation on the 4100. This behavior
> occurs with exam1a.s. (While Silo does run on the XPS, it crashed
> while I was adjusting a window size. How stable is the demo version
> of Silo?)
>
> Does anyone have any idea what might be causing this?
>
> Thanks,
>
> Dave Feustel
>
>



Article: 33345
Subject: Re: Silo-3 Demo Program Crashes onDell 4100
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Tue, 24 Jul 2001 10:52:41 +0530
Links: << >>  << T >>  << A >>
Hi Dave,


"Dave Feustel" <dfeustel@mindspring.com> wrote in message
news:9jhc90$g0p$1@nntp9.atl.mindspring.net...
>
> I downloaded the Silos demo program but it reports fatal errors when I try
> to run any of the sample projects. I'd be willing to try the evaluation
version
>

        What kind of error does it report? I had a similar situation
sometime ago and it said:

" Said that I must select a device.
 I was using Silos III demo version."

If this is the error that you have encountered I can sugegst a workaround,
do let me know.

Srini




Article: 33346
Subject: Re: Flex 10K10 prototyping system
From: Leon_Heller@hotmail.com (Leon Heller)
Date: 23 Jul 2001 23:02:38 -0700
Links: << >>  << T >>  << A >>
> 
> 
> Sorry, I should have uploaded it as a JPEG. Try
> 
>     http://www.geocities.com/leon_heller/flex.jpg

For some reason, clicking on the above doesn't work. If you type the
address in it does work!!!

Leon

Article: 33347
Subject: Again some question on a QPSK modulator
From: dottavio@ised.it (Antonio)
Date: 23 Jul 2001 23:43:43 -0700
Links: << >>  << T >>  << A >>
Good Morning,
Always a question on my QPSK classical modulator schema containing two
branches each one with a polyphase SRRC filter having it's output
going to a multiplier together with sine or cosine produced by a DDS
working at 165MHz to produce 40MHz , I've these two questions about :

1)I've arranged the interpolator rate so to always have at the
multiplier the same rate of the DDS, 165MHz , so if for example I've
at the modulator input a data rate of 55Mbps corresponding to a symbol
rate of 27.5MSpS , I interpolate 6 to have the same rate , is this
correct ??? There are other methods to do the same ???

2) What do you think about my choise to use 165MHz instead of 160MHz
to produce 40MHz , there is any consideration to do in terms of SFDR
???

Thank you all again for your help ...


Antonio D'Ottavio

Article: 33348
Subject: Re: Synchronous output enable not supported?
From: "Zimba" <zimba@zamba.com>
Date: Tue, 24 Jul 2001 08:48:08 +0200
Links: << >>  << T >>  << A >>
> Sounds like the synthesis tool isn't being as intelligent as it could be.
I
> agree with your suggestion to try a different coding style, though.

That's what I thought, because it synthesized fine with FPGA Express but the
problem came up with XST VHDL.

Thanks for the replies,
Clemens



Article: 33349
Subject: Re: any vb sample code for access database function
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 24 Jul 2001 07:54:36 +0100
Links: << >>  << T >>  << A >>


ts1@its.com.sg wrote:

> I am new in vb design, anybody can email some sample code or show me some site to download, I just want to design a vb program to load an MS access database(phonebook directory), I can search by name , by postcode, by tel no, to select some company.
>
> thanks
> ts

Wrong news group. You probably need to look around in comp.lang.XXX.




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