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Messages from 33425

Article: 33425
Subject: Re: Silo-3 Demo Program Crashes onDell 4100
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Thu, 26 Jul 2001 12:30:50 +0530
Links: << >>  << T >>  << A >>
Hi,

"Tim" <tim@rockylogic.com.nospam.com> wrote in message
news:996070958.5973.0.nnrp-14.9e9832fa@news.demon.co.uk...
> "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in> wrote in
message
> news:9jln51$n11@news.or.intel.com...
>
> > Software & Silicon Systems India Pvt. Ltd. (An Intel company)
>
> How long have you been an Intel company?
>

  I myself just moved in last week (from another startup Realchip, Chennai).
During initial "warm up" programs I got to know that it was acquired by
Intel during Feb 2000.

Srini
>



Article: 33426
Subject: Re: Application obstacle course
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 26 Jul 2001 08:04:10 +0100
Links: << >>  << T >>  << A >>


Dave Feustel wrote:

> I have installed a licensed version of the 60 day eval version of Xilinx
> ISE Foundation  and the 30 day Modelsim package but I am plagued
> with license-related problems that prevent the software from working.
> I don't see this situation getting any better in the future.
> I am now seriously considering  uninstalling this software and going to Webpack
> (at least it's free with no time constraints).
>

I've not tried the ModelSim starter so I can't comment on that, although I've been using the PE edition for
a long time now with no problems. For the 3.3 eval I looked at the warning on the cover & took it seriously
by

o Copying my 2.1i & WebPACK installations somewhere else.

o Uninstalling them.

3.3i eval installed & worked fine BUT I don't use the GUI & run everything from the command line.
All the scripts start with a line like this [bash shell from Cygwin]

declare -x XILINX=D:/<WebPACK | Fndtn2.1iSP6 | Fndtn3.3iSP8>

depending on which toolset I'm using - WebPACK for CPLDs, 2.1i for mainline work, 3.3i for experimentation
with Virtex-2.

>
> If I had a way to generate Spartan 2 and Virtex 2 FPGA configuration
> bit files from the output of gEDA tools and then download the configuration
> files to the hardware, I would switch to them immediately
> on the grounds that, whatever shorterm problems I might have with them,
> the longterm lack of licensing problems would more than compensate.
>

A gEDA P&R tool would be a wonderful thing but I'm not sure there's enough info to write one. The route in -
for Xilinx FPGAs - would be to use the XDL text based circuit description language but its very poorly
documented. You might want to think about it in this way: How many GPL'ed PCB autorouters are there ?





Article: 33427
Subject: Free VHDL cores - where?
From: Daniel =?iso-8859-1?Q?Ha=F1czewski?= <danhan@wp.pl>
Date: Thu, 26 Jul 2001 10:27:45 +0200
Links: << >>  << T >>  << A >>
Hi,

Can anyone suggest website(s) with free core VHDL files? Just to learn
VHDL...
Are there any educational resources for people starting with VHDL? I
found some but I wonder if there are other sites...

Regards
Daniel


Article: 33428
Subject: Re: FPGA Express or Spectrum?
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 26 Jul 2001 09:31:36 +0100
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
> 
> I tried both and like Leonardo.
> Easier to handle and the results are better than Synopsys (less LCs, higher
> clock).
> You need a network card for Leonardo.


Martin,

Was that higher clock speeds when Quartus has placed and routed a design
or higher speeds as reported by the synthesis tools?

Nial.

Article: 33429
Subject: Re: Prom: Download problem
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Thu, 26 Jul 2001 10:34:34 +0200
Links: << >>  << T >>  << A >>
Harry Chung a écrit :
> 
> Hi,
>     I would like to download the *.mcs file to a prom
> (XC18V04) with Parallel Cable III.
> Questions:
> 1) What is the circuit for connecting the prom with cable
> correctly?
> 2) Can the JTAG programmer download the *.mcs file?
> Thank you very much,

The hardware you need is only The parallel III cable. Have a look at the
18Vxx datasheet: there are the 4 JTAG signals on the chip, you can't
miss them.
The JTAG Programmer seems to handle .mcs files so I think there's really
no problem here.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 33430
Subject: Re: Prom: Download problem
From: Falk <>
Date: Thu, 26 Jul 2001 01:52:39 -0700
Links: << >>  << T >>  << A >>
1) Use the JTAG port. Simply 4 wires.

2) yes. 

Regards
Falk

Article: 33431
Subject: Architecture Evaluation Tools
From: Michael Hosemann <hosemann@ifn.et.tu-dresden.de>
Date: Thu, 26 Jul 2001 11:02:50 +0200
Links: << >>  << T >>  << A >>
hello,

I am looking for a tool which i can use for modelling architectural ideas 
for a DSP and simulate those to get cycle counts for certain applications. 
Ideally I'd like to use it for generation of tools (assembler, debugger, 
simulator) too.

So far I found CGen and HASE on the web. Unfortunatelt CGen's documentation 
is not exactly beginner-friendly and i am not sure if it is in a usable 
stage yet. HASE was not available for download, dunno if I will get to use 
it.

Any hints, comments etc.

regards

Michael

-- 
Dipl.-Ing. Michael Hosemann
Research Associate
Mannesmann Mobilfunk Chair for Mobile Communication Systems
Dresden University of Technology
01061 Dresden

Tel: +49 351 463 5674
Fax: +49 351 463 7255 

Article: 33432
Subject: PQFP sockets
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 26 Jul 2001 10:17:01 +0100
Links: << >>  << T >>  << A >>
I know this is a bit off topic but there's a lot of general h/w
expertise in this NG so here goes:

What's the general view of PQFP sockets that mount on the same SMT
footprint as the component itself ?

o As test sockets ?

o For production ?

My experience of these this things is that they are as flakey as a bad
case of dandruff but maybe there are better ones than those I've had to
deal with. If so which ones are best ?


Article: 33433
Subject: Re: FPGA Express or Spectrum?
From: Andreas Bombe <bombe@sunhalle78.informatik.tu-muenchen.de>
Date: 26 Jul 2001 09:41:19 GMT
Links: << >>  << T >>  << A >>
In comp.lang.vhdl "Andy Peters <andy [@] exponentmedia" <".> com"> wrote:
> Russell Shaw wrote:
>> I couldn't try Leonardo Spectrum until i get an old network
>> card with NIC. Will it work without a network connected? (using
>> win2k)
> 
> All it uses the network card for is its MAC address, which is a unique
> identifier that the licensing tool uses to guarantee that your copy of
> the program doesn't run on other computers.  Unless you remove the NIC
> and put it in a different computer.  Which is possibly one Real Good
> Reason to buy a CardBus (PC Card) adapter for your PC and stick a
> CardBus NIC in it, and tell the licensing people the MAC address of the
> CardBus NIC.

Current Linux drivers can actualle change the MACs on many types of
network cards while they don't have a network running.  However I don't
expect Windows drivers to have this feature since the MAC is often used
for licensing.

> And, on another note, remember all of the hoopla that arose when Intel
> announced that they had put a serial number in each Pentium II (or III,
> I don't remember)?  At the time, I thought the hoopla was silly, since
> every NIC has a unique serial number, too, and software vendors use it
> for EXACTLY the same reasons people bitched at Intel for.  Note that I
> in no way, shape or form defending Intel here (I have Athlon boxes and Macintoshes).

Actually it's very different.  There are a number of unique serial
numbers in a PC (apart from NICs every hard disk should have its own
ID).  These can not be accessed by user software however, they depend on
the operating system to read it.

At that point, you can block them (simply don't hand out the number when
the programs ask for it) or give them any desired number instead of the
real thing.

The Pentium serial number however was directly accessible to user
programs.  Reading it is an unprivileged operation, and AFAIK can not be
set to trap into the OS.  This means the only way to control access is
to scan each opcode before executing (i.e. having a VMWare like virtual
environment with its associated slowdown and memory requirements as your
native environment).  This sucks badly.

-- 
Andreas Bombe <bombe@informatik.tu-muenchen.de>

Article: 33434
Subject: Re: Free VHDL cores - where?
From: Edwin Naroska <edwin@ds.e-technik.uni-dortmund.de>
Date: Thu, 26 Jul 2001 12:05:52 +0200
Links: << >>  << T >>  << A >>
Hi,

Daniel Hañczewski wrote:

> Hi,
>
> Can anyone suggest website(s) with free core VHDL files? Just to learn
> VHDL...
> Are there any educational resources for people starting with VHDL? I
> found some but I wonder if there are other sites...
>

You may check out the VHDL FAQ at

    http://www.vhdl.org/comp.lang.vhdl/ or
    (http://www.eda.org/comp.lang.vhdl/) .

Part 1 lists some free VHDL model sites:

    http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#3.2
    http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#4.9

--
Edwin




Article: 33435
Subject: Re: Windows ME and Foundation ISE?
From: "Rémi SEGLIE" <remi.seglie@optrantechno.com>
Date: Thu, 26 Jul 2001 12:56:22 +0200
Links: << >>  << T >>  << A >>
Xilinx software doesn't work under Windows Me : try Windows 98 or better,
Windows NT 2000, the most appropriate OS, from microsoft, for such work...

"Paul Teagle" <pteagle@bigpond.net.au> a écrit dans le message news:
S0C77.62047$Xr6.245659@news-server.bigpond.net.au...
> Hi
>
> I am attempting to install an evaluation version of ISE 3.3 on a Windows
ME
> machine (750MHz pentium III laptop, 128M RAM) . Is this possible/has
anyone
> else tried this?? It does actually install, and the Project Navigator
comes
> up - and then dies after about 1 second...There is no other Xilinx s/w on
> the machine.
>
> I'd put this to the support people, but I've only just registered &
haven't
> got access to the web case tools yet.
>
> regards,
>
> Paul Teagle
> CAE Inc
>
>
>
>



Article: 33436
Subject: Re: Windows ME and Foundation ISE?
From: "Paul Teagle" <pteagle@bigpond.net.au>
Date: Thu, 26 Jul 2001 12:04:08 GMT
Links: << >>  << T >>  << A >>
Well, that is not quite the case...

After much mucking around, and trying to bridge the gaps between what is in
the documentation, the Xilinx solutions guide (answer no. 9253 is most
appropriate) and how Windows ME actually works, I managed to update my
autoexec.bat (now updated via the registry, so you can't edit it directly)
to include the necessary lines. Voilá! It is now working (qualification - I
can view files & muck around with schematics etc. Haven't sunk my teeth into
any real designs or simulations yet).

So am I the only one on the planet using Xilinx under Windows ME? *sigh*

I must say that I'm a bit disappointed in the installation guides so far -
it does seem to make many references to directories etc that don't exist on
the CD ROM, and the info on ME is rather scant. I've had to read between the
lines and make some WAGs in several places as to what is actually meant by
the instructions.

However, this evaluation copy is free - for 60 days, at least. Crossing
fingers...

regards,

Paul T.


"Rémi SEGLIE" <remi.seglie@optrantechno.com> wrote in message
news:9joski$83k$1@news4.isdnet.net...
> Xilinx software doesn't work under Windows Me : try Windows 98 or better,
> Windows NT 2000, the most appropriate OS, from microsoft, for such work...
>
> "Paul Teagle" <pteagle@bigpond.net.au> a écrit dans le message news:
> S0C77.62047$Xr6.245659@news-server.bigpond.net.au...
> > Hi
> >
> > I am attempting to install an evaluation version of ISE 3.3 on a Windows
> ME
> > machine (750MHz pentium III laptop, 128M RAM) . Is this possible/has
> anyone
> > else tried this?? It does actually install, and the Project Navigator
> comes
> > up - and then dies after about 1 second...There is no other Xilinx s/w
on
> > the machine.
> >
> > I'd put this to the support people, but I've only just registered &
> haven't
> > got access to the web case tools yet.
> >
> > regards,
> >
> > Paul Teagle
> > CAE Inc
> >
> >
> >
> >
>
>



Article: 33437
Subject: Re: PQFP sockets
From: Greg Neff <gregeneff@yahoo.com>
Date: Thu, 26 Jul 2001 10:03:10 -0400
Links: << >>  << T >>  << A >>
On Thu, 26 Jul 2001 10:17:01 +0100, Rick Filipkiewicz
<rick@algor.co.uk> wrote:

>I know this is a bit off topic but there's a lot of general h/w
>expertise in this NG so here goes:
>
>What's the general view of PQFP sockets that mount on the same SMT
>footprint as the component itself ?
>
>o As test sockets ?
>
>o For production ?
>
>My experience of these this things is that they are as flakey as a bad
>case of dandruff but maybe there are better ones than those I've had to
>deal with. If so which ones are best ?


I don't know about surface mount PQFP sockets.  The only PQFP test
sockets that we have used are Yamaichi through-hole clam shells:

http://www.yeu.com/index_tb.html

These have worked fairly well for us.  The only place we have used
these is on engineering evaluation boards to qualify ASICs in place of
FPGAs.  I would not use these in production.  I don't even like
socketing QFPs for programming (we use in-circuit programming).  Why
would you want to socket a PQFP on a production board?


===================================
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com

Article: 33438
Subject: Re: Free VHDL cores - where?
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Thu, 26 Jul 2001 09:05:11 -0500
Links: << >>  << T >>  << A >>
See also http://www.opencores.org

"Edwin Naroska" <edwin@ds.e-technik.uni-dortmund.de> wrote in message news:3B5FEB80.6873C01F@ds.e-technik.uni-dortmund.de...
> Hi,
>
> Daniel Hañczewski wrote:
>
> > Hi,
> >
> > Can anyone suggest website(s) with free core VHDL files? Just to learn
> > VHDL...
> > Are there any educational resources for people starting with VHDL? I
> > found some but I wonder if there are other sites...
> >
>
> You may check out the VHDL FAQ at
>
>     http://www.vhdl.org/comp.lang.vhdl/ or
>     (http://www.eda.org/comp.lang.vhdl/) .
>
> Part 1 lists some free VHDL model sites:
>
>     http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#3.2
>     http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#4.9
>
> --
> Edwin
>
>
>



Article: 33439
Subject: Re: Application obstacle course
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Thu, 26 Jul 2001 09:13:35 -0500
Links: << >>  << T >>  << A >>

"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B5FBD21.C2575779@algor.co.uk...
>
>
> David Wright wrote:
>
> > (2) ModelSim XE Starter is free if you limit your code to 500 lines or less.
>
> Don't bother with it. My advice is to just bite the bullet & get the full-fat PE
> NT version, its only ~$4.5K. Put it on a fast DDR Athlon box and you really
> won't regret it.

Is this a one-time or annual expense?



Article: 33440
Subject: He is back from vacation, and he has a tan, too!
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 26 Jul 2001 07:46:29 -0700
Links: << >>  << T >>  << A >>
Gosh,

Peter is an inspiration to us all, and I am so glad I decided to join Xilinx three
years ago.

Now I just wish there was a DLL, DCM, DCI, or power issue on this board so I could
play, too.

Austin


Article: 33441
Subject: PCI-Interface
From: Wilfried Philippi <wph@gmx.net>
Date: Thu, 26 Jul 2001 16:50:18 +0200
Links: << >>  << T >>  << A >>
hello,
i want to develop a PCI Interface that read from i/o Adress 80hex as i/o
read and then stores
the data for displaying with 2 7seg display's. The function of this is
do show the postcode while
system is booting. because the interface must work wen power ist
switching on, a fpcga with
sram can not work. has anyone Ideas or can tell me what chip is the best
reason
many Thanks.
best regards
wilfried


Article: 33442
Subject: Scope of libraries in leonardo spectrum
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Fri, 27 Jul 2001 00:51:56 +1000
Links: << >>  << T >>  << A >>
Hi all,

If i leave out the second "LIBRARY ieee" and "USE" statement, i get
an error about undeclared types in the second entity (wave). It seems
that the scope of the first library statement ends at the first
entity. Is this normal, or a leonardo quirk?


LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY traffic IS port(
  de : IN std_ulogic;
  ab : OUT std_ulogic);
END;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY wave IS port(
d:     IN std_ulogic;
clk:   IN BIT;
clear: IN BIT;
outa:  OUT BIT);
END wave;

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 33443
Subject: Re: prospects for tiny FPGA supercomputer?
From: "Jon Harrison" <jon.harrison@gecm.com>
Date: Thu, 26 Jul 2001 16:03:57 +0100
Links: << >>  << T >>  << A >>

"Thomas Stanka" <Thomas.Stanka@de.bosch.com> wrote in message
news:3B5FBF32.737193D3@de.bosch.com...
> HI,
>
> Jason Stratos Papadopoulos wrote:
>
> > and the chip had eight 16-bit integer multipliers. The PhD students on
> > this project got HP to implement it in about 750,000 gates (1995
> > technology)
>
> I think, thats today possible in a highend-Virtex-FPGA
>
> > Am I completely nuts here? Are there low-cost tools that can do a
> > synthesis and/or place and route for what even to me sounds like a
pretty
> > ambitious design?
>
> There are low cost or freeware tools, that fit. But I know from
> experience, that for designs that size you use better commercial tools
> to receive best results.
> What will mean, that you develop using lowcost tools until you reach
> acceptable results and then search for someone, doing the final work.
>
> > What about tutorials on Verilog/VHDL?
>
> Its easier to learn Verilog or VHDL than to learn designing hardware
> using this languages.
> So you should start with small designs to learn how to build hardware
> using Verilog/VHDL
>
> > Finally, are there
> > IP cores for little processors like an ARM7 or older MIPS that would fit
> > into a big FPGA?
>
> I can't believe, that there will be ever an suiable ARM-core available,
> but there free cpus online. Eg Leon http://www.leoncenter.com which will
> fit even in a Virtex-800 FPGA with a pack of surounding logic.
>
> bye Thomas
>

There is an ARM7 clone under development at http://www.opencores.org
together with some others which are at the concept stage.

Jon




Article: 33444
Subject: FPGA Advantage
From: Hong <lvhong@aol.com>
Date: Thu, 26 Jul 2001 08:38:43 -0700
Links: << >>  << T >>  << A >>
Hi,
It works fine without the networking card, you will need the Disk Serial Number, of course!
Here is an example, just simply follow the installed instruction, there is an optional for it (HD S/N)! You could get free trial license in 30-day then determine the needs. It's pretty cool!
More info:
http://www.mentor.com/fpga-advantage/

Example:
Product ID : FA4.0 (FA5.0)
Eval Host ID : xxxxxxxxxxxxxxxxxxxxx
Ethernet Address : -X
Hostname : yourhost
Disk Serial Number : xxxxxxxx
Internet Address : xxx.0.0.x

You wrote:
>>>I couldn't try Leonardo Spectrum until i get an old network
card with NIC. Will it work without a network connected? (using
win2k)<<<

Hope this helps,

Hong

Article: 33445
Subject: Re: prospects for tiny FPGA supercomputer?
From: John_H <johnhandwork@mail.com>
Date: Thu, 26 Jul 2001 15:44:40 GMT
Links: << >>  << T >>  << A >>
Jason Stratos Papadopoulos wrote:

> I was wondering if it would be possible to pack a 64-bit version of this
> kind of vector processor into latter-day programmable logic; specifically
> something with a group of 64-bit ALUs that could do adds, subtracts and
> 64 x 64 bit pipelined integer multiplies as fast as possible. A beast like
> this would be very useful for the very large integer convolutions I
> continually find myself doing, and for which conventional general-purpose
> processors are way too slow for my taste.

Rather than going for the generic processor approach with a boatload of ALU
capability, perhaps an "integer convolution coprocessor" would be a more
manageable design task?  FPGA designs excel at attacking very specific
problems without the overhead of a generic approach.  For instance there are
FFT cores that allow very high speed transforms compared to the processor
counterparts.  Lots of computational horsepower and cost effective at the same
time.  Your specific tasks might be implemented with blinding speed if you put
the hardware toward only the task you need.


Article: 33446
Subject: Re: Scope of libraries in leonardo spectrum
From: "Tom Verbeure" <tverbeure@globespan.net>
Date: Thu, 26 Jul 2001 12:03:54 -0400
Links: << >>  << T >>  << A >>


> If i leave out the second "LIBRARY ieee" and "USE" statement, i get
> an error about undeclared types in the second entity (wave). It seems
> that the scope of the first library statement ends at the first
> entity. Is this normal, or a leonardo quirk?

This is normal. Library declarations are only valid for that particular
module/package/configuration.

Tom


>
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
>
> ENTITY traffic IS port(
>   de : IN std_ulogic;
>   ab : OUT std_ulogic);
> END;
>
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
>
> ENTITY wave IS port(
> d:     IN std_ulogic;
> clk:   IN BIT;
> clear: IN BIT;
> outa:  OUT BIT);
> END wave;
>



Article: 33447
Subject: Re: XC4010 ! help please
From: Werner Dreher <dreher@informatik.uni-tuebingen.de>
Date: Thu, 26 Jul 2001 18:14:03 +0200
Links: << >>  << T >>  << A >>
Joe,

on which platform do you use the XACT software?
We have a legal license for XACT (and the software itself) for
Sun/SunOS, but the software doesn't run because of an y2k bug
in the license deamon :-(

 Werner Dreher

Joe wrote:
> 
> Unfortunately, you will have to get a copy of Xilinx's legacy tool called XACT. We use both the Alliance and XACT toolset to support Xilinx legacy and new devices...
> 
> Tran Cong So wrote:
> 
> > Hi,
> > I have now to design on a very old FPGA XC4010 (not E or XL).
> > The problem is the current development softwware that I am using is Fondation ISE 3.1 and this version does not support for xc4000 family and the old software XACT Step 5.2/Sun is out of license. I tried to contact distributor to get new license but just have got the NOT SUPPORT because the software (XACTStep) is too old.
> > Does any one have an idea how to be able to work with XC4000 family at this time ? The device is not replacable because replacement means to destroy the PCB.
> > Thank you very much.
> > Tran Cong So.

Article: 33448
Subject: Re: Free VHDL cores - where?
From: sknapp@triscend.com (Steven K. Knapp)
Date: 26 Jul 2001 10:04:22 -0700
Links: << >>  << T >>  << A >>
There is plenty of VHDL and Verilog source at
http://www.opencores.org/projects.shtml

One site that might have a few useful VHDL links is
http://www.optimagic.com/tutorials.html.


Daniel Hañczewski <danhan@wp.pl> wrote in message news:<3B5FD481.C03DE3E0@wp.pl>...
> Hi,
> 
> Can anyone suggest website(s) with free core VHDL files? Just to learn
> VHDL...
> Are there any educational resources for people starting with VHDL? I
> found some but I wonder if there are other sites...
> 
> Regards
> Daniel

Article: 33449
Subject: Re: Bound Scan
From: sknapp@triscend.com (Steven K. Knapp)
Date: 26 Jul 2001 10:13:24 -0700
Links: << >>  << T >>  << A >>
Are you looking for information on what boundary scan testing is all
about?  If so, the following link from the T.I. web site is useful.

Testability Primer
http://www-s.ti.com/sc/psheets/ssya002c/ssya002c.pdf


"Igor Koulikov" <51147@sovintel.spb.ru> wrote in message news:<9jn443$233a$1@josh.sovintel.ru>...
> Hello, All!
> I look for news about boundary scan. If any, tell me.



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