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Paul Smart wrote: > Hi All, > > I was wondering if anyone can shed some light on this: > > The Xilinx and Altera tools seem to produce a behavioral verilog file > for simulation. Is there any way I can get a structural verilog file? > You need to go all the way through to place & route and then (1) Run NGDANNO on the routed database .ncd file => a timing backannotated .nga file. (2) Use the .nga + .ngm from the MAP stage as input to NGD2VER to get a post-route structural netlist based on the ``simprims'' library. Also outputs an SDF file. Details are in the ``Development System Reference Guide'' aka dev_ref..pdf aka the Xilinx P&R Bible part I. [Part II is the Libraries guide]. If you are not worried about timing info you can run NGD2VER on the .ngd output from NGDBUILD.Article: 33476
Rick Filipkiewicz wrote: > Paul Smart wrote: > > > Hi All, > > > > I was wondering if anyone can shed some light on this: > > > > The Xilinx and Altera tools seem to produce a behavioral verilog file > > for simulation. Is there any way I can get a structural verilog file? > > > > You need to go all the way through to place & route and then > > (1) Run NGDANNO on the routed database .ncd file => a timing > backannotated .nga file. > > (2) Use the .nga + .ngm from the MAP stage as input to NGD2VER to get a > post-route structural netlist based on the ``simprims'' library. Also > outputs an SDF file. > > Details are in the ``Development System Reference Guide'' aka > dev_ref..pdf aka the Xilinx P&R Bible part I. [Part II is the Libraries > guide]. > > If you are not worried about timing info you can run NGD2VER on the .ngd > output from NGDBUILD. I should of course have begun this as ... for Xilinx devices ...Article: 33477
Programmable parts have different test requirements to ASICs, so I guess the answer to your question is Yes. "Paul Smart" <pablo*@*maine.rr.com> wrote in message news:nf63mto80i93domopvj4lfanb4tm07c726@4ax.com... > Hi All, > > I was wondering if anyone can shed some light on this: > > The Xilinx and Altera tools seem to produce a behavioral verilog file > for simulation. Is there any way I can get a structural verilog file? > > There are some (ASIC) tools I want to use with these files that only > support structural verilog (the tools are for ATPG, DFT, and fault > simulation (ultimate goal is device testing)). Examples of this type > of tool are: > - IBM: TestBench (DFT, ATPG) > - Synopsys: DFT Compiler and TetraMax ATPG > > Is this something that Xilinx or Altera will provide someday? > > I know a lot of ASIC related tools cannot work with current FPGA > design methodologies, but do we really expect to work with multi > million gate FPGAs without access to DFT, ATPG, and fault simulation > tools as are used in the ASIC world? > > Thanks for your time, > PaulArticle: 33478
Hi, I believe they only transfer through an FTP site from there. If I am not mistaken Xilinx used to have HTTP download possibilities on a 'documentation' page on their site, which used to be accessible from the downloads page of the updates. I also tried to download individual files and then tried to recombine using the batch file, but have never been able to get it to work. I now download using an FTP program. Advantage is that the 'resume' option of the FTP site does work; with some 80Mb to download on a telephone- line.... You may want to try installing a FTP program (CuteFtp for example) and use that to download the one large file. Cheers, Jan Martin Wagenaar In article <3B5C2513.7030409@amontec.com>, laurent.gauch@amontec.com says... > I am on > http://support.xilinx.com/support/techsup/sw_updates/31i/sw_f33i_pc.htm > trying to download the Foundation 3.3i Software Updates for PC (3.3i > service pack 8), but I cannot download these single files. Why? > >Article: 33479
In article <996261418.29083.0.nnrp-13.9e9832fa@news.demon.co.uk>, Tim <tim@rockylogic.com.nospam.com> writes >Programmable parts have different test requirements to ASICs, so >I guess the answer to your question is Yes. If you cannot insert scan into an FPGA how do you get a high fault coverage? If you have a poor fault coverage you will be shipping defective parts which is not good for your business. -- Andy BotterillArticle: 33480
"Bertram Geiger" <bgeiger@aon.at> wrote in message news:3B5E797B.94BAF241@aon.at... > It would be nice to have a little test program, to be able to check the > cable with a continous puls train without the need of having the CPLD > connected. > > greetings, bertram I would think this would be quite easy given that its just the "PC" parallel port. DaveArticle: 33481
You can't use the F5/F6 mux in the same slice as 2 srl16's because the BX and BY lines which control the mux are shared with the write enables for the SRL16's. Depending on your application, you might change the programming of the SRL16 address lines on two serially cascaded SRL16s, which (without intervening FD's) gives you a delay between 2 and 32 clocks and no mux. You will need to translate the delay code into the 8 select bits for the SRL16s. If you are concerned for speed, you'll want to register the output of each SRL16 with the FF in the same half-slice. The clock to out time of the SRL16 is pretty lousy compared to that of the FF's. Huang wrote: > Hi, > > When using CoreGenerator for a SRL16 based shif register, say, a 32x1 shfit register, I found the result was 3 LUT, 2 for SRL16, 1 for mux. > > Does anyone know why CoreGen doesn't use MUXF5/6/7/8 for a more resource efficient result? > > Thanks -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33482
We have it on Sun OS4.1 -- XACT will not work on Solaris Werner Dreher wrote: > Joe, > > on which platform do you use the XACT software? > We have a legal license for XACT (and the software itself) for > Sun/SunOS, but the software doesn't run because of an y2k bug > in the license deamon :-( > > Werner Dreher > > Joe wrote: > > > > Unfortunately, you will have to get a copy of Xilinx's legacy tool called XACT. We use both the Alliance and XACT toolset to support Xilinx legacy and new devices... > > > > Tran Cong So wrote: > > > > > Hi, > > > I have now to design on a very old FPGA XC4010 (not E or XL). > > > The problem is the current development softwware that I am using is Fondation ISE 3.1 and this version does not support for xc4000 family and the old software XACT Step 5.2/Sun is out of license. I tried to contact distributor to get new license but just have got the NOT SUPPORT because the software (XACTStep) is too old. > > > Does any one have an idea how to be able to work with XC4000 family at this time ? The device is not replacable because replacement means to destroy the PCB. > > > Thank you very much. > > > Tran Cong So.Article: 33483
"Philip Freidin" <philip@fliptronics.com> wrote in message news:1oo0mt8l12baa247co6mujfcavm96bge7f@4ax.com... > This is why debug boards with the 2 digit display are ISA boards. ISA > is always active. Actually, I've seen some PCI boards as well. The IT guy at work here has a "flip over" one that's ISA on one edge and PCI on the other, so it works with any PC, new or old. These cards usually just have a CPLD on them, since they're simple compared to a full blown PCI core (even a target-only implementation). You may well be quite correct about such cards being useless if the PCI bus isn't up and running until well into the POST process... ---Joel KolstadArticle: 33484
I was shocked to discover that walmart.com offers "Verilog HDL" for $54.60 vs $68.95 at bookpool.com. I haven't bought from walmart.com, yet, but for 30% off such hitech and expensive books, I'll have to give it a try. "Vladimir Dergachev" <volodya@mindspring.com> wrote in message news:bmU47.119053$HJ1.3694202@e3500-atl1.usenetserver.com... > SAF wrote: > > > Thant's absolutely mad. I checked the prices on Amazon, BooksaMillion > > and BarnesandNoble, and they're all too high. If you want, try > > ordering them from Amazon.co.uk (www.amazon.co.uk), the price there is > > close to what I got them for. > > > > Never thought I'd see the day where something was cheaper here than in > > the US! :) > > > > You are lucky. When I wanted to get a book, the only one available (in > Barnes'n'Noble) was "Verilog HDL", Samir Palnitkar. I like it, but it was > the very last one and now none of the stores around here have any. > (I checked several). > > Vladimir Dergachev > PS I live in NC, USA > cheap! > >> Good for you! > > > > >Article: 33485
Dave Feustel wrote: > > The modelsim licensing program never asked me for the name > of the file containing the license. I think the problem is more > basic than that. And at this point I am pretty fed up with the > entire licensing fiasco that I have been experiencing. And if you ever set your real time clock ahead by accident, you practicaly have to format the drive and reinstall everything ( and get a new licence) if you want to run your computer at the correct time. The moment you set you clock back the software will refuse to run. Ben.Article: 33486
"Andy Botterill" <csm@plymouth2.demon.co.uk> wrote in message news:YNNvDUAmacY7EwX0@plymouth2.demon.co.uk... > >Programmable parts have different test requirements to ASICs, so > >I guess the answer to your question is Yes. > > If you cannot insert scan into an FPGA how do you get a high fault > coverage? If you have a poor fault coverage you will be shipping > defective parts which is not good for your business. The FPGA manufacturers do this for you. They use a combination of the reprogrammability of the part and, presumably, a few undisclosed test structures. The result is closer to 100% tested than just about any ASIC. All you have to worry about is logical and timing errors :)Article: 33487
In article <996308678.26850.0.nnrp-07.9e9832fa@news.demon.co.uk>, Tim <tim@rockylogic.com.nospam.com> writes > >"Andy Botterill" <csm@plymouth2.demon.co.uk> wrote in message >news:YNNvDUAmacY7EwX0@plymouth2.demon.co.uk... > >> >Programmable parts have different test requirements to ASICs, so >> >I guess the answer to your question is Yes. >> >> If you cannot insert scan into an FPGA how do you get a high fault >> coverage? If you have a poor fault coverage you will be shipping >> defective parts which is not good for your business. > >The FPGA manufacturers do this for you. They use a combination of the >reprogrammability of the part and, presumably, a few undisclosed test >structures. Hmmm I wonder what the test structures are. > >The result is closer to 100% tested than just about any ASIC. All >you have to worry about is logical and timing errors :) > OK -- Andy BotterillArticle: 33489
what is wrong if the clk out is bigger ??? Ray Andraka <ray@andraka.com> wrote in message news:<3B61C975.E74BEFE3@andraka.com>... > You can't use the F5/F6 mux in the same slice as 2 srl16's because the BX and BY lines which control the mux are shared with the write enables > for the SRL16's. Depending on your application, you might change the programming of the SRL16 address lines on two serially cascaded SRL16s, > which (without intervening FD's) gives you a delay between 2 and 32 clocks and no mux. You will need to translate the delay code into the 8 > select bits for the SRL16s. If you are concerned for speed, you'll want to register the output of each SRL16 with the FF in the same > half-slice. The clock to out time of the SRL16 is pretty lousy compared to that of the FF's. > > Huang wrote: > > > Hi, > > > > When using CoreGenerator for a SRL16 based shif register, say, a 32x1 shfit register, I found the result was 3 LUT, 2 for SRL16, 1 for mux. > > > > Does anyone know why CoreGen doesn't use MUXF5/6/7/8 for a more resource efficient result? > > > > ThanksArticle: 33490
The ContinuingSaga of Installing Modelsim software on my computer My attempts to install Xilinx Foundation ISE software came to naught since the installer, insisting that I had other unspecified Xilinx software on my computer, refused to install. After uninstalling the Xilinx Foundation Evaluation Software I discovered I had made it impossible to reinstall that software. I then got cable modem, downloaded 175 Megabytes of Xilinx Webpack software and installed it. My first attempt to run Modelsim resulted in a statement that I needed a license for that software. I immediately made the license request and instantly thereafter received my license file which I moved to a known location on my hard drive. Then I ran the Modelsim licensing program and got the following reply as the very first output from the Modelsim licensing program: "Your evaluation license has been invalidated because a text file necessary for licensing cannot be written. "In order to continue with the evaluation of Modelsim you will need to correct the error, re-install the evaluation copy and re-request an evalution license from Model Technology." Note 1) that the file that could not be written by the Modelsim installer is not identified. 2) that the cause of the inability of the licensing program to write the file is not identified. 3) that invalidating the entire install effort because of this error is strictly punitive 4) that the error will occur again the next time I run the licensing program since I have no clue as to what went wrong. 5) Because of 4) I won't bother trying to install Modelsim again. So it appears that both the Xilinx Foundation ISE install program and now the Modelsim licensing program like to let their customers guess what's wrong when the software won't install rather than just explicitly identify the cause of the failure. Welcome to the Brave New World of Software Licensing Any other alternatives to Modelsim?Article: 33491
"Dave Feustel" <dfeustel@mindspring.com> wrote in message news:9juddd$357$1@slb6.atl.mindspring.net... > The ContinuingSaga of Installing Modelsim software on my computer > > Welcome to the Brave New World of Software Licensing > > Any other alternatives to Modelsim? > Aldec is better, IMHO. But probably has similar licensing problems since FlexLM has almost 100% of the licensing software market. For your main problem, try checking that the license file is not read-only. license.dat is probably the file you want.Article: 33492
"K.O" <alkosd@yahoo.co.uk> wrote in message news:c999654a.0107280312.1a0f8938@posting.google.com... > what is wrong if the clk out is bigger ??? > SRL clk-to-out is bigger than FF clk-to-out, which eats into your timing budget. Especially important on a fast design.Article: 33493
There is a listing of related books on the Programmable Logic Jump Station at the following link. http://www.optimagic.com/books.html I haven't seen a book that exactly covers the material you seek (market opportunity?). On the advanced topics, you might look at the Virtex-II Handbook, available online. http://www.xilinx.com/products/virtex/handbook/index.htm safahmy@hotmail.com (SAF) wrote in message news:<66c23f42.0107160129.530f9e0e@posting.google.com>... > Ok, > > I am looking for a good introductory book, not to VHDL, but more to > the whole shebang behind design of FPGAs. I've done courses in college > on Digital Electronics, and some practicals with Altera PLDs, but I'd > like a way of putting things together. Questions like: > > -How to design with the target architecture in mind > -Good and bad practice > -Efficient use of HDL > -Interfacing with other devices > -Timing considerations > > The more modern the book, the better. I'll probably be getting > Ashenden's "Designer's Guide to VHDL"/2e anyway, so I need something > which would be a good complement. If it covers Xilinx chips, even > better. > > Also, what resources might I use to get in tune with my target > Architecture? Is it just a matter of data sheets and experience? > > The sorts of terms puzzling me: > -Block RAM - how do you use these? > -Distributed RAM > -DLLs - what are they for? > -Cascade Chains > -Different types of clocks (I know wat a clock does, but what're all > the different types?) > > As you can see these are the questions of an ignorant beginner. Hence > the sort of book I need. > > Thanks all.Article: 33494
The modelsim licensing program never asked me for the name of the file containing the license. I think the problem is more basic than that. And at this point I am pretty fed up with the entire licensing fiasco that I have been experiencing. "Tim" <tim@rockylogic.com.nospam.com> wrote in message news:996326790.11050.0.nnrp-02.9e9832fa@news.demon.co.uk... > > "Dave Feustel" <dfeustel@mindspring.com> wrote in message > news:9juddd$357$1@slb6.atl.mindspring.net... > > The ContinuingSaga of Installing Modelsim software on my computer > > > > > Welcome to the Brave New World of Software Licensing > > > > Any other alternatives to Modelsim? > > > > Aldec is better, IMHO. But probably has similar licensing problems > since FlexLM has almost 100% of the licensing software market. > > For your main problem, try checking that the license file is not > read-only. license.dat is probably the file you want. > > >Article: 33495
You might find some useful information on the Programmable Logic Jump Station. VHDL and Verilog Tutorials http://www.optimagic.com/tutorials.html Free Software Page http://www.optimagic.com/lowcost.html Philipp Krause <pkk@spth.de> wrote in message news:<3B594569.9000504@spth.de>... > Are there any free tools around? I'd like to learn VHDL, but don't want > to spend money on commercial software since I don't know which chip > family I'll use when it comes to implementing something. > > Philipp KrauseArticle: 33496
Modelsim licensing refuses to work on my computer. What alternatives to Modelsim are there for Verilog simulation on Windows 2000? Thanks.Article: 33497
I was recently laid off from an employer due to a downturn in tech industries. During the time between jobs I would like to improve my base skills in FPGA design and programming. Could someone please post some xilinx design software. thanks, This will help me find a job. I own a copy of OrCad 7.2Article: 33498
Rick Filipkiewicz wrote: > I've been working around this for some time by maintaining a list of what I > expect to see in the IOBs > and using a perl script to compare that with the last section of the MAP > report. The list, in fact, holds exceptions to the rule that everything is > registered onto & off the chip i.e. the default is to see INFF/OUTFF on an > input/output (or both on a bidir - the script parses the top level module to > get a list of the IOs). I am dealing with this problem right now. I can't seem to find the earlier posts on this topic that would have covered the details that can prevent an inferred FF from being moved to the IOB. I know you can't use the async S/R (other than via GSR) and you can't use the output for any other logic for an OFDX. A manager who has worked this design says you can't even source the FF from internal logic, but rather it has to be connected to another FF output. Anyone know about this? I looked through a hundred or so results in the Xilinx data base, but could not find a doc that summarizes all of the things that are required to let a FF be placed in the IOB. Our parts are 4000XLA. Anyone care to take a stab at this list? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 33499
FH, Try http://www.xilinx.com/sxpresso/webpack.htm It's all free but you may have to register. Dave "feather head" <shyboy1@bellsouth.net> wrote in message news:jtm5mtsmvo1p2ums2on744nfreb3punhfh@4ax.com... > I was recently laid off from an employer due to a downturn in tech > industries. > During the time between jobs I would like to improve my base skills in > FPGA design and programming. > Could someone please post some xilinx design software. > thanks, This will help me find a job. I own a copy of OrCad 7.2 >
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z