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Messages from 33650

Article: 33650
Subject: Re: RAM - VHDL - Altera,...
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 01 Aug 2001 09:21:52 -0700
Links: << >>  << T >>  << A >>
Russell Shaw wrote:

> How does leonardo know? Is it just because a large array of words
> is declared?

Yes, under some size limit it drops back to gates and flops,
You also have to match one of the lpm templates:

http://www.edif.org/lpmweb/documentation/docu_index.html
http://www.edif.org/lpmweb/more/vhdl.htm

 --Mike Treseler

Article: 33651
Subject: Re: Spanning the heirarchy
From: Ken McElvain <ken@synplicity.com>
Date: Wed, 01 Aug 2001 09:48:59 -0700
Links: << >>  << T >>  << A >>
There is an option to Synplify-Pro called Certify-SC that will let you 
bring RTL signals out to pins with no modification of your 
RTL source.  You can also have logic inserted as part of the "probe"
that will minimize the number of pins needed.  This includes insertion
of imbedded logic analysers like Chipscope - again with no mods to the RTL.

Rick Collins wrote:
> 
> I am adding some code to a verilog design for debug and I need to access
> signals in a remote portion of the design. I have been told that there
> is a way to do this in the form of
> "top_level.mid_level.low_level.signal_name" where the level names are
> module instance names. This works ok in simulation, but I can't get it
> to work in synthesis. We are using Synplify. Is this not supported by
> this tool? Is this not supported by any synthesis tool?
> 
> If this is supported for synthesis, any idea what I am doing wrong? Also
> is there a way to use a symbol for the top level part of the name since
> we have a top level test bench in the case of simulation and the top
> level module name has a unique instance name. Could I use a define such
> as `TOP_LEVEL.mid_level... where TOP_LEVEL is a defined symbol?
> 
> Maybe that is what is wrong. In my code I am using the top level module
> name since there is no instance name. Is there something I am missing
> about the top level name? How does the synthesizer know which module is
> the top level?
> 
> --
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

-- 
Ken McElvain, CTO
Synplicity Inc.
(408)215-6060

Article: 33652
Subject: Re: RAM - VHDL - Altera,...
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 01 Aug 2001 09:56:44 -0700
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
> 
> I tried somthing like that but with independent read and write
> address. Latching the address with the clock and reading data
> without clock. BUT Leonardo synthesized unlatched read address
> and latched data out. It's the same function but with a very different
> timing.

I have not seen a case where a leo 
synth netlist did not sim the same 
as the code. If you have such an example, 
please post it.

> I think if you want to use the special functions (like embedded ram)
> in a FPGA you have to code some vendor specific code.

Vendor tools probably give you the 
best fit and utilization.
I haven't run that experiment.

The downside to device specific generators is 
having non-pretty vendor-dependent source code and 
separate simulation models.

It is *not* true however that device vendor 
tools are *required* to get at special
functions like ram, counters, 
carry chains, fifos etc.

Keep in mind that there is no good
business reason for the device vendors
to help you write independent code.


   --Mike Treseler

Article: 33653
Subject: Re: Foundation 2.1 Schematic in WebPack
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Wed, 01 Aug 2001 18:24:01 +0100
Links: << >>  << T >>  << A >>
Hi Simon,

If you are using the Foundation ALDEC version (Project Manager instead of
Project Navigator) then the schematics from WebPACK cannot be read into the
2.1i software. The same applies going the other way around. The two formats
are completely different.

Regards,
SN

Simon Webb wrote:

> Has any one had a go at opening schematic files in WebPack that were
> generated in Foundation 2.1?  I have been sent some source for a 9572 CPLD
> and I would like to use it as a basis for further development.
>
> Any help would be appreciated.
>
> Regards,
>
> Simon
>
> --
> -----------------------------------------


Article: 33654
Subject: Re: Xilinx Foundation 2.1i Update
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 01 Aug 2001 10:38:55 -0700
Links: << >>  << T >>  << A >>
Send money to Xilinx

On Wed, 1 Aug 2001 01:56:19 -0700, LUUTHANHTRUNG <ttcminh@dee.hcmut.edu.vn>
wrote:
>Hi,
>Please tell me how I can update Xilinx Foundation 2.1i .
>Your help will be appreciated .
>Thanks 
>LUU^THANH TRUNG

Philip Freidin
Fliptronics

Article: 33655
Subject: Re: BlockRAM architecture
From: Tim Hubberstey <sendme@no.spam>
Date: Wed, 01 Aug 2001 17:48:20 GMT
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> The Virtex BlockRAM operates synchronously, even in read mode. It thus differs
> from a traditional old RAM where the read operation used to be combinatorial.
> 
> So you need a read clock for Virtex BlockRAMs, but you also get all the
> advantages of fully synchronous operation. For example, you can use the output
> data as the next address, without incurring a race condition.

I have a question regarding the design of BlockRAMs: Why didn't you
include optional output registers as part of the RAM block? This is a
*very* common requirement in high speed designs. Adding them in CLBs and
constraining them so the brain dead place and route tool won't scatter
the registers all over the die is a major hassle.
-- 
Tim Hubberstey, P.Eng. . . . . . . . . . . . . . .  Marmot Engineering
Vancouver, BC, Canada  . . . . . Hardware/Software Consulting Engineer
 . . . . . . . . . . . . . . . .  VHDL, ASICs, FPGAs, embedded systems

Article: 33656
Subject: Re: DLL useage
From: Ray Andraka <ray@andraka.com>
Date: Wed, 01 Aug 2001 20:01:25 GMT
Links: << >>  << T >>  << A >>
We had some trouble in a virtex1000-4 with the combined effects of jitter and skew
caused by loading where that made transfers across this boundary unreliable if the same
edge was used to clock the flip-flop on each side of the boundary (In our case, IIRC,
there was no logic between the flip-flops and they were in adjacent slices within a
CLB).  Since then, we have been very careful not to allow a transfer from one domain to
the other to occur on the same edge.

The outputs from the DLL are supposed to be locked together within a small offset, and
they do as long as you don't have jitter on the input clock (note that you can get
jitter introduced from something as simple as outputs toggling in the same i/o bank as
the clock). The delay on the clock tree is balanced for approximately equal loading, so
you don't get a spread there unless you've got a wide variance in number of loads (we
did, and often do).  We treat the different clock trees as synchronous but with a phase
tolerance that prohibits direct crossing without some intervening delay or by using the
additional clock phases.  After getting bitten once, we take the safe route.

Falk Brunner wrote:

> Ray Andraka schrieb:
> >
> > that has been confirmed by xilinx).  Maybe he is using the DLL for both 1x and 2x
> > clocks and transferring the data between the domains on the same aligned edge
> > (data book says that's OK, but we've seen problems where unequal loading of the
> > clock trees has introduced enough skew to make a direct transfer between the
> > clock0 and clk2x domains unreliable--and that does not change with clock
> > frequency but will work in some parts and not in others and will work at some
> > locations but not others on the chip).  Since he is unwilling to share his test
>
> Hey, what do I hear?? There can be some trouble when using the x1 clock
> and x2 clock of a DLL and treating them as synchronous??
> NOOOOOOO.
>
> Iam currently working on a design, where I would like to divide a 28 MHz
> clock from an XO with the DLL by 4 and simultaneously double the 28 MHz
> to get 56 MHz. Both clocks go onto global clock buffers. The feedback of
> the DLL is feed by the 56 MHz clock net.
> Is this a save design?? Or is it better to use two DLLs, one for
> dividing down and one for doubling?

Two DLLs won't help: you still may have a skew between clocks.  Best solution is to
guarantee using different edges by design.  A second approach is to include enough
delay between registers in different domains to guarantee the propagation time is
greater than the maximum skew.

>
> Or better enter the FPGA with 56 Mhz and just divide by 8?
>
> --
> MFG
> Falk

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 33657
Subject: Re: What way for Xilinx to ASIC migration ?
From: kayrock66@yahoo.com (Jay)
Date: 1 Aug 2001 13:52:40 -0700
Links: << >>  << T >>  << A >>
The typical way of making an ASIC from your Xilinx design is to
re-sythesize the source code targeting the particular standard cell
(oxymoron) library of the foundry your have contracted to fab your
chip.  In general your will need to make some change for memory I/O to
suit the memories for the ASIC process.

While it seems logically possible to do a direct translation of Xilinx
netlist to another cell library, a non-optimal netlist result due to
the inherent differences between these 2 implimentation technologies. 
The die will be larger and slower than you would have otherwise
gotten.

Regards,
Jay

litv@fromru.com (Alexander Litvinov) wrote in message news:<1a6c31a1.0107311751.4fdeee4@posting.google.com>...
> Hi !
> I designed Xilinx project - 1000000 gates(Virtex).
> I want to convert this project to ASIC.
> 1.I know that Xilinx have way to automatic convert FPGA to ASIC.
>   Who try this method? What about advantages of this method ?
> 2.Who know information about translation Xilinx EDIF file to 
>   ASIC ?  I used AutoLogic for this, but now it was dead.
> 
> Thanks
> Alexander

Article: 33658
Subject: Re: Altera MPLD
From: kayrock66@yahoo.com (Jay)
Date: 1 Aug 2001 14:07:51 -0700
Links: << >>  << T >>  << A >>
I'll venture a guess and throw in my 2 cents.  Seems to me that they
are trying to hit a sort of middle ground between a standard cell part
and an FPGA.  The die is certainly going to be larger than a real
ASIC, but you save some engineering because its an automated process. 
They could split the metal mask charges if they mix different
customers parts onto the same mask.  The rest of the layers
photo-tools being reused for all cutomers.  Theoretically the schedule
could be shorter if they have already fabbed wafers and held them at
metal, so you only have to wait for those steps and package/test.

So the niche might be for low volume customers (100's of parts) that
are trying to save some bux or high volume customers that don't know
better or don't have the expertise to make a conversion to standard
cell and would rather give a check to Altera than Synopsys.

Regards,
Jay


"Axel Sautter" <AxelSautter@bigfoot.com> wrote in message news:<9k727s$15d6$1@wrath.news.nacamar.de>...
> Hi all,
> 
> does anyone have more detailed information than those available on As
> website about their MPLD service? Rumours are welcome as well...
> 
> I would like to know something more about this, such as:
> 
> - Time schedule for this service
> - Price informations
> - Minimum ordering quantity
> - Will there be conversions from Apex devices or is A waiting for their new
> Apex II....?
> - Did anyone try this service?
> - Is there really no need to provide test vectors (the website says)
> - What strategy could be behind this service? What target market A want to
> cover with MPLD?

Article: 33659
Subject: Re: What way for Xilinx to ASIC migration ?
From: Muzaffer Kal<muzaffer@dspia.com>
Date: Wed, 01 Aug 2001 14:19:13 -0700
Links: << >>  << T >>  << A >>
kayrock66@yahoo.com (Jay) wrote:

>The typical way of making an ASIC from your Xilinx design is to
>re-sythesize the source code targeting the particular standard cell
>(oxymoron) library of the foundry your have contracted to fab your

I think what's meant by the "standard" in this context is that there
is a single set of cells which is used in all the projects on chip
with fixed width, height and metal connections as opposed to each
group doing a different cell library which makes the chip level
placement/routing very difficult.

Muzaffer Kal
President, DSPIA INC.
http://www.dspia.com


Article: 33660
Subject: Re: Foundation 2.1 Schematic in WebPack
From: Chris Arndt <chris.arndt@xilinx.com>
Date: Wed, 01 Aug 2001 16:17:47 -0600
Links: << >>  << T >>  << A >>
Simon,

Stephan is correct.  The Foundation ALDEC schematics are not compatible with the
ISE or Webpack schematics.  If the design isn't too complex, a Xilinx FAE may be
able to do a conversion for you.

Chris


Stephan Neuhold wrote:

> Hi Simon,
>
> If you are using the Foundation ALDEC version (Project Manager instead of
> Project Navigator) then the schematics from WebPACK cannot be read into the
> 2.1i software. The same applies going the other way around. The two formats
> are completely different.
>
> Regards,
> SN
>
> Simon Webb wrote:
>
> > Has any one had a go at opening schematic files in WebPack that were
> > generated in Foundation 2.1?  I have been sent some source for a 9572 CPLD
> > and I would like to use it as a basis for further development.
> >
> > Any help would be appreciated.
> >
> > Regards,
> >
> > Simon
> >
> > --
> > -----------------------------------------


Article: 33661
Subject: a few xilinx fpga and hdl questions
From: atifh1@yahoo.com (atif)
Date: 1 Aug 2001 15:52:57 -0700
Links: << >>  << T >>  << A >>
Hi ppl,

I am trying to build a parallel port to PC card interface for a
student project. I have a few problems and I will appreciate any help
about them.

1) When reading data from the memory card, I have to make the OE
(output enable) signal low a setup time after I make the read address
valid. How can I get this delay using HDL code? I don't have a clock
that I can use for this purpose.

2) Some of the pins connected with the PC card control signals have to
be open drain with pullup resistor (>10 k). I am not sure how get that
in a Xilinx 4000 series FPGA. The data sheet says I can get an open
drain output by using a tri state ouput buffer(OBUFT), with its input
connected to ground and enable pin to the output signal. Seems to me
that in this case, I will have to use external pull up resistors (not
really interested in doing this). Or can I connect PULLUP at the
output of the buffer? Can I use the BUFOD (open drain buffer) with a
PULLUP as output buffer? Any other ways of doing this?

3) For Global Set/Reset, the manuals say I have to use the INIT
attribute to specify the locat set/reset state of each ff. Where do I
set this INIT attribute....in the schematic or in the code? How? for
example, following is the general structure of my code
   process(clk, reset)
   begin
      if reset='1' then
          x<='0';
          y<='1';
      elsif rising_edge(clk) then
      -- stuff
      end if;
   end process;
What do I have to do so that x and y are reset and set
respectively(using GSR).
Note that the 4000E series that I am using does not seem to have a
STARTBUF module. In has a STARTUP module, which has GSR input, but no
GSR output (as in STARTBUF). Thus using this module will set/reset the
flip flops according to the INIT attribute.

Thanx

Atif

Article: 33662
Subject: spartan & atmel eeproms
From: emanuel stiebler <emu@ecubics.com>
Date: Wed, 01 Aug 2001 17:21:48 -0600
Links: << >>  << T >>  << A >>
Hi,

Anybody here uses an ATMEL serial EEPROm as a configuration
PROM for a SPARTAN XC40 device ?

Which one ?
Problems ?
Hints ?

Cheers & thanks a lot,
emanuel

Article: 33663
Subject: Re: May I connect two pins to the same net?
From: "Peter Ormsby" <faepetedeletethis@mediaone.net>
Date: Wed, 01 Aug 2001 23:32:45 GMT
Links: << >>  << T >>  << A >>

Falk Brunner <Falk.Brunner@gmx.de> wrote in message
news:3B69836F.F6A70539@gmx.de...
> Olaf Reichenbaecher schrieb:
> >
> > Hello all,
> >
> > just a simple question: I am concerned what might happen when
> > I put a Xilinx Virtex part on a board where two package pins
> > are connected to the same net.
> > In the FPGA definetely only one of the pins (inputs) is connected to
> > some logic / clock network. The other is left open / unused.
> > This is because we a using the same board for different versions
> > (with different pinouts) of this FPGA.
>
> >From the FPGA point of view, this is not critical, as long as dont on of
> the two FPGA pins is a ground, VCC or dedicated pin. Unused IO pins are
> tristated by default (unlike Altera parts, where unused pins DRIVE a
> signal :-(
>
> --
> MFG
> Falk
>

I'm not sure where you got your information, but that last statement is just
plain WRONG.
The unused pins behave however you want them to.  Your choices are:

- As input, tri-stated
- As output, driving ground
- As output, driving an unspecified signal

The selection for device wide unused pin behaviour is under the Processing
menu, select Compiler Settings, select the Chips & Devices tab, click on the
Device & Pin options button and select the Unused Pins tab.  You can also
individually assign specific behaviour to pins, e.g. unused pin A34 can be
as input, tri-stated and G15 can be as output driving ground.

-Pete-




Article: 33664
Subject: Re: Err with this AHDL code
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 02 Aug 2001 10:51:51 +1000
Links: << >>  << T >>  << A >>
I can't see a problem. Have you fed it thru the maxplus2 simulator?

Abhimanyu Rastogi wrote:
> 
> Hi all,
> I haveing some trouble with this code I wrote...

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\ Russell Shaw, B.Eng, M.Eng(Research)  /  /\/\
/__/   / Victoria, Australia, Down-Under      /__/\/\/
\  \  /  http://home.iprimus.com.au/rjshaw    \  \/\/
 \__\/                                         \__\/

Article: 33665
Subject: Re: RAM - VHDL - Altera,...
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 02 Aug 2001 11:13:04 +1000
Links: << >>  << T >>  << A >>


Mike Treseler wrote:
> 
> Russell Shaw wrote:
> 
> > How does leonardo know? Is it just because a large array of words
> > is declared?
> 
> Yes, under some size limit it drops back to gates and flops,
> You also have to match one of the lpm templates:
> 
> http://www.edif.org/lpmweb/documentation/docu_index.html
> http://www.edif.org/lpmweb/more/vhdl.htm
> 
>  --Mike Treseler

Interesting. I thought LPM was just an altera thing for AHDL. Are
all device and tools vendors supporting LPM libraries?

I guess its ok to use LPM functions in brand-neutral code then?

Article: 33666
Subject: Re: Altera MPLD
From: "Peter Ormsby" <faepetedeletethis@mediaone.net>
Date: Thu, 02 Aug 2001 02:56:08 GMT
Links: << >>  << T >>  << A >>

Axel Sautter <AxelSautter@bigfoot.com> wrote in message
news:9k727s$15d6$1@wrath.news.nacamar.de...
> Hi all,
>
> does anyone have more detailed information than those available on As
> website about their MPLD service? Rumours are welcome as well...
>
> I would like to know something more about this, such as:
>
> - Time schedule for this service
> - Price informations
> - Minimum ordering quantity
> - Will there be conversions from Apex devices or is A waiting for their
new
> Apex II....?
> - Did anyone try this service?
> - Is there really no need to provide test vectors (the website says)
> - What strategy could be behind this service? What target market A want to
> cover with MPLD?
> --
>
> Thanks!
> cu
> Axel

Axel,

The MPLD program (Marketing Name: Hardcopy) takes your existing,
functioning, APEX 20KE design and converts it to an ASIC-like (or Gate
array-like) device.  The advertised schedule for the conversion is something
like 6-8 weeks from design submission to prototypes (I think you get 10) and
then another 8 weeks after you've verified the operation of the prototypes
in your circuits.  Since the layers of the MPLD that are the Logic Elements
(LUTs/FFs) are common in all hardcopy devices of a given size and it's
mostly just interconnect that is specific to your design, the turn times are
pretty quick.

The cost savings is pretty significant, especially at the large device
sizes.  You'll see something like 80+% cost reduction from the FPGA costs to
the MPLD costs on the largest devices.  Minimum quantity depends on the
device sizes, but for a 20K1500E device, you'll need to order 5,000 parts.
There is a NRE charge somewhere in the $100K to $200K range, once again
dependant upon device size.

The APEX 20KE devices and the Excalibur devices (FPGA with ARM 9 processor
hard core) are available now.  The APEX II device will probably take a while
as this family is just coming available now (contact your local Altera sales
office for schedules).

Test vectors aren't required as Altera has a design checklist up front to
verify that you're not doing anything that won't translate well into the
MPLD devices.  Things like gated clocks and asynchronous circuits need to be
looked at very carefully.  Once you've got a good synchronous design working
in-curcuit, the MPLD device will just drop in (pin-compatible) with very few
differences.  The differences seem to be limited to the obvious higher
speeds (faster Fmax).

The strategy seems to be to target the medium-volume production runs where
recurring cost is the main concern.  Many of the ASIC vendors won't do 5000
piece ASIC runs and if you have a product that has unpredictable volumes
near end-of-life, it's pretty easy to switch back and forth between the MPLD
devies and the FPGA devices (with the obvious trade-off being higher costs
of FPGAs vs. the minimum order quantity of the MPLD).

I hope this helps explain the program.  Contact Altera for more details.

-Pete-



Article: 33667
Subject: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
From: Manoj K Krishnan <mkk3@Ra.MsState.Edu>
Date: Wed, 1 Aug 2001 22:22:53 -0500
Links: << >>  << T >>  << A >>
	Iam trying to build a ROM and RAM module using Xilinx Foundation
series 3.1i (VHDL coding) I tried using Core Generator to generate a
Distributed Memory block. But unfortunately the memory was not properly
generated. It works sometimes but fails sometimes. I tried calling Xilinx
custommer support. I came to know that they have some problem with the
core generator software.

Can anyone suggest me a way to build a ROM and RAM using VHDL coding. Iam
not very particular about using core generator. All I need is to build a
ROM and a RAM which is generic in nature.

thanx for ur help,

-Manoj.


Article: 33668
Subject: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Thu, 2 Aug 2001 10:13:20 +0530
Links: << >>  << T >>  << A >>
Hi,
  Very interesting facts, where do you normally find such benchmarks? I
tried at AMD's site at
http://www.amd.com/products/cpg/athlon/benchmarks/benchmarks.html but didn't
find stuff that you have quoted like Linux compile, MPEG etc. Also what is
"vectorizable code" - pardon me for this newbie question (perhaps a stupid
one), but I am not a SW guy at all.

TIA for any pointers,
Srini

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)


"B. Joshua Rosen" <bjrosen@polybus.com> wrote in message
news:20010730.094756.492067917.10867@polybus.com...
> The Athlon will probably be much faster. The P4 has a very long pipeline
> and really suffers on any code that takes a lot of branches. The relevant
> benchmark is probably the Linux kernel compile time where the Althon is
> about twice as fast as the P4. The place where the P4 shines is in highly
> vectorizable code like MPEG encoding. Place and Route and simulation
> programs aren't vectorized at all. Both of those tasks are compiler like
> so the Athlon is likely to be the best choice.
>
> In article <9j49st$9m4@dispatch.concentric.net>, "Pete Fraser"
> <pete@rgb.com> wrote:
>
> > We're upgrading a few of our old 800 MHz PIII machines to speed Xilinx
> > design.
> >
> > Has anybody published benchmarks to indicate if we'd be better of with
> > fast Athlons or Fast P 4s?
> >
> > Thanks.
> >
> >



Article: 33669
Subject: deskewing PLL/DLL paper
From: yorams@hywire.com (Yoram Stern)
Date: 1 Aug 2001 22:34:45 -0700
Links: << >>  << T >>  << A >>
Hi.
I have seen altera application notes saying PLL usage for deskewing purposes
is better than DLL.
I have seen xilinx application notes saying DLL usage for deskewing purposes
is better than PLL.

I have'nt seen references to these application notes.

I am looking for an unbiased book / paper / research that will tell me what is 
better.

Can you send me a pointer for such book / paper / research ?

ThankX,
Yoram Stern.

Article: 33670
Subject: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
From: Ray Andraka <ray@andraka.com>
Date: Thu, 02 Aug 2001 06:27:51 GMT
Links: << >>  << T >>  << A >>
Depends on your synthesis tool.  If you have synplicity, refer to the the
on-line help.  Synplicity will infer a ROM from RTL coding if you match the
template.

You can also build your own using generates and luts, muxes etc.  painful,
but once you have the code written it will work every time and you can even
place the blocks.  Rams are easier because you don't have to deal with the
initialization.

Manoj K Krishnan wrote:

>         Iam trying to build a ROM and RAM module using Xilinx Foundation
> series 3.1i (VHDL coding) I tried using Core Generator to generate a
> Distributed Memory block. But unfortunately the memory was not properly
> generated. It works sometimes but fails sometimes. I tried calling Xilinx
> custommer support. I came to know that they have some problem with the
> core generator software.
>
> Can anyone suggest me a way to build a ROM and RAM using VHDL coding. Iam
> not very particular about using core generator. All I need is to build a
> ROM and a RAM which is generic in nature.
>
> thanx for ur help,
>
> -Manoj.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 33671
Subject: Re: May I connect two pins to the same net?
From: Falk <>
Date: Wed, 1 Aug 2001 23:54:28 -0700
Links: << >>  << T >>  << A >>
So what the hell means

- as output, driving an unspecified signal????

Is there any use for that??
My opinion is, that the software has to keep its hands of the pins, unless I tell them to do other. So unused pins should be tristated by default (not after you set a tiny switch hidden deep down in the 10th option menu :-(

Regards
Falk

Article: 33672
Subject: Re: finite defect statistics
From: Falk <>
Date: Thu, 2 Aug 2001 00:22:36 -0700
Links: << >>  << T >>  << A >>
Ok, I think the easiest and safest solution is a synchronizing FF working on the other (here the falling) edge.
Thanks a lot for the warning and advice.

Regards
Falk

Article: 33673
Subject: Re: spartan & atmel eeproms
From: "Felix Bertram" <fbertram@gmx.net>
Date: Thu, 2 Aug 2001 09:37:07 +0200
Links: << >>  << T >>  << A >>
Emanuel,


> Anybody here uses an ATMEL serial EEPROm as a configuration
> PROM for a SPARTAN XC40 device ?
> Which one ?

we have successfully used AT17LV512 with XCS30XL devices.

> Problems ?
> Hints ?

You can program the boards using Xilinx Parallel Cable III and some simple
home-brew software. If this would help, contact me directly.

Watch out to program the correct reset polarity!

Hope this helps,
best regards

Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 49 39 755
Fax.: +49 (0) 5223 48 945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de




Article: 33674
Subject: Re: RAM - VHDL - Altera,...
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Thu, 02 Aug 2001 07:52:48 GMT
Links: << >>  << T >>  << A >>
> Interesting. I thought LPM was just an altera thing for AHDL. Are
> all device and tools vendors supporting LPM libraries?
>
> I guess its ok to use LPM functions in brand-neutral code then?

I also thought that's good news. But I tried today to use LPMs
in Xilinx WebPack but it's not supported:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=5163

So again two versions for A and X.

Martin
--
Whant to see the evolution of a Java processor?

         http://www.jopdesign.com






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