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Messages from 34850

Article: 34850
Subject: Innoveda and ISE Alliance 4.1i ?
From: "Pete Dudley" <padudle@sandia.gov>
Date: Tue, 11 Sep 2001 10:12:48 -0600
Links: << >>  << T >>  << A >>
I just installed ISE Alliance 4.1i and find no support for Innoveda tools.
There are no Viewdraw libraries shipped with the software and no Innoveda
Interface Guide in the online documentation. There is still a Mentor
Graphics Interface Guide.

Has Xilinx stopped working with Innoveda? I would consider that a shame.

--
Pete Dudley
Sandia National Labs
padudle@sandia.gov



Article: 34851
Subject: Re: Open collector outputs
From: Alan Nishioka <alann@accom.com>
Date: Tue, 11 Sep 2001 09:19:49 -0700
Links: << >>  << T >>  << A >>
Note that you *cannot* pull up the signal higher than VIO (in this case 3.3V).
The input protection diodes prevent this.

Alan Nishioka
alann@accom.com



Article: 34852
(removed)


Article: 34853
Subject: Missing bits Part 2!
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 11 Sep 2001 20:06:51 +0200
Links: << >>  << T >>  << A >>
Hi,

For those of you who missed my last post Missing Bits, I seem to be missing
some bits when I read in a 4 bit, 32Mhz signal from an ADC and was wondering
if anyone can help me. Since the last plea for help, I am using a 32Mhz
clock, coming into a BUFGDLL. This clock then goes out the FPGA again and
clocks an ADC. It also goes to the clock input of a registered adder. The 4
bit input (the MSB bits of a 6bit ADC) go from the input pads, to the input
buffers, and then onto a bus which feeds directly into the adder. I have
registered my IOB's. The outputs of the adder then go to a register, after
which the signal is outputted for testing.
I still appear to be getting glitches on my signal, and am missing some
bits. Can anyone give any more advice???????

Thanks
Adrian




Article: 34854
Subject: Re: Missing bits Part 2!
From: John_H <johnhandwork@mail.com>
Date: Tue, 11 Sep 2001 18:12:23 GMT
Links: << >>  << T >>  << A >>
A new suggestion:

Look past "missing" data... Are the data bits that are going out correct?


Noddy wrote:

> Hi,
>
> For those of you who missed my last post Missing Bits, I seem to be missing
> some bits when I read in a 4 bit, 32Mhz signal from an ADC and was wondering
> if anyone can help me. Since the last plea for help, I am using a 32Mhz
> clock, coming into a BUFGDLL. This clock then goes out the FPGA again and
> clocks an ADC. It also goes to the clock input of a registered adder. The 4
> bit input (the MSB bits of a 6bit ADC) go from the input pads, to the input
> buffers, and then onto a bus which feeds directly into the adder. I have
> registered my IOB's. The outputs of the adder then go to a register, after
> which the signal is outputted for testing.
> I still appear to be getting glitches on my signal, and am missing some
> bits. Can anyone give any more advice???????
>
> Thanks
> Adrian


Article: 34855
Subject: Re: Missing bits Part 2!
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 11 Sep 2001 20:27:37 +0200
Links: << >>  << T >>  << A >>
Not really...I'm just testing with a sinusoidal, and the output signal kind
of looks like a sinusoid, except that there are little glitches along the
signal. Also, the signal appears to be too quantised.



> A new suggestion:
>
> Look past "missing" data... Are the data bits that are going out correct?
>
>
> Noddy wrote:
>
> > Hi,
> >
> > For those of you who missed my last post Missing Bits, I seem to be
missing
> > some bits when I read in a 4 bit, 32Mhz signal from an ADC and was
wondering
> > if anyone can help me. Since the last plea for help, I am using a 32Mhz
> > clock, coming into a BUFGDLL. This clock then goes out the FPGA again
and
> > clocks an ADC. It also goes to the clock input of a registered adder.
The 4
> > bit input (the MSB bits of a 6bit ADC) go from the input pads, to the
input
> > buffers, and then onto a bus which feeds directly into the adder. I have
> > registered my IOB's. The outputs of the adder then go to a register,
after
> > which the signal is outputted for testing.
> > I still appear to be getting glitches on my signal, and am missing some
> > bits. Can anyone give any more advice???????
> >
> > Thanks
> > Adrian
>



Article: 34856
(removed)


Article: 34857
Subject: Re: Innoveda and ISE Alliance 4.1i ?
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 11 Sep 2001 12:13:05 -0700
Links: << >>  << T >>  << A >>
Well I did a 4.1i install (for PC) and selected
   "Innoveda Interface Libraries"

and it seems to have installed all the libraries in the expected place:

   D:\Xilinx\viewlog\data\ ...

But I agree that the Interface Guide seems to be missing

Philip.

On Tue, 11 Sep 2001 10:12:48 -0600, "Pete Dudley" <padudle@sandia.gov> wrote:
>I just installed ISE Alliance 4.1i and find no support for Innoveda tools.
>There are no Viewdraw libraries shipped with the software and no Innoveda
>Interface Guide in the online documentation. There is still a Mentor
>Graphics Interface Guide.
>
>Has Xilinx stopped working with Innoveda? I would consider that a shame.

Philip Freidin
Fliptronics

Article: 34858
Subject: Re: Spartan II JTAG configuration
From: atali@cygrp.com (Aare Tali)
Date: 11 Sep 2001 12:55:37 -0700
Links: << >>  << T >>  << A >>
> I dont get your problem. When DONE goes high, everything should wor
> fine.

So far it does. But I was worried that if verify fails, there might be
problems in some areas of the chip that are not detected when
programming. Just like flash, you burn it and verify after that just
to be sure.

> What kind of noard do you have ? Homemade or professional Prototype
> board?

Homemade, so far works fine.

Article: 34859
(removed)


Article: 34860
Subject: Re: Selection of a suitable FPGA board
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 12 Sep 2001 00:24:35 +0100
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:

>
>
> You're right, it looks like the high signal spec is v. marginal.
>
> In advance of Austin F. I'm going into our lab tomorrow to both try out a few 5V PCI cards
> and have a look at the signal quality on a DSO.

I've had a first look with the DSO & the - small - sample of 3V3 signals look very clean with
not even a sign of a reflection step. The time from clock rising to 2V4 varies from about 9-10
nsec with no 5V cards plugged in to 12-13 nsec fully populated. No signs even of any ringing,
just a nice monotonic rising edge.

The situation is very simple with an Eth chip polling its Tx ring and the CPU polling the Eth
stat reg.
Since the network ports near the 'scope were down I'll have to wait a couple of days to get
some burst data going.




Article: 34861
Subject: Question concerning Verilog scheduling
From: Tom <tomcip@concentric.net>
Date: 11 Sep 2001 23:33:41 GMT
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;
<p>Hi,
<p>I have a question concerning the processing of events from the Verilog
Active Events Queue. In section 5.3 of&nbsp; IEEE std 1364-1995, defining
the Stratified Events Queue, there is the following statement.
<br>&nbsp;
<blockquote TYPE=CITE>
<pre>1) Events that occur at the current simulation time and can be processed in any order. These are the active
events.</pre>
</blockquote>

<p><br>Does this imply that events that occur at the current simulation
time can be put <b>on</b> the active events queue in any order or taken
<b>off
</b>the active events queue in any order? I would think that putting them
<b>on</b> the queue in any order would make more sense.
<br>&nbsp;
<br>&nbsp;
<blockquote TYPE=CITE>
<pre>5.4.1 Determinism
This standard guarantees a certain scheduling order.
1) Statements within a begin-end block shall be executed <b>in the order in which they appear in that begin-
end block</b>. Execution of statements in a particular begin-end block can be suspended in favor of other
processes in the model; however, in no case shall the statements in a begin-end block be executed in any
order other than that in which they appear in the source.</pre>
</blockquote>

<p><br>The above statement seems to conflict with the first statement.&nbsp;
One way that I can interpert this is to say that if I had only one proceedural
begin-end block which was scheduled for a specific time, then the begin-end
block itself can be considered <b>an event</b>. Statements within the begin-end
block would be executed (put onto the active events queue and taken off
the active events queue) in the order in which they appear in that begin-end
block. If I had more than one begin-end block scheduled for the same time,
as would happen if, say, I had the same clock going to different begin-end
blocks in different modules, then each begin-end block could be placed
on and off the active events queue in any order. The statements within
each begin-end block would be executed in the order in which they appear.
<br>Would this interpertation be correct?
<blockquote TYPE=CITE>
<pre>5.4.2 Nondeterminism
One source of nondeterminism is the fact that active events can be taken off the queue and processed in any order.</pre>
</blockquote>

<p><br>Again, is an event considered a single statement or could an event
be considered a group of statements.
<br>&nbsp;
<p>Finally, in the example below, which statement is the "expression evaluation
" and and which is the "net update event"?
<blockquote TYPE=CITE>
<pre>
assign p = q;
initial begin
q = 1;
#1 q = 0;
$display(p);
end</pre>
</blockquote>

<p>Thank You
<br>Tom Cipollone
<br>tomcip@concentric.net
<br>&nbsp;</html>


Article: 34862
Subject: Re: Give me some information!
From: sknapp@triscend.com (Steven K. Knapp)
Date: 11 Sep 2001 17:13:21 -0700
Links: << >>  << T >>  << A >>
You can also try The Programmable Logic Jump Station at
http://www.optimagic.com, though the FAQ is a bit old.



John <jiangz00@mails.tsinghua.edu.cn> wrote in message news:<ee72386.-1@WebX.sUN8CHnE>...
> hi 
> 
> Do have someeone have some fpga 
> 
> web or newsgroup or faq site 
> 
> address familiar with the 
> 
> comp.arch.fpga. pls tell me! 
> 
> thanks a lot

Article: 34863
Subject: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
From: Arthur <>
Date: Tue, 11 Sep 2001 18:29:13 -0700
Links: << >>  << T >>  << A >>
David- 
Nope, no Xilinx software package comes with Leonardo and Synplify. The website is definitely not clear in specifying that it has 'integration' with Synplify and Leonardo, but does not come with these products. What this 'integration' means is that you don't need to open up Synplify or Leonardo to get access to their synthesis options - so you can do the entire design flow from one GUI.

Regards,
Arthur

Article: 34864
Subject: Re: Missing bits Part 2!
From: "Tony Proudfoot" <tonyp@vl.com.au>
Date: Wed, 12 Sep 2001 11:52:23 +1000
Links: << >>  << T >>  << A >>

You say you are using the 4MSBits of a 6-bit ADC. Is your input sinusoid
suitably scaled to fill the 6 bits ?

I sometimes find it helps to rewind a bit to get the mechanics working. Use
a pot and a 1MHz clock. Then once your satisfied its all working, wind up
the clock.


Tony.
_________________________________
 Tony Proudfoot, tonyp@vl.com.au
 Hardware Design Engineer
 Virtual Logic Pty Ltd
 Ph: +61(0)2 9599 3255
 _________________________________

"Noddy" <g9731642@campus.ru.ac.za> wrote in message
news:1000232632.239843@turtle.ru.ac.za...
> Not really...I'm just testing with a sinusoidal, and the output signal
kind
> of looks like a sinusoid, except that there are little glitches along the
> signal. Also, the signal appears to be too quantised.
>
>
>
> > A new suggestion:
> >
> > Look past "missing" data... Are the data bits that are going out
correct?
> >
> >
> > Noddy wrote:
> >
> > > Hi,
> > >
> > > For those of you who missed my last post Missing Bits, I seem to be
> missing
> > > some bits when I read in a 4 bit, 32Mhz signal from an ADC and was
> wondering
> > > if anyone can help me. Since the last plea for help, I am using a
32Mhz
> > > clock, coming into a BUFGDLL. This clock then goes out the FPGA again
> and
> > > clocks an ADC. It also goes to the clock input of a registered adder.
> The 4
> > > bit input (the MSB bits of a 6bit ADC) go from the input pads, to the
> input
> > > buffers, and then onto a bus which feeds directly into the adder. I
have
> > > registered my IOB's. The outputs of the adder then go to a register,
> after
> > > which the signal is outputted for testing.
> > > I still appear to be getting glitches on my signal, and am missing
some
> > > bits. Can anyone give any more advice???????
> > >
> > > Thanks
> > > Adrian
> >
>
>



Article: 34865
Subject: Re: Question concerning Verilog scheduling
From: Parvathy Uma <parvathy.uma@verizon.net>
Date: Wed, 12 Sep 2001 02:10:20 GMT
Links: << >>  << T >>  << A >>


>
>
>
>> 1) Events that occur at the current simulation time and can be processed in any order. These are the active
>> events.
>>
>
> Does this imply that events that occur at the current simulation time
> can be put on the active events queue in any order or taken off the
> active events queue in any order? I would think that putting them on
> the queue in any order would make more sense.

Well, it can be both ; right? For example , think of fanouts of a net:
they are all scheduled for updating in any order by putting them on the
active event queue. What the spec  says is that even if you can
guarantee by magic  that they get put in the event queue in a certain
order (by observing behavior of the simulator under use and tweaking
where the source code appears) , the simulator does not guarantee that
the events will be taken of the queue in the same order  if the
circumstances were changed even slightly (maybe by  adding a new source
file or something ). In other words it does not guarantee  delta time
behavior like VHDL does

>
>
>> 5.4.1 Determinism
>> This standard guarantees a certain scheduling order.
>> 1) Statements within a begin-end block shall be executed in the order in which they appear in that begin-
>> end block. Execution of statements in a particular begin-end block can be suspended in favor of other
>> processes in the model; however, in no case shall the statements in a begin-end block be executed in any
>> order other than that in which they appear in the source.
>>
>
> The above statement seems to conflict with the first statement.  One
> way that I can interpert this is to say that if I had only one
> proceedural begin-end block which was scheduled for a specific time,
> then the begin-end block itself can be considered an event. Statements
> within the begin-end block would be executed (put onto the active
> events queue and taken off the active events queue) in the order in
> which they appear in that begin-end block. If I had more than one
> begin-end block scheduled for the same time, as would happen if, say,
> I had the same clock going to different begin-end blocks in different
> modules, then each begin-end block could be placed on and off the
> active events queue in any order. The statements within each begin-end
> block would be executed in the order in which they appear.
> Would this interpertation be correct?

You are not entirely correct. The begin end block cannot be considered
as a single event because within the begin end block you may be
affecting variables that have fanouts. These may cause more active
events. Or, the begin-end block may have delays.

However , you are correct in saying that if you had the same clock going
to different begin-end blocks in different modules, they (or rather the
statements in them) can be placed on and off the active events queue in
any order. The only thing the standard guarantees is that within a
begin-end block , statements get executed in the order they appear (and
not always)
The only counter example I know  is when you have
a<= #5 1'b1;
a<= #5 1'b0;

In this case , the behavior is non-deterministic. You may want to read
the Verilog 2000 spec . It  has changed the language for this section to
remove inconsistencies.


>
>
>> 5.4.2 Nondeterminism
>> One source of nondeterminism is the fact that active events can be taken off the queue and processed in any order.
>>
>
> Again, is an event considered a single statement or could an event be
> considered a group of statements.
>
>

It depends on the simulator and maybe even the mode you are running :
for example certain optimizations can collapse all the events in a
begin-end block to a single event if you are not in the debug mode.
A stupid example would be when  you have
 begin
  a=0;
  a=1; // This never needs to be executed unless you are single stepping

         // or if you have a $display between each statement
  a=0;
 end


>
> Finally, in the example below, which statement is the "expression
> evaluation " and and which is the "net update event"?
>
>> assign p = q;
>>
I  do not have the LRM open, so I may be a bit off , but
the net update event is when p gets scheduled with the new value of the
expression on the rhs, in this case a simple expression q . It follows
that expression evaluation is when the value of q gets computed. AFAIK,
expression evaluation always happens instantaneously. There is no
scheduling (or events ) associated with expression evaluation. If I am
wrong , I hope someone will correct me.

Hope this helps
Uma



Article: 34866
Subject: Re: ISE 4.1
From: "Andrew Dyer" <adyer@enteract.com>
Date: Wed, 12 Sep 2001 04:10:30 GMT
Links: << >>  << T >>  << A >>

"David Wright" <dwright@srtorque.com> wrote in message
news:4S3m7.232735$NK1.21400208@bin3.nnrp.aus1.giganews.com...
> Xilinx's ISE 4.1 sounds promising.  After talking to my local Xilinx
> representative, it should be available shortly.  My current project is
2300
> lines of untested VHDL code including a small test vector.  The WebPack
has
> a limit of 500 lines.
>
> I was assured the ISE 4.1 was all that I might need to do my design.
> However,  I am skeptical as to the adequacy of the simulator.  As I
learned
> from past experience with Cypress and Altera, test and verification are of
> key importance to a design.
>

I tried installing it today at work - (someone had to be first...)

Beware if you have a machine with an Athlon CPU.  There are problems
with "some" Athlon boards.  I have a 1.1 GHz Athlon on an ASUS mobo
with 768 Mb of Micron memory running Win 2000 SP2 and I was getting
lockups running ngdbuild that required a hard reset.  The system is
otherwise
very solid running Modelsim, older Xilinx tools, Foundation express, etc.

 Fortunately I didn't uninstall my old tools, just installed the 4.1i stuff
in a new
directory and changed the %XILINX% environement variable.

My advice is to wait for a few service packs to go by unless you want to be
a guinea pig like me :-)



Article: 34867
Subject: Re: Data cache for fpga-cpu using Xilinx BlockRam
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Wed, 12 Sep 2001 00:21:18 -0400
Links: << >>  << T >>  << A >>

"Erik Widding" <widding@birger.com> wrote in message
news:ihnn7.15659$Uf1.1369777@bgtnsc06-news.ops.worldnet.att.net...
>
> If you are having a speed problem, you should probably be using two pual
> port rams, one for instruction and one for data.  Then use the second port
> on each of the memories as the interface to your external memory.

Thanks for the suggestion, but duh, I can't see how using the second port to
interface to external memory would improve performance (talking about
reducing clock cycle time). What does it give me? I know it's difficult to
illuminate over the net, but could you give some examples ? Code ?

As I see it there is only din,dout,addr,and wr to worry about with the
cache. din is always connected to the databus no mux required here, dout is
connected back to the data bus with an unavoidable mux (the cpu might be
trying to read i/o not memory). I can't avoid a mux on the addr inputs
because of the way block ram works. Because the memory transactions are
pipelined, and the block ram's register the read address on the clock edge,
the address for the next read needs to be present before the clock edge.
Once the clock edge occurs (provided pipe is enabled) the read address at
the input will change to the next read address. Since we can't tell whether
there was a cache miss or hit until after the clock, and the read address
has already advanced to the next address on the clock edge, the address has
to be muxed back to the previous address in order to re-read on a cache
miss. I sure would like to avoid that mux on the address.. Controlling wr
isn't that hard, it's activated when the memory system is ready and is a
registered output on a clock edge.

When I started I had only an instruction cache using one port to interface
to memory, and the second port for cpu cache access. However, after looking
at the code and some timing experimentation I found using the second port
for memory access didn't provide any benefit; but I could be missing
something.
I then decided to add a data cache so I had two independent caches one for
instructions and one for data. However when I looked at them I realized I
was only using one port on each and hence could combine the two. By
combining the two I made a larger cache and was able to use some block rams
for cache data that were previously used as tag rams; thus making the cache
even larger. So I can have either a 4kb unified cache or two 1kb independent
cache.

>  If you
> have a cache miss, you will have to insert one wait state, so that you can
> read the memory location that was just fetched.

On a miss I have to insert at least two wait states because I have one or
more for memory arbitration as well as an additional cycle for external ram
read. :(

> Further, if every time you
> have a miss, you fetch four or
> eight data/instruction words, then it is likely that you will suffer fewer
> misses.
>

Right now I have a fairly simple system. Without adding fifos to various i/o
devices I can't really read more than one word at a time. For instance the
vga controller could require about one out of every three or four memory
cycles.


Thanks
Rob
http://www.birdcomputer.ca






Article: 34868
Subject: LeonardoSpectrum Timing reports
From: prv3299@yahoo.com (Paulo Valentim)
Date: 12 Sep 2001 01:19:21 -0700
Links: << >>  << T >>  << A >>
Hi,

Can any one explain me how to interpret this timing report generated by
LeonardoSpectrum.


My doubt is : because I specified a clock of 40MHz, I don't understand why
it says that I can use up to 68.5 MHz (I think) but with a negative slack.


==============================================
****************************************
        Clock Frequency Report
****************************************

Clock                : Frequency
------------------------------------
CLK                  : 68.5 MHz

Critical path #1, (path slack = -5.1):

NAME                           GATE              ARRIVAL              LOAD
----------------------------------------------------------------------------
---
CLK (offset)                                     0.00 (rising edge)
delay thru clock network                         4.00 (worst case)
I4_I0_reg_fifo_prs_l/CLK       DFFC_P            4.00 (rising edge)

I4_I0_reg_fifo_prs_l/Q         DFFC_P            0.00  9.10 up       6.50
fifo_prs_l/Y                   NOT               0.00  9.10 up       9.49
fifo_prs_l/                                      0.00  9.10 up       0.00
data arrival time                                      9.10

data required time                                     4.00
----------------------------------------------------------------------------
---------------
data required time                                     4.00
data arrival time                                      9.10
                                                    ----------
slack                                                -5.10
----------------------------------------------------------------------------
--------------- 


And I appreciate if anyone can tell me where I can find documents that
explain this timing reports.


Thanks in advance,

Paulo

Article: 34869
Subject: Re: FPGA Evaluation Board for image processing
From: "Ken" <aeu96186@yahoo.co.uk>
Date: Wed, 12 Sep 2001 09:21:23 +0100
Links: << >>  << T >>  << A >>

Try http://www.nallatech.com

Cheers,

Ken

"Dave Moore" <dave.m.moore@baesystems.com> wrote in message
news:3B9E0070.A12DE8B4@baesystems.com...
> Hi All,
>     I'm investigating the possible use of an FPGA based system for high
> bandwidth realtime image processing. What I'm really after is an
> evaluation board, that's capable of sampling SXGA (1280x1024) video at
> 60Hz, performing processing upon the captured image and splitting it out
> through a video output (analogue or digital).
>
> Any ideas of a possible source for such a card/board?.
>
> Regards,
> Dave
>
>



Article: 34870
Subject: Re: LeonardoSpectrum Timing reports
From: Alan Fitch <alan.fitch@doulos.com>
Date: Wed, 12 Sep 2001 09:30:03 +0100
Links: << >>  << T >>  << A >>
In article <5ed45146.0109120019.65eb445b@posting.google.com>, Paulo
Valentim <prv3299@yahoo.com> writes
>Hi,
>
>Can any one explain me how to interpret this timing report generated by
>LeonardoSpectrum.
>
>
>My doubt is : because I specified a clock of 40MHz, I don't understand why
>it says that I can use up to 68.5 MHz (I think) but with a negative slack.
>
>
>==============================================
>****************************************
>        Clock Frequency Report
>****************************************
>
>Clock                : Frequency
>------------------------------------
>CLK                  : 68.5 MHz
>
>Critical path #1, (path slack = -5.1):
>
>NAME                           GATE              ARRIVAL              LOAD
>----------------------------------------------------------------------------
>---
>CLK (offset)                                     0.00 (rising edge)
>delay thru clock network                         4.00 (worst case)
>I4_I0_reg_fifo_prs_l/CLK       DFFC_P            4.00 (rising edge)
>
>I4_I0_reg_fifo_prs_l/Q         DFFC_P            0.00  9.10 up       6.50
>fifo_prs_l/Y                   NOT               0.00  9.10 up       9.49
>fifo_prs_l/                                      0.00  9.10 up       0.00
>data arrival time                                      9.10
>
>data required time                                     4.00
>----------------------------------------------------------------------------
>---------------
>data required time                                     4.00

                                                        ^^^^^
where does this come from?

It looks to me that you might have accidentally specified a 4ns clock,
rather than a 40 ns clock??

regards

Alan


-- 
Alan Fitch
DOULOS Ltd.
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Tel: +44 1425 471223                           Email: alan.fitch@doulos.com
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Article: 34871
Subject: Error messages
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Wed, 12 Sep 2001 12:25:22 +0200
Links: << >>  << T >>  << A >>
For some reason, my design is not implementing anymore. does anyone know
what the following error message means

            Pcm: Specified revision is invalid

adrian




Article: 34872
Subject: Programming Delays in ABEL
From: Pedley@talk21.com (M Pedley)
Date: 12 Sep 2001 03:32:25 -0700
Links: << >>  << T >>  << A >>
I need my ABEL code to give a constant output for 2 seconds after it
is switched before flash patterns begin

there is a clock input(10 Hz)

peusdocode ->

when (input switches to 1) output = 1; delay for 2 secs; then
          output = flash pattern; //carry on as normal

Is there a way to do this in ABEL? can anyone give me any ideas.

Thankyou

Matt

Article: 34873
Subject: Re: Using falling and rising clock mistery.
From: Michal Rutka <rutka@lucent.com>
Date: 12 Sep 2001 14:16:21 +0200
Links: << >>  << T >>  << A >>
>>>>> "Nicolas" == Nicolas Matringe <nicolas.matringe@IPricot.com> writes:

 Nicolas> Michal Rutka a écrit :
 >>  Hello all,
 Nicolas> [...]
 >> After synthesis I've noticed that this circuit have the same
 >> maximum frequency as a circut in which process 'b' is triggered on
 >> the positive edge. Is this flaw of Leonardo? How other synthesis
 >> tools handle it?

 Nicolas> Hi It depends on wher 'o' comes from. If it's just an input,
 Nicolas> ther's no problem. If it's the output of another FF (clocked
 Nicolas> by the same clock signal) then you should notice that the
 Nicolas> max frequency is half the frequency you get when using the
 Nicolas> same edge for all FFs.

Exactly. I've checked with Synopsys FPGA compiler, and there
everything is OK. Thus this is Leonardo bug.

Regards,

Michal

P.S1. From Leonardo report I see that they constrain such a case with
1.5 x clock period instead of 0.5.
P.S2. I wonder how Symplicity handle this case?

Article: 34874
Subject: Re: WebPack Con-Game
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 12 Sep 2001 06:41:47 -0700
Links: << >>  << T >>  << A >>
Since there were people including myself who were able to synthesize
and simulate working designs exceeding 500-lines of code, why not give
it a try?
Since the tools are free, there is nothing to lose.
Although, I cannot find it now, Xilinx's website used to mention that
the ModelSim XE-Starter has a 500-line code limitation, but it did
also note that the simulator doesn't stop the simulation even after
the 500-line code limit.
As I mentioned somewhere in the thread, I have simulated a 8,000 gate
post-routed version of my design that exceeded the limit by about
23,000 lines of code.
It took about 40 minutes to simulate it for 4000ns at 33MHz.



Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

 


"David Wright" <dwright@srtorque.com> wrote in message news:<Gcpl7.202944$VV1.14811252@bin1.nnrp.aus1.giganews.com>...
> False advertising is unlawful.
> 
> Eric Smith wrote in message ...
> >"David Wright" <dwright@srtorque.com> writes:
> >> The "free" Xilinix Webpack should be classified as a Demo and not a real
> >> system to do even realistic small designs.
> >
> >You get what you pay for.  Naturally the free package provides less
> >functionality than the expensive package; how can you rationally expect
> >otherwise?  Calling it a "con game" seems entirely uncalled for; the
> >features and limitations of WebPack are plainly described on the web site.
> >
> >I've found it to be perfectly usable for a design with a 32-bit RISC
> >core, memory, UART, Ethernet, and timers.  I did my simulation using
> >Savant.
> >



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