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Messages from 34925

Article: 34925
Subject: Re: Clock Multiplication
From: Paul Hardy <paul.hardy@xilinx.com>
Date: Fri, 14 Sep 2001 12:20:38 +0200
Links: << >>  << T >>  << A >>
If you have a 50/50 input signal, you can use it to double the frequency ( takes
one XOR, one inverter and a ff ), and you then divide by three.
If the input is not 50% duty cycle, you get a strangely modulated output
frequency.

Peter Alfke, presently stuck in Stockholm, until air traffic resumes...

Sriram S wrote:

> Hi friends,
>
> Without using a DLL/PLL how can i multiply a clock by 1.5.
>
> I belive a Lookup Table method can be used. But this is not an optimal method.
> Please give more ideas on this.......
>
> Kind regards
> sriram


Article: 34926
Subject: Re: Foundation 3.1i REINSTALLATION
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Fri, 14 Sep 2001 11:28:39 +0100
Links: << >>  << T >>  << A >>
For Xilinx stuff, I believe you only have to install the CDs and
then the most recent update/patch.  Check with Xilinx support.

"jdiaz_pr" <jdiaz_pr@excite.com> wrote in message
news:ae1bba04.0109132034.6e95fd91@posting.google.com...
> Hi,
>
> I got a virus that erased my C: drive, is there a way to reinstall de
> S/W over the D: drive (yet installed) without requiring to do the
> tedious patching/update procedure. I tried the installation over
> another tool A-HDL giving me many headaches trying to enable the
> floating license (no success so far). I am pondering to uninstall (or
> erase) the whole D: drive's tools directories and start with some
> 'clean' installations. In any case a "XIE internal error 101" message
> from Foundation may indicate several no registry entries available (I
> think).
>
> If you like to share some experiences, we ALL be grateful!
>
> Peace!



Article: 34927
Subject: Re: Looking for knowledge on CORDIC, division, correlators, TSBs, sorting, and path-delay handling
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Fri, 14 Sep 2001 11:31:51 +0100
Links: << >>  << T >>  << A >>

"jdiaz_pr" <jdiaz_pr@excite.com> wrote in message
news:ae1bba04.0109132101.41589132@posting.google.com...
> Hello everyone!
>
> I got several questions; hope to have answers to some:
>
> 1. Can you share experiences on CORDIC using Xilinx 4K architecture
> (i.e., strictly using its primitives) and how it compares with a
> Virtex implementation?

CORDIC comes up from time to time.  Check the archives and Google.

> 6. This is the last naive question: Implementing an intensive
> arithmetic path, which for some instances its delay path, is shorted
> by a no-intense arithmetic 'case' condition. How can I do the
> reconciliation on the next stage input, in the sense of "data_ready"
> condition taking in account a fixed clocking scheme?

In X architecture, use SRLs in the short path.  You need
to match path delays.




Article: 34928
Subject: Re: Segmented interconnects
From: Paul Hardy <paul.hardy@xilinx.com>
Date: Fri, 14 Sep 2001 12:36:00 +0200
Links: << >>  << T >>  << A >>
Be careful so you don't fall victim to poisoned propaganda.
Whenever one company touts its advantages over the arch-competitor, take
that information with a big fistful of salt. Marketing knows how to present
anything in a beautiful light, and the truth often is the victim.
The PREP data cited by Altera is outdated, and was crap even when it was
young, 8 years ago.
The proof of the pudding is the performance and density you can achieve for
a given cost and pc-board complexity. Since Xilinx and Altera are still
very much in business, you can assume that both offer attractive devices.
In my humble opinion, Xilinx FPGAs offer higher performance and more
features, but you may have to figure this out yourself. There is no generic
answer.

Peter Alfke, presently stuck in Stockholm...

Russell Shaw wrote:

> Hi all,
>
> What advantages/disadvantages do segmented-interconnect fpgas have over
> continuous interconnect cplds?
>
> Is there more flexibility in placing pins with segmentation?
>
> A vs X:
>
>   http://www.altera.com/literature/pib/pib18_01.pdf
>
> --
>    ___                                           ___
>   /  /\                                         /  /\
>  /  /__\ Russell Shaw, B.Eng, M.Eng(Research)  /  /\/\
> /__/   / Victoria, Australia, Down-Under      /__/\/\/
> \  \  /  http://home.iprimus.com.au/rjshaw    \  \/\/
>  \__\/                                         \__\/


Article: 34929
Subject: Re: Virtex-E1600 unsupported?
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Fri, 14 Sep 2001 11:38:14 +0100
Links: << >>  << T >>  << A >>
I think you need the 'Foundation for real men' upgrade.

As a .ac you will probably get this real cheap.  And so should anyone
else using a reasonable number of these parts.  How much are they now?


"Michael Boehnel" <boehnel@iti.tu-graz.ac.at> wrote in message
news:3BA1C966.C209A63D@iti.tu-graz.ac.at...
> Hello!
>
> I'm trying to implement a design on a VirtexE-1600 or higher. I use
> Foundation 3.1i and Service Pack 8, FPGA Express.
>
> While VirtexE-1000 is supported I get the following message with
> XCV1600E or higher:
> Error Message: The specified part XCV1600E-6-BG560 is either invalid or
> not supported.
>
> Is this a problem of FPGA Express or Foundation?
>
> Can someone tell me where I can find a documentation (file or www) with
> the supported single devices?
>
> Thanks,
>
> Michael
>
>



Article: 34930
Subject: Re: Clock Multiplication
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Fri, 14 Sep 2001 11:39:38 +0100
Links: << >>  << T >>  << A >>

"Paul Hardy" <paul.hardy@xilinx.com> wrote in message
news:3BA1D9F6.FE2894DE@xilinx.com...
> If you have a 50/50 input signal, you can use it to double the frequency (
takes
> one XOR, one inverter and a ff ), and you then divide by three.
> If the input is not 50% duty cycle, you get a strangely modulated output
> frequency.
>
> Peter Alfke, presently stuck in Stockholm, until air traffic resumes...

Gives you time to visit the BlackARM guys...






Article: 34931
Subject: Re: Foundation 3.1i REINSTALLATION
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Fri, 14 Sep 2001 13:20:00 +0200
Links: << >>  << T >>  << A >>
After installing the CDs you should install SP3 before installing the
latest SP (see Answer Record #10301 at Xilinx Support). Otherwise you'll
probably get problems with the license manager.

Michael



Article: 34932
Subject: Re: Foundation 3.1i REINSTALLATION
From: "fred" <x@y.z>
Date: Fri, 14 Sep 2001 12:29:39 +0100
Links: << >>  << T >>  << A >>
I have been in a similar situation with Xilinx and AHDL where the
installation spanned two drives. The installation was a complete mess with
hanging registry entries which screwed up any attmept to re-install. My
solution was to delete all Xilinx and Aldec related files from the machine
and then manually remove all registry entries or branch with Xilinx or ahdl
in the path. IIRC, there were about 80 entries per user. It sounds scary but
the regedit search function made it straightforward - it took a morning to
recover.

I now never install applications across two drives.

Fred
ps: Just thought that this doesn't really apply to you as you have a brand
spanking new registry - but hope it helps anyway.



> "jdiaz_pr" <jdiaz_pr@excite.com> wrote in message
> news:ae1bba04.0109132034.6e95fd91@posting.google.com...
> > I got a virus that erased my C: drive, is there a way to reinstall de
> > S/W over the D: drive (yet installed) without requiring to do the
<snip>



Article: 34933
(removed)


Article: 34934
Subject: Re: Clock Multiplication
From: Paul Hardy <paul.hardy@xilinx.com>
Date: Fri, 14 Sep 2001 14:10:36 +0200
Links: << >>  << T >>  << A >>
Yes, I already realized that I gave you a recipe for division. Sorry...
Multiplication is far more difficult without a DLL or PLL ( with them, it's trivial)
If you really need a continuously running "single frequency"! output, I think it is impossible without a DLL or PLL,
which the newer FPGAs have, as you undoubtably know.
If you can cheat, and insert a clock pulse now and then at the right time, it should be quite simple, but you will
have uneven pulse spacing.

Peter Alfke, still stuck in Stockholm.
But the sun is shining now.Makes everything look less gloomy.

Sriram S wrote:

> "Chris Mc Clements" <cmcclement@computing.dundee.ac.uk> wrote in message news:<9mvos9$l4v$1@dux.dundee.ac.uk>...
>
> I wanted clock multiplication not division


Article: 34935
Subject: Re: Block RAM initialization
From: Catalin Baetoniu <catalinb@xilinx.com>
Date: Fri, 14 Sep 2001 09:08:30 -0400
Links: << >>  << T >>  << A >>
Here is a VHDL example on how to do this. The code works both for synthesis and
functional simulation, all you have to do is choose the proper library at the top
of the file.

Catalin Baetoniu

library IEEE;
use IEEE.STD_LOGIC_1164.all;

-- For Synthesys
library virtex;
use virtex.components.all;

-- For Functional Simulation
--library unisim;
--use unisim.all;

entity SBox is
  port(CLK:in STD_LOGIC;
       I:in STD_LOGIC_VECTOR(17 downto 0);
       O:out STD_LOGIC_VECTOR(31 downto 0));
end SBox;

architecture SBox of SBox is
  attribute black_box:BOOLEAN;
  component RAMB4_S8_S8
    generic(INIT_00,INIT_01,INIT_02,INIT_03,
            INIT_04,INIT_05,INIT_06,INIT_07,
            INIT_08,INIT_09,INIT_0A,INIT_0B,

INIT_0C,INIT_0D,INIT_0E,INIT_0F:BIT_VECTOR:=X"0000000000000000000000000000000000000000000000000000000000000000");

    port(CLKA:in STD_LOGIC;
         RSTA:in STD_LOGIC;
         ENA:in STD_LOGIC;
         WEA:in STD_LOGIC;
         ADDRA:in STD_LOGIC_VECTOR (8 downto 0);
         DIA:in STD_LOGIC_VECTOR (7 downto 0);
         DOA:out STD_LOGIC_VECTOR (7 downto 0);
         CLKB:in STD_LOGIC;
         RSTB:in STD_LOGIC;
         ENB:in STD_LOGIC;
         WEB:in STD_LOGIC;
         ADDRB:in STD_LOGIC_VECTOR (8 downto 0);
         DIB:in STD_LOGIC_VECTOR (7 downto 0);
         DOB:out STD_LOGIC_VECTOR (7 downto 0));
  end component;
  attribute black_box of RAMB4_S8_S8:component is TRUE;
  attribute xc_props:STRING;
  attribute xc_props of s0:label is
"INIT_00=C072A49CAFA2D4ADF04759FA7DC982CA76ABD7FE2B670130C56F6BF27B777C63,"&

"INIT_01=75B227EBE28012079A059618C323C7041531D871F1E5A534CCF73F362693FDB7,"&

"INIT_02=CF584C4A39BECB6A5BB1FC20ED00D153842FE329B3D63B52A05A6E1B1A2C8309,"&

"INIT_03=D2F3FF1021DAB6BCF5389D928F40A351A89F3C507F02F94585334D43FBAAEFD0,"&

"INIT_04=DB0B5EDE14B8EE4688902A22DC4F816073195D643D7EA7C41744975FEC130CCD,"&

"INIT_05=08AE7A65EAF4566CA94ED58D6D37C8E779E4959162ACD3C25C2406490A3A32E0,"&

"INIT_06=9E1DC186B95735610EF6034866B53E708A8BBD4B1F74DDE8C6B4A61C2E2578BA,"&

"INIT_07=16BB54B00F2D99416842E6BF0D89A18CDF2855CEE9871E9B948ED9691198F8E1,"&

"INIT_08=CBE9DEC444438E3487FF2F9B8239E37CFBD7F3819EA340BF38A53630D56A0952,"&

"INIT_09=25D18B6D49A25B76B224D92866A12E084EC3FA420B954CEE3D23C2A632947B54,"&

"INIT_0A=849D8DA75746155EDAB9EDFD5048706C92B6655DCC5CA4D41698688664F6F872,"&

"INIT_0B=6B8A130103BDAFC1020F3FCA8F1E2CD00645B3B80558E4F70AD3BC8C00ABD890,"&

"INIT_0C=6EDF751CE837F9E28535ADE72274AC9673E6B4F0CECFF297EADC674F4111913A,"&

"INIT_0D=F45ACD78FEC0DB9A2079D2C64B3E56FC1BBE18AA0E62B76F89C5291D711AF147,"&

"INIT_0E=EF9CC9939F7AE52D0D4AB519A97F51605FEC8027591012B131C7078833A8DD1F,"&

"INIT_0F=7D0C2155631469E126D677BA7E042B17619953833CBBEBC8B0F52AAE4D3BE0A0";
begin
  s0:RAMB4_S8_S8 generic
map(INIT_00=>X"C072A49CAFA2D4ADF04759FA7DC982CA76ABD7FE2B670130C56F6BF27B777C63",


INIT_01=>X"75B227EBE28012079A059618C323C7041531D871F1E5A534CCF73F362693FDB7",

INIT_02=>X"CF584C4A39BECB6A5BB1FC20ED00D153842FE329B3D63B52A05A6E1B1A2C8309",

INIT_03=>X"D2F3FF1021DAB6BCF5389D928F40A351A89F3C507F02F94585334D43FBAAEFD0",

INIT_04=>X"DB0B5EDE14B8EE4688902A22DC4F816073195D643D7EA7C41744975FEC130CCD",

INIT_05=>X"08AE7A65EAF4566CA94ED58D6D37C8E779E4959162ACD3C25C2406490A3A32E0",

INIT_06=>X"9E1DC186B95735610EF6034866B53E708A8BBD4B1F74DDE8C6B4A61C2E2578BA",

INIT_07=>X"16BB54B00F2D99416842E6BF0D89A18CDF2855CEE9871E9B948ED9691198F8E1",

INIT_08=>X"CBE9DEC444438E3487FF2F9B8239E37CFBD7F3819EA340BF38A53630D56A0952",

INIT_09=>X"25D18B6D49A25B76B224D92866A12E084EC3FA420B954CEE3D23C2A632947B54",

INIT_0A=>X"849D8DA75746155EDAB9EDFD5048706C92B6655DCC5CA4D41698688664F6F872",

INIT_0B=>X"6B8A130103BDAFC1020F3FCA8F1E2CD00645B3B80558E4F70AD3BC8C00ABD890",

INIT_0C=>X"6EDF751CE837F9E28535ADE72274AC9673E6B4F0CECFF297EADC674F4111913A",

INIT_0D=>X"F45ACD78FEC0DB9A2079D2C64B3E56FC1BBE18AA0E62B76F89C5291D711AF147",

INIT_0E=>X"EF9CC9939F7AE52D0D4AB519A97F51605FEC8027591012B131C7078833A8DD1F",

INIT_0F=>X"7D0C2155631469E126D677BA7E042B17619953833CBBEBC8B0F52AAE4D3BE0A0")
                 port map(CLKA=>CLK,
                          RSTA=>'0',
                          ENA=>'1',
                          WEA=>'0',
                          ADDRA=>I,
                          DIA=>"00000000",
                          DOA=>O(7 downto 0),
                          CLKB=>CLK,
                          RSTB=>'0',
                          ENB=>'1',
                          WEB=>'0',
                          ADDRB=>I(17 downto 9),
                          DIB=>"00000000",
                          DOB=>O(15 downto 8));
end SBox;


renaux wrote:

> Try to read the XAPP199 page 21 . Coergen use a COE file and creates a MIF
> (memory Init file ). This file is an ascii one which would be easy to creates
> in the vhdl. But I am not sure it will work on synthesis . I have the same
> problem issue and I have to try myself to solve this
>
> regards
>
> ------
> User of http://www.foorum.com/. The best tools for usenet searching.


Article: 34936
Subject: Re: configuration latency for PCI bridge in FPGA
From: "clevin1234" <clevin1234@home.com>
Date: Fri, 14 Sep 2001 13:11:48 GMT
Links: << >>  << T >>  << A >>
Matthias,

    Instead of using a Xilinx PCI core you might want to consider a
QuickLogic FPGA with a hard PCI core built into the device.  The QuickLogic
FPGA's are OTP and alive at power up so you don't have to worry about a
configuration cycle.  The other advantage is the there are no fees
associated with using the PCI cores. QuickLogic has PCI devices that support
not 32bit / 33 Mhz  Target only or Master/Target PCI applications. You can
check out the devices on the QuickLogic web site at www.quicklogic.com.


"Matthias Fuchs" <matthias.fuchs@esd-electronics.com> wrote in message
news:3BA09B96.5A7782A7@esd-electronics.com...
> Hi,
>
> we are considering about using the Xilinx PCI core in a future design.
> Because of the high prices of
> configuration PROMs we are thinking about a little uC that does the FPGA
> configuration after power on !
> This seems to be very plexible because the uC can do other things after
> booting the FPGA.
>
> The problem I see is the configuration latency. Configuring the FPGA
> through a small uCs I/O pins might be much slower than using a PROM
> solution (serial PROM or PLD/Flash-combination).
>
> Did anybody build a design with a uC configuring a PCI bridge FPGA ? How
> much time is allowed until the FPGA must be booted to be detected by the
> hosts plug and plug run ? Is there a way to extend or slow done the plug
> and play stuff and to force retrys ?
>
> Any idea ?
>
> Matthias



Article: 34937
Subject: Re: Clock Multiplication
From: Paul Hardy <paul.hardy@xilinx.com>
Date: Fri, 14 Sep 2001 15:48:20 +0200
Links: << >>  << T >>  << A >>
Here is the simpel solution:
Divide the incoming clock by 2 in one ff.
Use this ff to enable/disable a clock doubler ( one ff, one inverter, one XOR)
So the total circuit fits easily into two LUTs + FFs. Runs 100 MHz or even faster.
But you get uneven pulse spacing.

Peter Alfke
==============================
Paul Hardy wrote:

> Yes, I already realized that I gave you a recipe for division. Sorry...
> Multiplication is far more difficult without a DLL or PLL ( with them, it's trivial)
> If you really need a continuously running "single frequency"! output, I think it is impossible without a DLL or PLL,
> which the newer FPGAs have, as you undoubtably know.
> If you can cheat, and insert a clock pulse now and then at the right time, it should be quite simple, but you will
> have uneven pulse spacing.
>
> Peter Alfke, still stuck in Stockholm.
> But the sun is shining now.Makes everything look less gloomy.
>
> Sriram S wrote:
>
> > "Chris Mc Clements" <cmcclement@computing.dundee.ac.uk> wrote in message news:<9mvos9$l4v$1@dux.dundee.ac.uk>...
> >
> > I wanted clock multiplication not division


Article: 34938
Subject: Re: configuration latency for PCI bridge in FPGA
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 14 Sep 2001 07:52:05 -0700
Links: << >>  << T >>  << A >>



Matthias,

The PCI specification has 80 ms before a unit must be ready (took me all day
to find that in the spec).

If anyone else has a different interpretation of the specification (or some
user experience with resetting), it would be a service to post it here.

Austin

Matthias Fuchs wrote:

> Hi,
>
> we are considering about using the Xilinx PCI core in a future design.
> Because of the high prices of
> configuration PROMs we are thinking about a little uC that does the FPGA
> configuration after power on !
> This seems to be very plexible because the uC can do other things after
> booting the FPGA.
>
> The problem I see is the configuration latency. Configuring the FPGA
> through a small uCs I/O pins might be much slower than using a PROM
> solution (serial PROM or PLD/Flash-combination).
>
> Did anybody build a design with a uC configuring a PCI bridge FPGA ? How
> much time is allowed until the FPGA must be booted to be detected by the
> hosts plug and plug run ? Is there a way to extend or slow done the plug
> and play stuff and to force retrys ?
>
> Any idea ?
>
> Matthias




Article: 34939
Subject: Re: Using Synopsys Design Compiler to target Virtex-E FPGA
From: amey@controlnet.co.in (amey hegde)
Date: 14 Sep 2001 07:54:33 -0700
Links: << >>  << T >>  << A >>
Hi,
thanks a lot for replying.
but synlibs is not working on my PC could u send me the sldb via email?
-amey

"Ansgar Bambynek" <a.bambynek_xxx_@avm.de> wrote in message news:<3ba0c3cc$0$228$4d4ebb8e@businessnews.de.uu.net>...
> Hi Amey
> 
> you could use synlibs which is a XILINX program to get the required
> libraries. Just type in synlibs -help
> 
> To get the libraries for virtexe-6 just type
> 
> synlibs xdc_virtexe-6
> 
> the following is the result
>     link_library = {xdc_virtexe-6.db xdw_virtex.sldb}
>     target_library = {xdc_virtexe-6.db }
>     symbol_library = {virtexe.sdb}
>     define_design_lib xdw_virtex -path XilinxInstall +
> /synopsys/libraries/dw/lib/virtex
>     synthetic_library = {xdw_virtex.sldb standard.sldb}
> 
> Based on my experiences I would strongly recommend using fpga compiler II
> instead of Design Compiler or FPGA Compiler.
> If don't know if this holds true for virtexe but I got much better results
> in terms of area and speed when using FC II.
> My design was targeted for SPARTAN2
> 
> Unfortunately commands are not the same for DC and FCII so you can't just
> your synthesis scripts one by one.
> 
> HTH
> 
> Ansgar
> --
> Attention reply address is invalid.
> Please remove _xxx_
> amey hegde <amey@controlnet.co.in> schrieb in im Newsbeitrag:
> f8b003f9.0109130130.380ff99d@posting.google.com...
> > Hi,
> > In Design Compiler which db do I use to synthesize my RTL to the
> > Virtex XCV1000E-6 ?
> > Can anyone send a sample .synopsys_dc.setup file listing the target
> > library, synthetic library and symbol library?
> > I tried using xdc_virtexe-6.db as the target library with virtexe.sdb
> > as the symbol library but I am getting a large violation (about 30ns
> > violation for my 16ns period clock)
> >
> > -amey

Article: 34940
Subject: Re: A vs. X
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 14 Sep 2001 08:01:51 -0700
Links: << >>  << T >>  << A >>



Peter,

Holding down the fort here in San Jose.  We all miss you, and look forward to
your homecoming.  Don't enyoy things too much over there.

I would also remind everyone that Altera and Xilinx signed an agreement a
little while ago.  Details are on the websites of the joint statement.
Naturally Peter and I are convinced of Xilinx's superior product offering, but
that would be natural for he and I (as employees in the FPGA Products Group, or
'FPG' -- I love it when people rename things!).

The agreement took the fight out of the courts, and left it (much healthier) in
the marketplace.

Austin Lesea
FPGA Lab
ICDES
FPG
XSJ

"If I hear one more damned TLA here at HP I am going to really get mad ...."  a
quote from a manager at 24 years ago when I visited HP in Cupertino.




Article: 34941
Subject: Re: A vs. X
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Fri, 14 Sep 2001 17:34:42 +0200
Links: << >>  << T >>  << A >>
Austin Lesea a écrit :
> 
[...]
> "If I hear one more damned TLA here at HP I am going to really
> get mad ...."  a quote from a manager at 24 years ago when I
> visited HP in Cupertino.

Sorry to interrupt but I'm afraid I'm missing something so I don't enjoy
the quote. What is a TLA?

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 34942
Subject: Re: A vs. X
From: John_H <johnhandwork@mail.com>
Date: Fri, 14 Sep 2001 15:46:36 GMT
Links: << >>  << T >>  << A >>
TLA:  Three Letter Achronym for "Three Letter Achronym"

(I'm imagining newsgroup lag allows this to be one of many answers)


Nicolas Matringe wrote:

> Sorry to interrupt but I'm afraid I'm missing something so I don't enjoy
> the quote. What is a TLA?


Article: 34943
Subject: Re: A vs. X
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 14 Sep 2001 09:15:13 -0700
Links: << >>  << T >>  << A >>
Nicolas,

Excusez-moi.

TLA = three letter acronym, as in "FYI" = "for your interest", or any other
three letter representation, or short hand, of a multi-word phrase.

There are those here (English speakers) who also did not "get" it, so I
understand the confusion.

Que'es que c'est TLA en Francais?  Acronyme à trois mots? ATM?

Quand j'étais à Paris en 1977, j'ai travaillé pour Sybex.    J'ai travaillé
à un dictionnaire technique Anglais-Français.  Dans une classe, j'ai utilisé
le mot pour "carry bit" en français.  Personne n'ont su de ce que je
parlais.

Aujourd'hui, avez-vous un mot français que vous utilisez pour "carry-bit"?
Je ne puis pas me rappeler.

Austin


Nicolas Matringe wrote:

> Austin Lesea a écrit :
> >
> [...]
> > "If I hear one more damned TLA here at HP I am going to really
> > get mad ...."  a quote from a manager at 24 years ago when I
> > visited HP in Cupertino.
>
> Sorry to interrupt but I'm afraid I'm missing something so I don't enjoy
> the quote. What is a TLA?
>
> --
> Nicolas MATRINGE           IPricot European Headquarters
> Conception electronique    10-12 Avenue de Verdun
> Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
> Fax +33 1 46 52 53 01      http://www.IPricot.com/


Article: 34944
Subject: using BlockRAM
From: Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore>
Date: Fri, 14 Sep 2001 19:41:50 +0200
Links: << >>  << T >>  << A >>
Hi!

I get large delays, when I use BlockRAM.
Please have a look at the following code:

library IEEE;
use IEEE.std_logic_1164.all;

entity ram16 is
        port (
                enable: in STD_LOGIC;
                writeEnable: in STD_LOGIC;
                address: in std_logic_vector(7 downto 0);

                -- in /out data
                dq: in STD_LOGIC_VECTOR (15 downto 0);
                dqOut: out STD_LOGIC_VECTOR (15 downto 0);

                -- global
                reset: in STD_LOGIC;
                clock: in STD_LOGIC
        );
end ram16;

architecture ram16_arch of ram16 is
        SIGNAL clockInverted: std_logic;
        component RAMB4_S16
                port(
                        we,en,rst, clk: in std_logic;
                        addr: in std_logic_vector (7 downto 0);
                        di: in std_logic_vector (15 downto 0);
                        do: out std_logic_vector (15 downto 0)
                );
        end component; -- RAMB4_S16
begin
        clockInverted <= not(clock);

                ram0: RAMB4_S16
                port map (
                        we => writeEnable,
                        en => enable,
                        rst => reset,
                        clk => clockInverted,
                        addr(7 downto 0) => address(7 downto 0),
                        di(15 downto 0) => dq(15 downto 0),
                        do(15 downto 0) => dqOut(15 downto 0)
                );

end ram16_arch;

The response time in the verification stage is 20ns. This is what the
static analysis says:

================================================================================

Timing constraint: PATH "PATHFILTERS" = FROM TIMEGRP "SOURCES" TO
TIMEGRP
"DESTINATIONS" ;
 44 items analyzed, 0 timing errors detected.
 Maximum delay is  11.586ns.
--------------------------------------------------------------------------------

Delay:    11.586ns ram0 to dqOut<11>

Path ram0 to dqOut<11> contains 2 levels of logic:
Path starting from Comp: RAMB4_R3C0.CLKA (from N_clock)
To                   Delay type         Delay(ns)  Physical Resource
                                                   Logical Resource(s)
-------------------------------------------------  --------
RAMB4_R3C0.DOA11     Tbcko                 3.310R  ram0
                                                   ram0.A
H5.O                 net (fanout=1)        3.489R  N_dqOut<11>
H5.PAD               Tioop                 4.787R  dqOut<11>
                                                   C_dqOut<11>
                                                   dqOut<11>.PAD
-------------------------------------------------
Total (8.097ns logic, 3.489ns route)      11.586ns
      (69.9% logic, 30.1% route)

--------------------------------------------------------------------------------



All constraints were met.

My questions are:

 * Where does the large delay of 20ns come from? The new address should
be read in 5ns
     after the rising edge of the clock, then it should take about 5ns
until the data
     should be available at the output. Why 11.586ns from the RAM to the
output pad?

 * How can I optimize the paths through the FPGA? I played around with
timing constraints,
     but I haven't had any luck so far. Do I use timing constraints just
to know if the are
     fulfilled or to tell the PAR what ways to optimize?

I'm about to write a SDRAM interface. I only have 30ns from a read
command until the
data from the BlockRAM must be stable at the output. My state machine
needs 10ns to
apply the read address to the BlockRAM. That leaves 20ns for the read
delay. The
window is very tight, I want to optimze it is much as I can.

Thanks a LOT for your help!

-jc-


Article: 34945
Subject: Re: A vs. X
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Fri, 14 Sep 2001 21:58:49 +0200
Links: << >>  << T >>  << A >>

[sorry for the non French speakers here but I couldn't resist replying in
French to Austin]

"Austin Lesea" <austin.lesea@xilinx.com> wrote
> Nicolas,
>
> Excusez-moi.
>
> TLA = three letter acronym, as in "FYI" = "for your interest", or any
other
> three letter representation, or short hand, of a multi-word phrase.
>
> There are those here (English speakers) who also did not "get" it, so I
> understand the confusion.
>
> Que'es que c'est TLA en Francais?  Acronyme à trois mots? ATM?
>
> Quand j'étais à Paris en 1977, j'ai travaillé pour Sybex.    J'ai
travaillé
> à un dictionnaire technique Anglais-Français.  Dans une classe, j'ai
utilisé
> le mot pour "carry bit" en français.  Personne n'ont su de ce que je
> parlais.
>
> Aujourd'hui, avez-vous un mot français que vous utilisez pour "carry-bit"?
> Je ne puis pas me rappeler.

C'est bit de retenue. Bravo pour l'effort en tout cas!
Pour ce genre de termes techniques, vous pouvez aller chercher dans le
dictionnaire terminologique Français/Anglais de nos amis du Québec:
http://www.granddictionnaire.com

Marc Battyani

> Nicolas Matringe wrote:
>
> > Austin Lesea a écrit :
> > >
> > [...]
> > > "If I hear one more damned TLA here at HP I am going to really
> > > get mad ...."  a quote from a manager at 24 years ago when I
> > > visited HP in Cupertino.
> >
> > Sorry to interrupt but I'm afraid I'm missing something so I don't enjoy
> > the quote. What is a TLA?




Article: 34946
Subject: Re: A vs. X
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 14 Sep 2001 15:59:01 -0700
Links: << >>  << T >>  << A >>
Merveilleux!

Thank you.  I always wondered how anyone would ever translate the babel of
techno-jargon that Silicon Valley produces.  The web succeeds again!

Austin

Marc Battyani wrote:

> [sorry for the non French speakers here but I couldn't resist replying in
> French to Austin]
>
> "Austin Lesea" <austin.lesea@xilinx.com> wrote
> > Nicolas,
> >
> > Excusez-moi.
> >
> > TLA = three letter acronym, as in "FYI" = "for your interest", or any
> other
> > three letter representation, or short hand, of a multi-word phrase.
> >
> > There are those here (English speakers) who also did not "get" it, so I
> > understand the confusion.
> >
> > Que'es que c'est TLA en Francais?  Acronyme à trois mots? ATM?
> >
> > Quand j'étais à Paris en 1977, j'ai travaillé pour Sybex.    J'ai
> travaillé
> > à un dictionnaire technique Anglais-Français.  Dans une classe, j'ai
> utilisé
> > le mot pour "carry bit" en français.  Personne n'ont su de ce que je
> > parlais.
> >
> > Aujourd'hui, avez-vous un mot français que vous utilisez pour "carry-bit"?
> > Je ne puis pas me rappeler.
>
> C'est bit de retenue. Bravo pour l'effort en tout cas!
> Pour ce genre de termes techniques, vous pouvez aller chercher dans le
> dictionnaire terminologique Français/Anglais de nos amis du Québec:
> http://www.granddictionnaire.com
>
> Marc Battyani
>
> > Nicolas Matringe wrote:
> >
> > > Austin Lesea a écrit :
> > > >
> > > [...]
> > > > "If I hear one more damned TLA here at HP I am going to really
> > > > get mad ...."  a quote from a manager at 24 years ago when I
> > > > visited HP in Cupertino.
> > >
> > > Sorry to interrupt but I'm afraid I'm missing something so I don't enjoy
> > > the quote. What is a TLA?


Article: 34947
Subject: Re: Wanted: ISA bus implementation for Xilinx
From: steen_xxxtech@yahoo.com (Steen)
Date: 14 Sep 2001 17:10:01 -0700
Links: << >>  << T >>  << A >>
You might also want to check http://www.tech-forge.com.  My MS thesis
shows one (of many probable ways) to connect an Altera 10K20 to the
ISA bus.

-Steen
(To respond, remove xxx from email)

cnspy <cnspy@sohu.com> wrote in message news:<556gpt4vgrodk7c1uv0rmerm004j2a7v8a@4ax.com>...
> A long time before, I saw a free IP core for ISA. But I can not
> remember the URL and I don't know the kind of it. 
> You can try to look it up in google
> On 18 Apr 2001 18:46:23 GMT, ernstegon.NO@SPAM.freeze.com (Ernst
> Rattenhuber) wrote:
> 
> >I need some kind of IP module that implements an ISA bus interface. It could be 
> >in the form of a "black box" or in the form of synthesizable VHDL code. I 
> >believe Xilinx used to have something along those lines, but it seems to have 
> >been discontinued. Now they only offer a "PCI Development Kit" for the PCI bus, 
> >and it's rather expensive too (~9000 US dollars).
> >
> >My needs are not so great in terms of performance, and I'm not prepared to fork 
> >out that kind of money. So if someone could suggest an ISA solution that could 
> >be purchased for 1000 dollars or less, I'd be grateful.
> >
> >I need it for the design of a PC/104 board that is to be the interface between 
> >measurement devices and an embedded PC. The measurement devices use a 
> >proprietary, synchronous serial protocol. I'm planning to implement the whole 
> >thing in a single FPGA, preferably a Spartan-II device.
> >
> >TIA,
> >
> >Ernst Rattenhuber
> >
> >
> >P.S. Email replies can be sent to the address in my header minus the obvious 
> >spam deterrent parts.

Article: 34948
Subject: Re: Wanted: ISA bus implementation for Xilinx
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Fri, 14 Sep 2001 18:08:32 -0700
Links: << >>  << T >>  << A >>

Hello,

If you go to www.xilinx.com, and do a search for "ISA",
you will get this as one of the first hits:

http://www.xilinx.com/appnotes/plugplay.pdf

The following file has a reduced example, which does not
implement plug and play.  It was also one of the first
hits:

http://www.xilinx.com/appnotes/bus_conf.pdf

Both of these references are done in schematic, but that
doesn't stop you from translating them into Verilog or
VHDL if that is what you want to do.  There is a ton of
information out there on this topic; a simple interface
to read/write registers is trivial.

If, after you read this material, you are still willing
to pay $1,000 for such an interface, I would certainly
consider moonlighting for you.  :)

Hope that helps,
Eric Crabill

Article: 34949
Subject: Re: Block RAM initialization
From: hamish@cloud.net.au
Date: Sat, 15 Sep 2001 02:46:41 GMT
Links: << >>  << T >>  << A >>
Catalin Baetoniu <catalinb@xilinx.com> wrote:
> architecture SBox of SBox is
>  attribute black_box:BOOLEAN;
>  component RAMB4_S8_S8
>    generic(INIT_00,INIT_01,INIT_02,INIT_03,
>            INIT_04,INIT_05,INIT_06,INIT_07,
>            INIT_08,INIT_09,INIT_0A,INIT_0B,

> INIT_0C,INIT_0D,INIT_0E,INIT_0F:BIT_VECTOR:=X"0000000000000000000000000000000000000000000000000000000000000000");

You might need --synthesis translate_off/on around the generics, with
Synplify at least. Otherwise each instantiation will have a different
component name (RAMB4_S8_S8Z0, ..Z1, etc) because of the generics, and
ngdbuild will not recognise these components as primitives.

That's why UNISIM is full of translate off/ons.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>



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