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Messages from 34950

Article: 34950
Subject: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
From: "pete dudley" <padudle@spinn.net>
Date: Fri, 14 Sep 2001 22:38:10 -0600
Links: << >>  << T >>  << A >>
Xilinx FAE Jason Moore helped me on this one. You can directly instantiate a
MULT18X18S to get the Synchronous multiplier. The core generator does not
give you that primitive. Speed files are still bouncing around on the
Tmultck parameter but they should run 125MHz especially since I only need
10x18 out of them.

--
Pete Dudley

Arroyo Grande Systems

"pete dudley" <padudle@spinn.net> wrote in message
news:tpqon9s22vare9@corp.supernews.com...
> Hello All,
>
> Does anyone know whether there is really an internal pipeline register
> inside the Virtex II embedded multiplier?
>
> I have an application that is very multiplier intensive and I need to run
at
> 125MHz. Without internal pipelining it is just about impossible to meet
this
> clock rate. I have been told there is a register inside those multipliers
> but that they are not supported in the 3.1i tools. I received my 4.1i
tools
> today and tried to turn on the pipeline register by specifying maximum
> pipelining in the core generator but the timing report still  indicates no
> internal pipelining.
>
> When I look at the multiplier blocks using FPGA Editor I can see that it
has
> a clock input. What's the story?
>
>   Thanks,
>
> --
> Pete Dudley
>
> Arroyo Grande Systems
>
>
>



Article: 34951
Subject: Altera 10K shortage
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Sat, 15 Sep 2001 12:39:01 +0100
Links: << >>  << T >>  << A >>
Altera 10K10 and 10K50 parts seem difficult to find. Does anyone know why?

Leon
--
Leon Heller, G1HSM leon_heller@hotmail.con
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com





Article: 34952
Subject: Carry Chain: Delay
From: vivek <vivek.sood@st.com>
Date: Sat, 15 Sep 2001 06:13:56 -0700
Links: << >>  << T >>  << A >>
When implementing a two bit adder in the same slice of the Virtex CLB , I found that the F-LUT input to Cout delay(final Cout of the slice ) was less than the G-LUT input to Cout delay(final Cout delay of the same slice), while if one looks at the CLB structure it is seen that the number of muxes encountered from the G-LUT input  to Cout is less than those encountered form the F-LUT input to Cout.So I should get the F-LUT input to Cout delay more while I'am getting this less !!!Can anybody explain this conundrum!!

Thanx in advance

Article: 34953
Subject: Re: A vs. X
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sat, 15 Sep 2001 20:22:28 +0100
Links: << >>  << T >>  << A >>


Austin Lesea wrote:

> Merveilleux!
>
> Thank you.  I always wondered how anyone would ever translate the babel of
> techno-jargon that Silicon Valley produces.  The web succeeds again!
>
> Austin
>
> Marc Battyani wrote:
>
> > [sorry for the non French speakers here but I couldn't resist replying in
> > French to Austin]
> >
> > "Austin Lesea" <austin.lesea@xilinx.com> wrote
> > > Nicolas,
> > >
> > > Excusez-moi.
> > >
> > > TLA = three letter acronym, as in "FYI" = "for your interest", or any
> > other
> > > three letter representation, or short hand, of a multi-word phrase.
> > >
> > > There are those here (English speakers) who also did not "get" it, so I
> > > understand the confusion.
> > >
> > > Que'es que c'est TLA en Francais?  Acronyme à trois mots? ATM?
> > >
> > > Quand j'étais à Paris en 1977, j'ai travaillé pour Sybex.    J'ai
> > travaillé
> > > à un dictionnaire technique Anglais-Français.  Dans une classe, j'ai
> > utilisé
> > > le mot pour "carry bit" en français.  Personne n'ont su de ce que je
> > > parlais.
> > >
> > > Aujourd'hui, avez-vous un mot français que vous utilisez pour "carry-bit"?
> > > Je ne puis pas me rappeler.
> >
> > C'est bit de retenue. Bravo pour l'effort en tout cas!
> > Pour ce genre de termes techniques, vous pouvez aller chercher dans le
> > dictionnaire terminologique Français/Anglais de nos amis du Québec:
> > http://www.granddictionnaire.com
> >
> > Marc Battyani
> >
> >

Est'ce que il y a une traduction pour ``bit'' lui-meme ?



Article: 34954
Subject: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 15 Sep 2001 20:11:54 GMT
Links: << >>  << T >>  << A >>
To get the 125 MHz, you'll need to use the pipeline registers.  With 3.1 that
means using FPGA editor.  You'll also need to precede and follow the multiplier
immediately with CLB registers.  You may find you need to place those added
registers by hand so that they are in the rignt places to get on the direct
connects to the multiplier.

pete dudley wrote:

> Xilinx FAE Jason Moore helped me on this one. You can directly instantiate a
> MULT18X18S to get the Synchronous multiplier. The core generator does not
> give you that primitive. Speed files are still bouncing around on the
> Tmultck parameter but they should run 125MHz especially since I only need
> 10x18 out of them.
>
> --
> Pete Dudley
>
> Arroyo Grande Systems
>
> "pete dudley" <padudle@spinn.net> wrote in message
> news:tpqon9s22vare9@corp.supernews.com...
> > Hello All,
> >
> > Does anyone know whether there is really an internal pipeline register
> > inside the Virtex II embedded multiplier?
> >
> > I have an application that is very multiplier intensive and I need to run
> at
> > 125MHz. Without internal pipelining it is just about impossible to meet
> this
> > clock rate. I have been told there is a register inside those multipliers
> > but that they are not supported in the 3.1i tools. I received my 4.1i
> tools
> > today and tried to turn on the pipeline register by specifying maximum
> > pipelining in the core generator but the timing report still  indicates no
> > internal pipelining.
> >
> > When I look at the multiplier blocks using FPGA Editor I can see that it
> has
> > a clock input. What's the story?
> >
> >   Thanks,
> >
> > --
> > Pete Dudley
> >
> > Arroyo Grande Systems
> >
> >
> >

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34955
Subject: Re: A vs. X
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Sat, 15 Sep 2001 22:13:39 +0200
Links: << >>  << T >>  << A >>

"Rick Filipkiewicz" <rick@algor.co.uk> wrote
>
 > Austin Lesea wrote:
>
> > Merveilleux!
> >
> > Thank you.  I always wondered how anyone would ever translate the babel
of
> > techno-jargon that Silicon Valley produces.  The web succeeds again!
> >
> > Austin
> >
> > Marc Battyani wrote:
> >
> > > [sorry for the non French speakers here but I couldn't resist replying
in
> > > French to Austin]
> > >
> > > "Austin Lesea" <austin.lesea@xilinx.com> wrote
> > > > Nicolas,
> > > >
> > > > Excusez-moi.
> > > >
> > > > TLA = three letter acronym, as in "FYI" = "for your interest", or
any
> > > other
> > > > three letter representation, or short hand, of a multi-word phrase.
> > > >
> > > > There are those here (English speakers) who also did not "get" it,
so I
> > > > understand the confusion.
> > > >
> > > > Que'es que c'est TLA en Francais?  Acronyme à trois mots? ATM?
> > > >
> > > > Quand j'étais à Paris en 1977, j'ai travaillé pour Sybex.    J'ai
> > > travaillé
> > > > à un dictionnaire technique Anglais-Français.  Dans une classe, j'ai
> > > utilisé
> > > > le mot pour "carry bit" en français.  Personne n'ont su de ce que je
> > > > parlais.
> > > >
> > > > Aujourd'hui, avez-vous un mot français que vous utilisez pour
"carry-bit"?
> > > > Je ne puis pas me rappeler.
> > >
> > > C'est bit de retenue. Bravo pour l'effort en tout cas!
> > > Pour ce genre de termes techniques, vous pouvez aller chercher dans le
> > > dictionnaire terminologique Français/Anglais de nos amis du Québec:
> > > http://www.granddictionnaire.com
> > >
>
> Est'ce que il y a une traduction pour ``bit'' lui-meme ?

The number of French speaking people in this newsgroup is amazing...
"Bit" se dit "bit" en français (nom masculin : un bit). On a pris le mot
anglais. Sinon il faut dire élément binaire ou chiffre binaire.

Marc




Article: 34956
Subject: Problems with Xilinx App Note 223 (UART with Internal 16-Byte Buffer)
From: "llandre" <aaa@aaa.aaa>
Date: Sun, 16 Sep 2001 09:29:34 GMT
Links: << >>  << T >>  << A >>
I tried to use the macors described in App Note 223.
I istantiated them in a VirtexE FPGA with WebPACK 3.3.
I made a loopback connection inside the FPGA and I performed some
tests with a simple Visual Basic application. It sends a block of
4096 bytes through the serial port and verifies the match with the
received data (baud rate: 115200bps). I used a 1.843200 MHz quartz
as baud generator.
I noted that usually one or two bytes out of 4096 don't come back.

Anybody experiences similar problems?

Thanks in advance.


--
llandre
 e-mail : andmars -at- tin -dot- it
 web    : http://www.dei.unipd.it/~patch








Article: 34957
Subject: Virtex-2 availability
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 16 Sep 2001 17:19:57 +0100
Links: << >>  << T >>  << A >>

Has anyone seen the XC2V1500/2000 parts yet or have any idea when they
are due to hit the streets ?



Article: 34958
Subject: Re: configuration latency for PCI bridge in FPGA
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 16 Sep 2001 10:59:19 -0700
Links: << >>  << T >>  << A >>
Where were you able to find the 80 ms number?
PCI Local Bus Specification Revision 2.2 Page 128 and Page 135 seems
to mention Trst (Reset active time after power stable) to be asserted
for a minimum of 1 ms during when PWR_GOOD signal (not a part of the
PCI signals. Exists in IBM-PC/AT architecture as an onboard signal) is
still deasserted.
According the same PCI specification on Page 135, the PWR_GOOD signal
is typically asserted for 100 ms, but that number seems to be
implementation specific.
Does anyone know how to calculate the time it takes to program 
Spartan II or Virtex I/-E/II part during power-up?




Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)




Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3BA21995.63797EB9@xilinx.com>...
> Matthias,
> 
> The PCI specification has 80 ms before a unit must be ready (took me all day
> to find that in the spec).
> 
> If anyone else has a different interpretation of the specification (or some
> user experience with resetting), it would be a service to post it here.
> 
> Austin
> 
> Matthias Fuchs wrote:
> 
> > Hi,
> >
> > we are considering about using the Xilinx PCI core in a future design.
> > Because of the high prices of
> > configuration PROMs we are thinking about a little uC that does the FPGA
> > configuration after power on !
> > This seems to be very plexible because the uC can do other things after
> > booting the FPGA.
> >
> > The problem I see is the configuration latency. Configuring the FPGA
> > through a small uCs I/O pins might be much slower than using a PROM
> > solution (serial PROM or PLD/Flash-combination).
> >
> > Did anybody build a design with a uC configuring a PCI bridge FPGA ? How
> > much time is allowed until the FPGA must be booted to be detected by the
> > hosts plug and plug run ? Is there a way to extend or slow done the plug
> > and play stuff and to force retrys ?
> >
> > Any idea ?
> >
> > Matthias
> 
> --

Article: 34959
(removed)


Article: 34960
Subject: INIT attribute of SRL16E
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 17 Sep 2001 01:06:42 GMT
Links: << >>  << T >>  << A >>
Hi,

I have try the followings in my VHDL code:

....
attribute       INIT :  string; 
attribute       INIT    of      REG_W:  label is "0000000000011111";

begin
....

but the synopsys dc synthsis tools still post the following error:

Warning: Attribute INIT not supported for synthesis  on line 125  (VHDL-2040)
Warning: Attribute INIT not supported for synthesis  on line 126  (VHDL-2040)
...

where 125 is the second line with label

what should I do? help me please. thanks in advance!

---- Brittle

Article: 34961
Subject: Re: ISE 4.1
From: "Andrew Dyer" <adyer@enteract.com>
Date: Mon, 17 Sep 2001 05:11:48 GMT
Links: << >>  << T >>  << A >>

"Andrew Dyer" <adyer@enteract.com> wrote in message
news:WeBn7.56903$xb.30261138@news1.mntp1.il.home.com...
>
> "David Wright" <dwright@srtorque.com> wrote in message
> news:4S3m7.232735$NK1.21400208@bin3.nnrp.aus1.giganews.com...
> > Xilinx's ISE 4.1 sounds promising.  After talking to my local Xilinx
> > representative, it should be available shortly.  My current project is
> 2300
> > lines of untested VHDL code including a small test vector.  The WebPack
> has
> > a limit of 500 lines.
> >
> > I was assured the ISE 4.1 was all that I might need to do my design.
> > However,  I am skeptical as to the adequacy of the simulator.  As I
> learned
> > from past experience with Cypress and Altera, test and verification are
of
> > key importance to a design.
> >
>
> I tried installing it today at work - (someone had to be first...)
>
> Beware if you have a machine with an Athlon CPU.  There are problems
> with "some" Athlon boards.  I have a 1.1 GHz Athlon on an ASUS mobo
> with 768 Mb of Micron memory running Win 2000 SP2 and I was getting
> lockups running ngdbuild that required a hard reset.  The system is
> otherwise
> very solid running Modelsim, older Xilinx tools, Foundation express, etc.
>
>  Fortunately I didn't uninstall my old tools, just installed the 4.1i
stuff
> in a new
> directory and changed the %XILINX% environement variable.
>
> My advice is to wait for a few service packs to go by unless you want to
be
> a guinea pig like me :-)
>

I received word back from Xilinx that they did have a problem with Athlon
CPUs and believe
they have fixed the problem with the new service pack.

Today I upgraded my 4.1i installation to service pack 1 and managed to get
one run of  'par'
before I had to leave for home with no crashes, so things are looking up on
that front.




Article: 34962
Subject: Re: Virtex-2 availability
From: Jonas Weiss <jweiss@kontronmedical.ch>
Date: Mon, 17 Sep 2001 08:50:06 +0200
Links: << >>  << T >>  << A >>
According to the Xilinx roadmap they should be available in 2002.
JW

Rick Filipkiewicz wrote:

> Has anyone seen the XC2V1500/2000 parts yet or have any idea when they
> are due to hit the streets ?


Article: 34963
Subject: Re: using BlockRAM
From: lennart <lennartheijnen@hotmail.com>
Date: Sun, 16 Sep 2001 23:50:59 -0700
Links: << >>  << T >>  << A >>
why do you invert the clock signal? It looks like causes a great deal of delay.

lennart

Article: 34964
Subject: Re: INIT attribute of SRL16E
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 17 Sep 2001 07:13:48 GMT
Links: << >>  << T >>  << A >>
fogot to say that:
The code can run correct in FPGA Express Win version,
but I want to make it work for design compiler under SunOS.
I know that I can specify the attribute in dc script but
should it be a better way to only modify the VHDL codes?

---- Brittle


Article: 34965
Subject: Re: A vs. X
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Mon, 17 Sep 2001 09:48:05 +0200
Links: << >>  << T >>  << A >>
Sorry for jumping late in the discussion, I was already home when Austin
posted last friday :o)


Marc Battyani a écrit :
> 
> The number of French speaking people in this newsgroup is
> amazing...

I don't remember of Rick speaking french... I suppose my english is
better than his french :o)

To Austin: I don't know of any french equivalent of TLA. A translated
equivalent could be ATL (Acronyme en Trois Lettres) but I've never heard
it.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 34966
Subject: Re: Altera 10K shortage
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 17 Sep 2001 09:08:00 +0100
Links: << >>  << T >>  << A >>
"Leon Heller" <leon_heller@hotmail.com> writes:

> Altera 10K10 and 10K50 parts seem difficult to find. Does anyone know
> why?
> 

Possibly because they're very old - in semiconductor terms :-)

EBV (http://www.ebv.com/) have 10K10s and 50s in stock in some packages and
mainly industrial temp spec, which may be no use to you...

HTH<
Martin

-- 
martin.j.thompson@trw.com
TRW Automotive Technical Centre, Solihull, UK

Article: 34967
Subject: Altera survey
From: Jon <jschneider@cix.ceeowe.ewekay>
Date: 17 Sep 2001 10:07:07 +0100
Links: << >>  << T >>  << A >>
Of those who took the trouble to take part in their survey some months ago
how many of you actually got the promised Acex evaluation board ?

        Jon

Article: 34968
Subject: xilinx prom readback with jtag
From: "Jerre" <?@mail.com>
Date: Mon, 17 Sep 2001 09:24:00 GMT
Links: << >>  << T >>  << A >>
We have here a xilinx prom programmed through JTAG with working code.  The
only problem is that we don't know anymore what version of the code is in
there.  Stupid problem but it is the fact.  We know that through the JTAG
system it is possible to read back the contents of a prom into the .mcs or
.exo format. However this doesn't give us any infomation about the date when
it was implemented or formed.  You can also verify the prom file with
another one but considering the amount of prom files we have it would take
us a huge time to find it back.

Is there any other way to identify the code(e.g. through date)? When code is
implemented into a prom has it some ID or is there nothing but pure
functional information?

thanx in advance. J.





Article: 34969
Subject: Re: using BlockRAM
From: Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore>
Date: Mon, 17 Sep 2001 12:11:08 +0200
Links: << >>  << T >>  << A >>
lennart wrote:

> why do you invert the clock signal? It looks like causes a great deal of delay.
>
> lennart

The doc of the spartan-II (DS001-2 v2.1 march 5, 2001. fig.32 page 28)
indicates that t_BACK and t_BDCK (address befor clock and data befor clock)
must be larger than zero. In doc DS001-3 v2.4 August 28, 2001,page 17
"block ram switching charateristics" these times are stated
are specified with 1.4ns. The clock I plan to use has a frequency of
100MHz. When I have the BlockRAM triggerd on the falling edge
of the clock, t_Back and t_BDCK result in 5ns.
Do you think I should should have it triggerd on the rising edge
and use the ucf file to gaurantee t_BACK and t_BDCK?

I just tested the following code with out the inversion of the clock.
It seems to work. But the problem remains the same. I have a delay
of 11.78ns from the output of the RAM to the output pad.
Is there a way to optimze the routing process? I have to get rid
of this delay. First of all I still don't get why 11.882 ns. It says 68.1%
is logic. This is the worst case in the design. In a better case I get:


Total (8.097ns logic, 1.646ns route)       9.743ns
      (83.1% logic, 16.9% route)

This means it is not really a routing problem (1.646ns are fine with me).
Are the output pads clocked and could this be the place for optimizing
it?


Thanks for your help Lennart!
-jc-

P.S.:
This is the new code and the static timing analysis:

library IEEE;
use IEEE.std_logic_1164.all;

entity RAM64 is
        port (
                enable: in STD_LOGIC;
                writeEnable: in STD_LOGIC;
                address: in std_logic_vector(9 downto 0);

                -- in /out data
                dq: in STD_LOGIC_VECTOR (15 downto 0);
                dqOut: out STD_LOGIC_VECTOR (63 downto 0);

                -- global
                reset: in STD_LOGIC;
                clock: in STD_LOGIC
        );
end RAM64;

architecture RAM64_arch of RAM64 is
        SIGNAL writeEnableSRAM0: std_logic;
        SIGNAL writeEnableSRAM1: std_logic;
        SIGNAL writeEnableSRAM2: std_logic;
        SIGNAL writeEnableSRAM3: std_logic;
        component RAMB4_S16
                port(
                        we,en,rst, clk: in std_logic;
                        addr: in std_logic_vector (7 downto 0);
                        di: in std_logic_vector (15 downto 0);
                        do: out std_logic_vector (15 downto 0)
                );
        end component; -- RAMB4_S16
begin
        writeEnableSRAM0 <= '1' when ((writeEnable = '1') and (address(1
downto 0) = b"00")) else '0';
        writeEnableSRAM1 <= '1' when ((writeEnable = '1') and (address(1
downto 0) = b"01")) else '0';
        writeEnableSRAM2 <= '1' when ((writeEnable = '1') and (address(1
downto 0) = b"10")) else '0';
        writeEnableSRAM3 <= '1' when ((writeEnable = '1') and (address(1
downto 0) = b"11")) else '0';

                ram0: RAMB4_S16
                port map (
                        we => writeEnableSRAM0,
                        en => enable,
                        rst => reset,
                        clk => clock,
                        --addr => addressInternal,
                        addr(7 downto 0) => address(9 downto 2),
                        di(15 downto 0) => dq(15 downto 0),
                        do(15 downto 0) => dqOut(15 downto 0)
                );
        ram1: RAMB4_S16
                port map (
                        we => writeEnableSRAM1,
                        en => enable,
                        rst => reset,
                        clk => clock,
                        addr(7 downto 0) => address(9 downto 2),
                        di(15 downto 0) => dq(15 downto 0),
                        do(15 downto 0) => dqOut(31 downto 16)
                );
        ram2: RAMB4_S16
                port map (
                        we => writeEnableSRAM2,
                        en => enable,
                        rst => reset,
                        clk => clock,
                        addr(7 downto 0) => address(9 downto 2),
                        di(15 downto 0) => dq(15 downto 0),
                        do(15 downto 0) => dqOut(47 downto 32)
                );
        ram3: RAMB4_S16
                port map (
                        we => writeEnableSRAM3,
                        en => enable,
                        rst => reset,
                        clk => clock,
                        addr(7 downto 0) => address(9 downto 2),
                        di(15 downto 0) => dq(15 downto 0),
                        do(15 downto 0) => dqOut(63 downto 48)
                );

end RAM64_arch;

######################
================================================================================
Timing constraint: PATH "PATHFILTERS" = FROM TIMEGRP "SOURCES" TO TIMEGRP
"DESTINATIONS" ;
 184 items analyzed, 0 timing errors detected.
 Maximum delay is  11.882ns.
--------------------------------------------------------------------------------
Delay:    11.882ns ram3 to dqOut<63>

Path ram3 to dqOut<63> contains 2 levels of logic:
Path starting from Comp: RAMB4_R0C0.CLKA (from clock_BUFGPed)
To                   Delay type         Delay(ns)  Physical Resource
                                                   Logical Resource(s)
-------------------------------------------------  --------
RAMB4_R0C0.DOA15     Tbcko                 3.310R  ram3
                                                   ram3.A
A3.O                 net (fanout=1)        3.785R  N_dqOut<63>
A3.PAD               Tioop                 4.787R  dqOut<63>
                                                   C_dqOut<63>
                                                   dqOut<63>.PAD
-------------------------------------------------
Total (8.097ns logic, 3.785ns route)      11.882ns
      (68.1% logic, 31.9% route)


Article: 34970
Subject: Re: INIT attribute of SRL16E
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Mon, 17 Sep 2001 11:23:15 +0100
Links: << >>  << T >>  << A >>
Assuming the INIT attribute is the one you want (check in the
Xilinx Libraries guide), this looks like a problem with DC.

Do you have access to Synopsys FPGA Express?  Even better
would be Synplicity or Leonardo.  Or the Xilinx compiler.


<khtsoi@pc90026.cse.cuhk.edu.hk> wrote in message
news:9o3ib2$dd0$1@eng-ser1.erg.cuhk.edu.hk...
> Hi,
>
> I have try the followings in my VHDL code:
>
> ....
> attribute       INIT :  string;
> attribute       INIT    of      REG_W:  label is "0000000000011111";
>
> begin
> ....
>
> but the synopsys dc synthsis tools still post the following error:
>
> Warning: Attribute INIT not supported for synthesis  on line 125  (VHDL-2040)
> Warning: Attribute INIT not supported for synthesis  on line 126  (VHDL-2040)
> ...
>
> where 125 is the second line with label
>
> what should I do? help me please. thanks in advance!
>
> ---- Brittle



Article: 34971
Subject: how to simulate virtex components?
From: "Sebastian" <novalid@ress>
Date: Mon, 17 Sep 2001 14:05:19 +0200
Links: << >>  << T >>  << A >>
Hi Group

A question regarding the Virtex-2:
How to simulate the FPGA's special feature 'components' (such as embedded
multipliers and on-chip memory)?

To get a first impression of my vhdl's correctness, i want to do a
functional simulation of my design containing this kind of virtex
components. How to do this?

thanx in advance,
regards,
Sebastian


example:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library virtex;
use virtex.components.all;
library synplify;
use synplify.attributes.all;

entity matrix3x3 is
  port ( A, B, C: in std_logic_vector(11 downto 0);
        CLK, RST: in std_logic;
            CWEL: in std_logic_vector(1 downto 0);
      KA, KB, KC: in std_logic_vector(9 downto 0);
         X, Y, Z: out std_logic_vector(11 downto 0));
end matrix3x3 ;

architecture model of matrix3x3 is

component MULT18X18
port(
A,B: in std_logic_vector (17 downto 0);
P: out std_logic_vector (35 downto 0));
end component;



Article: 34972
Subject: Re: how to simulate virtex components?
From: Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore>
Date: Mon, 17 Sep 2001 14:49:34 +0200
Links: << >>  << T >>  << A >>
Sebastian wrote:

> How to simulate the FPGA's special feature 'components' (such as embedded
> multipliers and on-chip memory)?

In the thread "using BlockRam" started on friday is some code included which

shows how to use BlockRAM of a spartan-II. (In the message I posted this
morning) I suppose its similar to the virtex. If you have your design
syntethized, you can simulate it using a stimuli file, for example:

restart |                ******* RESTART *******
delete_signals
stepsize 5.0ns
clock clock 1 0
watch N_clock
vector address_ address[9:0]
assign address_ 00\h
vector N_address_ N_address[9:0]
vector dq_ dq[15:0]
assign dq_ 00\h
vector N_dq_ N_dq[15:0]
vector dqOut_ dqOut[63:0]
vector N_dqOut N_dqOut[63:0]
|vector ram0 ram0.DO[15:0]
|vector ram1 ram1.DO[15:0]
|vector ram2 ram2.DO[15:0]
|vector ram3 ram3.DO[15:0]
watch N138
watch N138_BUFGed
watch n_24
watch n_5
watch n_43
watch n_61
watch GND
watch GTS
assign enable 0
watch N_enable
assign writeEnable 0
watch N_writeEnable
assign reset 0

Look on the web side from xilinx for app notes! You'll probably find s.th.
about memory. Keep in mind, that there is a big difference between
"simulation" and "verification", although you can use the same stimuli
file. As long as you just simulate your design, the VHDL world is fine,
to understand the verification output you need a lot more knowledge
about the gate arry.

Hope that helps, I am a newby (as well (?)). Good luck!

-jc-


Article: 34973
Subject: Re: how to simulate virtex components?
From: "Sebastian" <novalid@ress>
Date: Mon, 17 Sep 2001 16:32:24 +0200
Links: << >>  << T >>  << A >>
That's clear to me. If i simulate after synthesis, the special components
can be simulated. This simulation however, is too far in the end of the
chain. I want to verify/correct my vhdl more quickly.

I think i need functional models of the components, or something.

regards,
Sebastian


"Jens-Christian Lache" <lache@tu-harburg.de_removeTheUnderscore> wrote in
message news:3BA5F15E.1C5A1E7C@tu-harburg.de_removeTheUnderscore...
> Sebastian wrote:
>
> > How to simulate the FPGA's special feature 'components' (such as
embedded
> > multipliers and on-chip memory)?
>
> In the thread "using BlockRam" started on friday is some code included
which
>
> shows how to use BlockRAM of a spartan-II. (In the message I posted this
> morning) I suppose its similar to the virtex. If you have your design
> syntethized, you can simulate it using a stimuli file, for example:
>
> restart |                ******* RESTART *******
> delete_signals
> stepsize 5.0ns
> clock clock 1 0
> watch N_clock
> vector address_ address[9:0]
> assign address_ 00\h
> vector N_address_ N_address[9:0]
> vector dq_ dq[15:0]
> assign dq_ 00\h
> vector N_dq_ N_dq[15:0]
> vector dqOut_ dqOut[63:0]
> vector N_dqOut N_dqOut[63:0]
> |vector ram0 ram0.DO[15:0]
> |vector ram1 ram1.DO[15:0]
> |vector ram2 ram2.DO[15:0]
> |vector ram3 ram3.DO[15:0]
> watch N138
> watch N138_BUFGed
> watch n_24
> watch n_5
> watch n_43
> watch n_61
> watch GND
> watch GTS
> assign enable 0
> watch N_enable
> assign writeEnable 0
> watch N_writeEnable
> assign reset 0
>
> Look on the web side from xilinx for app notes! You'll probably find s.th.
> about memory. Keep in mind, that there is a big difference between
> "simulation" and "verification", although you can use the same stimuli
> file. As long as you just simulate your design, the VHDL world is fine,
> to understand the verification output you need a lot more knowledge
> about the gate arry.
>
> Hope that helps, I am a newby (as well (?)). Good luck!
>
> -jc-
>



Article: 34974
Subject: Re: Altera survey
From: Nial Stewart <nials@britain.agilent.com>
Date: Mon, 17 Sep 2001 15:33:13 +0100
Links: << >>  << T >>  << A >>
Jon wrote:
> 
> Of those who took the trouble to take part in their survey some months ago
> how many of you actually got the promised Acex evaluation board ?
> 
>         Jon

Jon,

I recently received a ByteblasterMV cable, the latest CD romdata
sheet and a sample of a 7XXXB ( I think) device.

I couldn't remember what this was for, should I be waiting 
for an eval board too? :-).



Nial.



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