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Messages from 34975

Article: 34975
Subject: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 17 Sep 2001 07:51:07 -0700
Links: << >>  << T >>  << A >>
Ray,

For 10X18, he should be able to hit the desired speed without hand placing....

Austin

Ray Andraka wrote:

> To get the 125 MHz, you'll need to use the pipeline registers.  With 3.1 that
> means using FPGA editor.  You'll also need to precede and follow the multiplier
> immediately with CLB registers.  You may find you need to place those added
> registers by hand so that they are in the rignt places to get on the direct
> connects to the multiplier.
>
> pete dudley wrote:
>
> > Xilinx FAE Jason Moore helped me on this one. You can directly instantiate a
> > MULT18X18S to get the Synchronous multiplier. The core generator does not
> > give you that primitive. Speed files are still bouncing around on the
> > Tmultck parameter but they should run 125MHz especially since I only need
> > 10x18 out of them.
> >
> > --
> > Pete Dudley
> >
> > Arroyo Grande Systems
> >
> > "pete dudley" <padudle@spinn.net> wrote in message
> > news:tpqon9s22vare9@corp.supernews.com...
> > > Hello All,
> > >
> > > Does anyone know whether there is really an internal pipeline register
> > > inside the Virtex II embedded multiplier?
> > >
> > > I have an application that is very multiplier intensive and I need to run
> > at
> > > 125MHz. Without internal pipelining it is just about impossible to meet
> > this
> > > clock rate. I have been told there is a register inside those multipliers
> > > but that they are not supported in the 3.1i tools. I received my 4.1i
> > tools
> > > today and tried to turn on the pipeline register by specifying maximum
> > > pipelining in the core generator but the timing report still  indicates no
> > > internal pipelining.
> > >
> > > When I look at the multiplier blocks using FPGA Editor I can see that it
> > has
> > > a clock input. What's the story?
> > >
> > >   Thanks,
> > >
> > > --
> > > Pete Dudley
> > >
> > > Arroyo Grande Systems
> > >
> > >
> > >
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com


Article: 34976
Subject: Re: Virtex-2 availability
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 17 Sep 2001 07:58:20 -0700
Links: << >>  << T >>  << A >>
Rick,

The 2V3000, 2V1000, and 2V6000 are are available in the sample material
right now.

We chose the release the parts such that for development, one could start
with the 2V3000, and drop into the smaller parts for production.  The
packaging roadmap ensures compatibility.

And now for my own little comment:

The 2V40 is also available.  Poor little 2V40, all but ignored as its
larger cousins are passing it by.  The 2V40 costs less than the "robot
clock" chips, and does a heck of a lot lot more.  Anyone need variable
phase shift, fixed phase shift, skew management, multiple skew and duty
cycle corrected clock output driver that is programmable?

Austin

Rick Filipkiewicz wrote:

> Has anyone seen the XC2V1500/2000 parts yet or have any idea when they
> are due to hit the streets ?


Article: 34977
Subject: Re: INIT attribute of SRL16E
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 17 Sep 2001 08:00:20 -0700
Links: << >>  << T >>  << A >>
The SRL16 has no sets or resets, so...

If you which to use sets or resets (ie an intial value), the synthesis can not
use the SRL16.  Some synthesizers are smart enough to then re-target the SRL16 to
FF's, rather than use the LUT shift register.

Austin

khtsoi@pc90026.cse.cuhk.edu.hk wrote:

> Hi,
>
> I have try the followings in my VHDL code:
>
> ....
> attribute       INIT :  string;
> attribute       INIT    of      REG_W:  label is "0000000000011111";
>
> begin
> ....
>
> but the synopsys dc synthsis tools still post the following error:
>
> Warning: Attribute INIT not supported for synthesis  on line 125  (VHDL-2040)
> Warning: Attribute INIT not supported for synthesis  on line 126  (VHDL-2040)
> ...
>
> where 125 is the second line with label
>
> what should I do? help me please. thanks in advance!
>
> ---- Brittle


Article: 34978
Subject: Re: how to simulate virtex components?
From: Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore>
Date: Mon, 17 Sep 2001 17:19:52 +0200
Links: << >>  << T >>  << A >>
Sebastian wrote:

> That's clear to me. If i simulate after synthesis, the special components
> can be simulated. This simulation however, is too far in the end of the
> chain. I want to verify/correct my vhdl more quickly.
>
> I think i need functional models of the components, or something.
>
> regards,
> Sebastian
>
> "Jens-Christian Lache" <lache@tu-harburg.de_removeTheUnderscore> wrote in
> message news:3BA5F15E.1C5A1E7C@tu-harburg.de_removeTheUnderscore...
> > Sebastian wrote:
> >
> > > How to simulate the FPGA's special feature 'components' (such as
> embedded
> > > multipliers and on-chip memory)?
> >
> > In the thread "using BlockRam" started on friday is some code included
> which
> >
> > shows how to use BlockRAM of a spartan-II. (In the message I posted this
> > morning) I suppose its similar to the virtex. If you have your design
> > syntethized, you can simulate it using a stimuli file, for example:
> >
> > restart |                ******* RESTART *******
> > delete_signals
> > stepsize 5.0ns
> > clock clock 1 0
> > watch N_clock
> > vector address_ address[9:0]
> > assign address_ 00\h
> > vector N_address_ N_address[9:0]
> > vector dq_ dq[15:0]
> > assign dq_ 00\h
> > vector N_dq_ N_dq[15:0]
> > vector dqOut_ dqOut[63:0]
> > vector N_dqOut N_dqOut[63:0]
> > |vector ram0 ram0.DO[15:0]
> > |vector ram1 ram1.DO[15:0]
> > |vector ram2 ram2.DO[15:0]
> > |vector ram3 ram3.DO[15:0]
> > watch N138
> > watch N138_BUFGed
> > watch n_24
> > watch n_5
> > watch n_43
> > watch n_61
> > watch GND
> > watch GTS
> > assign enable 0
> > watch N_enable
> > assign writeEnable 0
> > watch N_writeEnable
> > assign reset 0
> >
> > Look on the web side from xilinx for app notes! You'll probably find s.th.
> > about memory. Keep in mind, that there is a big difference between
> > "simulation" and "verification", although you can use the same stimuli
> > file. As long as you just simulate your design, the VHDL world is fine,
> > to understand the verification output you need a lot more knowledge
> > about the gate arry.
> >
> > Hope that helps, I am a newby (as well (?)). Good luck!
> >
> > -jc-
> >

This is s.th. I haven't understood either. I work with Foundation
3.1i, which doesn't allow simulation before synthesis. I found
some screenshots of 2.1i on the net, that show the simulation button
directly attatched to the "design entry" button. Quit annying since my
largest file takes 3 min to synthesize...

-jc-


Article: 34979
Subject: Re: FPU core
From: Tom Dillon <tdillon@dilloneng.com>
Date: Mon, 17 Sep 2001 15:38:17 GMT
Links: << >>  << T >>  << A >>
Check ours out:

http://www.dilloneng.com/ipcores/fpoint/index.html



>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<

On 9/7/2001, 4:39:06 AM, "Andrew Gray" <andrew@tuks.co.za> wrote regardi=
ng=20
FPU core:


> Hi

> Does anyone know of a VHDL Floating point core that is capable of +, -=
,=20
x,
> div, int to FP & FP to int calculations?

> Andrew

Article: 34980
Subject: Re: Problems with Xilinx App Note 223 (UART with Internal 16-Byte Buffer)
From: Erik <e.vullings@ame.nu>
Date: Mon, 17 Sep 2001 08:44:58 -0700
Links: << >>  << T >>  << A >>
I found the same problem and discussed it with Ken Chapman of Xilinx, he didn't find it a problem.
Here after I made a RX-module and had a 100% performance. In short the RX-uart macro is buggy!!! Do not use that one. PS You can write a RX-module by yourself in 4 hours.

Succes.

Article: 34981
Subject: Re: Virtex-2 availability
From: John_H <johnhandwork@mail.com>
Date: Mon, 17 Sep 2001 16:12:41 GMT
Links: << >>  << T >>  << A >>
I'd love variable phase shift, but...
I haven't gotten good detail from the available DCM literature:
  How long (if at all) does it take to settle from this delay-line-switched
phase change?
  Can the phase shift be "wrapped around" such that decrementing past -255
ends up back at zero?
  If there is a wrap, is there a specified phase hit more than one delay tap
in size?

I love what the part might bring to my design but the info's a little
incomplete just yet.


Austin Lesea wrote:

> The 2V40 is also available.  Poor little 2V40, all but ignored as its
> larger cousins are passing it by.  The 2V40 costs less than the "robot
> clock" chips, and does a heck of a lot lot more.  Anyone need variable
> phase shift, fixed phase shift, skew management, multiple skew and duty
> cycle corrected clock output driver that is programmable?


Article: 34982
Subject: Re: Carry Chain: Delay
From: John_H <johnhandwork@mail.com>
Date: Mon, 17 Sep 2001 16:20:37 GMT
Links: << >>  << T >>  << A >>
Possible explanaition:
  What we see in the data sheets for the low level - LUTs, CLBs, Slices, IOBs - are the logical equivalent of the physical realization.  If a function is more apparent with an illustration with two cascaded MUXes while the physical implementation is a parallel structure, the illustration should probably show the MUXes.

I try to look at the timing numbers without explicit ties to the illustrated implementation.  I get by pretty well.

vivek wrote:

> When implementing a two bit adder in the same slice of the Virtex CLB , I found that the F-LUT input to Cout delay(final Cout of the slice ) was less than the G-LUT input to Cout delay(final Cout delay of the same slice), while if one looks at the CLB structure it is seen that the number of muxes encountered from the G-LUT input  to Cout is less than those encountered form the F-LUT input to Cout.So I should get the F-LUT input to Cout delay more while I'am getting this less !!!Can anybody explain this conundrum!!
>
> Thanx in advance


Article: 34983
Subject: Re: Virtex-E1600 unsupported?
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Mon, 17 Sep 2001 18:31:03 +0200
Links: << >>  << T >>  << A >>
Are there really two different Foundation versions? What is the name of this
"real man" :-) version?

Michael




Article: 34984
Subject: Re: Problems with Xilinx App Note 223 (UART with Internal 16-Byte
From: Goran Bilski <goran@xilinx.com>
Date: Mon, 17 Sep 2001 09:33:25 -0700
Links: << >>  << T >>  << A >>
Hi,

You need sample the RX signal with a flip-flop in order to remove the metastability on the RX signal.
The RX signals goes internally to three different flip-flops and since the RX signal is asynchronously to the clock signal,
a metastability problem can occur.

So just sample the RX signal with the clock signal before using it to the RX module.

Göran Bilski

Erik wrote:

> I found the same problem and discussed it with Ken Chapman of Xilinx, he didn't find it a problem.
> Here after I made a RX-module and had a 100% performance. In short the RX-uart macro is buggy!!! Do not use that one. PS You can write a RX-module by yourself in 4 hours.
>
> Succes.


Article: 34985
Subject: Re: using BlockRAM
From: John_H <johnhandwork@mail.com>
Date: Mon, 17 Sep 2001 16:34:34 GMT
Links: << >>  << T >>  << A >>
BlockRAMs are probably the weakest link in most speed-dependent Xilinx designs.
Tbcko is a resonable number but the routing just adds to it, especially when you have
great distances to traverse.  Add an IOB output pad delay (FAST?  High current?) and
your situation gets worse.

You should probably try to arrange your design to allow a pipeline stage:  register
the signals in the IOBs.  There aren't many ways to try to cheat the system.

As far as tBACK and tBDCK are concerned, I interpret the values as setup required
before the clock.  In a synchronous design it's just part of your 10nS cycle.


Jens-Christian Lache wrote:

> -------------------------------------------------  --------
> RAMB4_R0C0.DOA15     Tbcko                 3.310R  ram3
>                                                    ram3.A
> A3.O                 net (fanout=1)        3.785R  N_dqOut<63>
> A3.PAD               Tioop                 4.787R  dqOut<63>
>                                                    C_dqOut<63>
>                                                    dqOut<63>.PAD
> -------------------------------------------------
> Total (8.097ns logic, 3.785ns route)      11.882ns
>       (68.1% logic, 31.9% route)


Article: 34986
Subject: Re: how to simulate virtex components?
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Mon, 17 Sep 2001 17:44:08 +0100
Links: << >>  << T >>  << A >>
For RTL/pre-synth simulation use this:

-- synthesis translate_off
library unisim;
use unisim.vcomponents.all;
-- synthesis translate_on



"Sebastian" <novalid@ress> wrote in message
news:3ba6093c$0$210$4d4ebb8e@oce.news.eu.uu.net...
> That's clear to me. If i simulate after synthesis, the special components
> can be simulated. This simulation however, is too far in the end of the
> chain. I want to verify/correct my vhdl more quickly.
>
> I think i need functional models of the components, or something.
>
> regards,
> Sebastian
>
>
> "Jens-Christian Lache" <lache@tu-harburg.de_removeTheUnderscore> wrote in
> message news:3BA5F15E.1C5A1E7C@tu-harburg.de_removeTheUnderscore...
> > Sebastian wrote:
> >
> > > How to simulate the FPGA's special feature 'components' (such as
> embedded
> > > multipliers and on-chip memory)?
> >
> > In the thread "using BlockRam" started on friday is some code included
> which
> >
> > shows how to use BlockRAM of a spartan-II. (In the message I posted this
> > morning) I suppose its similar to the virtex. If you have your design
> > syntethized, you can simulate it using a stimuli file, for example:
> >
> > restart |                ******* RESTART *******
> > delete_signals
> > stepsize 5.0ns
> > clock clock 1 0
> > watch N_clock
> > vector address_ address[9:0]
> > assign address_ 00\h
> > vector N_address_ N_address[9:0]
> > vector dq_ dq[15:0]
> > assign dq_ 00\h
> > vector N_dq_ N_dq[15:0]
> > vector dqOut_ dqOut[63:0]
> > vector N_dqOut N_dqOut[63:0]
> > |vector ram0 ram0.DO[15:0]
> > |vector ram1 ram1.DO[15:0]
> > |vector ram2 ram2.DO[15:0]
> > |vector ram3 ram3.DO[15:0]
> > watch N138
> > watch N138_BUFGed
> > watch n_24
> > watch n_5
> > watch n_43
> > watch n_61
> > watch GND
> > watch GTS
> > assign enable 0
> > watch N_enable
> > assign writeEnable 0
> > watch N_writeEnable
> > assign reset 0
> >
> > Look on the web side from xilinx for app notes! You'll probably find s.th.
> > about memory. Keep in mind, that there is a big difference between
> > "simulation" and "verification", although you can use the same stimuli
> > file. As long as you just simulate your design, the VHDL world is fine,
> > to understand the verification output you need a lot more knowledge
> > about the gate arry.
> >
> > Hope that helps, I am a newby (as well (?)). Good luck!
> >
> > -jc-
> >
>
>



Article: 34987
Subject: Re: QPSK modulator with no multipliers
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 16:46:41 GMT
Links: << >>  << T >>  << A >>
There is a QPSK modem example in the foils for the
modulation/demodulation talk I gave at Designcon 2000.  They are
available on my website under the publications page.  I don't think that
presentation had the details for the complete modulator, but the
information is there in the sections on modulation.  Basically, it uses
serial distributed arithmetic for the transmit filters (which are
interpolating filters) and it mixes a Fs/4 carrier with the signal to get
to an IF.  That particular design fit in a Xilinx 4013 along with a
demodulator.

Antonio wrote:

> Good Morning
> I'm designing a QPSK Modulator using an NCO, do you know where I can
> found some documentation about a schema of it with no multiplier and
> no NCO, someone tried to explain it to me, but until now I didn't
> understand how it works and so I can't produce a valid schema for it.
> Thanks in any case ...
>
> Antonio D'Ottavio

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34988
Subject: Re: INIT attribute of SRL16E
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Mon, 17 Sep 2001 17:50:41 +0100
Links: << >>  << T >>  << A >>
Yes.  I have not seen the guy's code, but I think he wants
the SRL preloaded with a pattern, which could be done via
an INIT.  Of course, after 16 clocks the pattern has gone,
never to reappear even if reset is asserted till hell boils
over.  (Hades is icy cold in classical mythology)



"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3BA61004.50C47A6F@xilinx.com...
> The SRL16 has no sets or resets, so...
>
> If you which to use sets or resets (ie an intial value), the synthesis can not
> use the SRL16.  Some synthesizers are smart enough to then re-target the SRL16
to
> FF's, rather than use the LUT shift register.
>
> Austin
>
> khtsoi@pc90026.cse.cuhk.edu.hk wrote:
>
> > Hi,
> >
> > I have try the followings in my VHDL code:
> >
> > ....
> > attribute       INIT :  string;
> > attribute       INIT    of      REG_W:  label is "0000000000011111";
> >
> > begin
> > ....
> >
> > but the synopsys dc synthsis tools still post the following error:
> >
> > Warning: Attribute INIT not supported for synthesis  on line 125
(VHDL-2040)
> > Warning: Attribute INIT not supported for synthesis  on line 126
(VHDL-2040)
> > ...
> >
> > where 125 is the second line with label
> >
> > what should I do? help me please. thanks in advance!
> >
> > ---- Brittle
>



Article: 34989
Subject: Re: Problems with Xilinx VirtexE (Newbie)
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 16:55:37 GMT
Links: << >>  << T >>  << A >>
You will likely have lots of problems using a mechanical pushbutton as your
clock.  Mechanical switches 'bounce', meaning that they open and close many
times as the contact is being made or broken.  Each of the bounces will be
interpreted as a clock.  Instead, consider using a clock source as the
source of your clock.  The switch input should be debounced, then after
conditioning be used as an enable signal to your logic.

Debouncing a switch can be done with a counter and a simple  state state
machine arranged so that you can't go to the other stable state until the
counter reaches its terminal count.  The counter is reset anytime there is a
transition on the switch input.






Falk Brunner wrote:

> Paul schrieb:
> >
> > Hi,
> >
> > I'm trying to do my first examples with FPGA's and I am running into
> > some problems with a Xilinx VirtexE in a demo board.
> >
> > I want to make a counter and to display the count in a 7-segment
> > display of the board. The clock for this counter schould be a
> > press-button of the board. The problem is that the button is
> > physically connected to the pin P95 of th FPGA and the Xilinx tool
> > (ISE 3.1) doesn't allow me to place this input signal in this pin. If
> > I constrain this signal to this pin I get the following error:
> >
> > ERROR:MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or
> > BUFGP
> >    symbol "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should
> > only be LOCed
> >    to GCLKIOB site.
>
> The synthesis software recognizes the clock signal and automatically
> creates a clock buffer. This has to be disabled. This can be done in the
> synthesis constraints editor. When you create a new version (menu entry)
> , click the marker for EDIT SYNTHESIS CONSTRAINTS. When the windo pops
> up, go to the PORTS window, and select for the default clock buffer
> value (1st row) DONT USE.
>
> --
> MFG
> Falk

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34990
Subject: Re: Block RAM initialization
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 16:57:59 GMT
Links: << >>  << T >>  << A >>
You can also initialize it with an INIT attribute from within your VHDL code if you
instantiate the BRAMs.  Your VHDL can use a package file with the desired contents
as the source for the INIT attributes.   If you want to simulate it, you'll also
have to put similar values into the sim model using the INIT generics.

Tim wrote:

> Not practical for lots of data.  I don't have the books with me,
> but in essence you need to generate the BRAMs withe CoreGen, then
> wite a program to hack your init stuff into something like a .coe
> file(s).  This will then get you everything you want through both
> simulation and synthesis.
>
> Health warning - this is from memory - look it up in the help files.
>
> "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
> news:3B9FEA30.4E6811BF@algor.co.uk...
> >
> >
> > Jan Pech wrote:
> >
> > > Hi,
> > > I'm using RAM description in my design which maps on the BlockRAM in Xilinx
> > > Spartan-II. Is there any way how to initialize this RAM with my own values?
> > > I'm using WebPACK 3.3.
> > >
> > > Thanks
> > > Jan
> > >
> > > ___________________________
> > >      j.pech@sh.cvut.cz
> > >      +420 (723) 760802
> > >      ICQ: 56431283
> >
> > There is a thing called ``INIT'' you can apply through the user constraints
> > file (UCF). To get a description download the 3.3i `Libraries Reference Guide'
> > from the Xilinx site. Its decribed in the ``Attributes, Constraints, and Carry
> > logic'' section.
> >
> > The other possibility is to use JBits to hack the bitstream.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34991
Subject: Re: Block RAM initialization
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 17:02:24 GMT
Links: << >>  << T >>  << A >>
A couple of minor points here.

1) if instead of xc_props you create user attributes, the code will be more portable (ie it will also work with
leonardo).  FOr example:
Attribute INIT_00:string;
Attribute INIT_00 of U1:label is "C072A49CAFA2D4ADF04759FA7DC982CA76ABD7FE2B670130C56F6BF27B777C63";

2)  you will need synthesis translate_off and synthesis translate_on pragmas around the generics, else the synthesis
will create a mess.  It doesn't deal well with generics on black boxes.



Catalin Baetoniu wrote:

> Here is a VHDL example on how to do this. The code works both for synthesis and
> functional simulation, all you have to do is choose the proper library at the top
> of the file.
>
> Catalin Baetoniu
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
>
> -- For Synthesys
> library virtex;
> use virtex.components.all;
>
> -- For Functional Simulation
> --library unisim;
> --use unisim.all;
>
> entity SBox is
>   port(CLK:in STD_LOGIC;
>        I:in STD_LOGIC_VECTOR(17 downto 0);
>        O:out STD_LOGIC_VECTOR(31 downto 0));
> end SBox;
>
> architecture SBox of SBox is
>   attribute black_box:BOOLEAN;
>   component RAMB4_S8_S8
>     generic(INIT_00,INIT_01,INIT_02,INIT_03,
>             INIT_04,INIT_05,INIT_06,INIT_07,
>             INIT_08,INIT_09,INIT_0A,INIT_0B,
>
> INIT_0C,INIT_0D,INIT_0E,INIT_0F:BIT_VECTOR:=X"0000000000000000000000000000000000000000000000000000000000000000");
>
>     port(CLKA:in STD_LOGIC;
>          RSTA:in STD_LOGIC;
>          ENA:in STD_LOGIC;
>          WEA:in STD_LOGIC;
>          ADDRA:in STD_LOGIC_VECTOR (8 downto 0);
>          DIA:in STD_LOGIC_VECTOR (7 downto 0);
>          DOA:out STD_LOGIC_VECTOR (7 downto 0);
>          CLKB:in STD_LOGIC;
>          RSTB:in STD_LOGIC;
>          ENB:in STD_LOGIC;
>          WEB:in STD_LOGIC;
>          ADDRB:in STD_LOGIC_VECTOR (8 downto 0);
>          DIB:in STD_LOGIC_VECTOR (7 downto 0);
>          DOB:out STD_LOGIC_VECTOR (7 downto 0));
>   end component;
>   attribute black_box of RAMB4_S8_S8:component is TRUE;
>   attribute xc_props:STRING;
>   attribute xc_props of s0:label is
> "INIT_00=C072A49CAFA2D4ADF04759FA7DC982CA76ABD7FE2B670130C56F6BF27B777C63,"&
>
> "INIT_01=75B227EBE28012079A059618C323C7041531D871F1E5A534CCF73F362693FDB7,"&
>
> "INIT_02=CF584C4A39BECB6A5BB1FC20ED00D153842FE329B3D63B52A05A6E1B1A2C8309,"&
>
> "INIT_03=D2F3FF1021DAB6BCF5389D928F40A351A89F3C507F02F94585334D43FBAAEFD0,"&
>
> "INIT_04=DB0B5EDE14B8EE4688902A22DC4F816073195D643D7EA7C41744975FEC130CCD,"&
>
> "INIT_05=08AE7A65EAF4566CA94ED58D6D37C8E779E4959162ACD3C25C2406490A3A32E0,"&
>
> "INIT_06=9E1DC186B95735610EF6034866B53E708A8BBD4B1F74DDE8C6B4A61C2E2578BA,"&
>
> "INIT_07=16BB54B00F2D99416842E6BF0D89A18CDF2855CEE9871E9B948ED9691198F8E1,"&
>
> "INIT_08=CBE9DEC444438E3487FF2F9B8239E37CFBD7F3819EA340BF38A53630D56A0952,"&
>
> "INIT_09=25D18B6D49A25B76B224D92866A12E084EC3FA420B954CEE3D23C2A632947B54,"&
>
> "INIT_0A=849D8DA75746155EDAB9EDFD5048706C92B6655DCC5CA4D41698688664F6F872,"&
>
> "INIT_0B=6B8A130103BDAFC1020F3FCA8F1E2CD00645B3B80558E4F70AD3BC8C00ABD890,"&
>
> "INIT_0C=6EDF751CE837F9E28535ADE72274AC9673E6B4F0CECFF297EADC674F4111913A,"&
>
> "INIT_0D=F45ACD78FEC0DB9A2079D2C64B3E56FC1BBE18AA0E62B76F89C5291D711AF147,"&
>
> "INIT_0E=EF9CC9939F7AE52D0D4AB519A97F51605FEC8027591012B131C7078833A8DD1F,"&
>
> "INIT_0F=7D0C2155631469E126D677BA7E042B17619953833CBBEBC8B0F52AAE4D3BE0A0";
> begin
>   s0:RAMB4_S8_S8 generic
> map(INIT_00=>X"C072A49CAFA2D4ADF04759FA7DC982CA76ABD7FE2B670130C56F6BF27B777C63",
>
> INIT_01=>X"75B227EBE28012079A059618C323C7041531D871F1E5A534CCF73F362693FDB7",
>
> INIT_02=>X"CF584C4A39BECB6A5BB1FC20ED00D153842FE329B3D63B52A05A6E1B1A2C8309",
>
> INIT_03=>X"D2F3FF1021DAB6BCF5389D928F40A351A89F3C507F02F94585334D43FBAAEFD0",
>
> INIT_04=>X"DB0B5EDE14B8EE4688902A22DC4F816073195D643D7EA7C41744975FEC130CCD",
>
> INIT_05=>X"08AE7A65EAF4566CA94ED58D6D37C8E779E4959162ACD3C25C2406490A3A32E0",
>
> INIT_06=>X"9E1DC186B95735610EF6034866B53E708A8BBD4B1F74DDE8C6B4A61C2E2578BA",
>
> INIT_07=>X"16BB54B00F2D99416842E6BF0D89A18CDF2855CEE9871E9B948ED9691198F8E1",
>
> INIT_08=>X"CBE9DEC444438E3487FF2F9B8239E37CFBD7F3819EA340BF38A53630D56A0952",
>
> INIT_09=>X"25D18B6D49A25B76B224D92866A12E084EC3FA420B954CEE3D23C2A632947B54",
>
> INIT_0A=>X"849D8DA75746155EDAB9EDFD5048706C92B6655DCC5CA4D41698688664F6F872",
>
> INIT_0B=>X"6B8A130103BDAFC1020F3FCA8F1E2CD00645B3B80558E4F70AD3BC8C00ABD890",
>
> INIT_0C=>X"6EDF751CE837F9E28535ADE72274AC9673E6B4F0CECFF297EADC674F4111913A",
>
> INIT_0D=>X"F45ACD78FEC0DB9A2079D2C64B3E56FC1BBE18AA0E62B76F89C5291D711AF147",
>
> INIT_0E=>X"EF9CC9939F7AE52D0D4AB519A97F51605FEC8027591012B131C7078833A8DD1F",
>
> INIT_0F=>X"7D0C2155631469E126D677BA7E042B17619953833CBBEBC8B0F52AAE4D3BE0A0")
>                  port map(CLKA=>CLK,
>                           RSTA=>'0',
>                           ENA=>'1',
>                           WEA=>'0',
>                           ADDRA=>I,
>                           DIA=>"00000000",
>                           DOA=>O(7 downto 0),
>                           CLKB=>CLK,
>                           RSTB=>'0',
>                           ENB=>'1',
>                           WEB=>'0',
>                           ADDRB=>I(17 downto 9),
>                           DIB=>"00000000",
>                           DOB=>O(15 downto 8));
> end SBox;
>
> renaux wrote:
>
> > Try to read the XAPP199 page 21 . Coergen use a COE file and creates a MIF
> > (memory Init file ). This file is an ascii one which would be easy to creates
> > in the vhdl. But I am not sure it will work on synthesis . I have the same
> > problem issue and I have to try myself to solve this
> >
> > regards
> >
> > ------
> > User of http://www.foorum.com/. The best tools for usenet searching.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34992
Subject: Re: Carry Chain: Delay
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 17:05:01 GMT
Links: << >>  << T >>  << A >>
The actual circuit used is quite different than the equivalent circuit shown in the databooks.  The actual circuit has a more parallel structure (ie the carry out of the F does not feed into the carry in of the G, rather it is considerably more complex to help speed up the slice carry).

vivek wrote:

> When implementing a two bit adder in the same slice of the Virtex CLB , I found that the F-LUT input to Cout delay(final Cout of the slice ) was less than the G-LUT input to Cout delay(final Cout delay of the same slice), while if one looks at the CLB structure it is seen that the number of muxes encountered from the G-LUT input  to Cout is less than those encountered form the F-LUT input to Cout.So I should get the F-LUT input to Cout delay more while I'am getting this less !!!Can anybody explain this conundrum!!
>
> Thanx in advance

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34993
Subject: Re: INIT attribute of SRL16E
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 17:13:29 GMT
Links: << >>  << T >>  << A >>
If the SRL16E is instantiated, this will work to initialize it on power up (but not
for subsequent global resets).  I am assuming that REG_W is an instantiated SRL16E.
If it is, then I don't see anything wrong with your code.  It may be DC doesn't
properly support user attributes, or that the INIT attribute has already been defined
elsewhere.  Also, IIRC, the INIT attribute for an SRL16E should be a hex string, not
a binary string (I don't think this is your problem though, as the synthesis should
just pass whatever string you give it through to the edif netlist).  This does work
for synplicity and leonardo.  Maybe you need to switch tools.

Austin Lesea wrote:

> The SRL16 has no sets or resets, so...
>
> If you which to use sets or resets (ie an intial value), the synthesis can not
> use the SRL16.  Some synthesizers are smart enough to then re-target the SRL16 to
> FF's, rather than use the LUT shift register.
>
> Austin
>
> khtsoi@pc90026.cse.cuhk.edu.hk wrote:
>
> > Hi,
> >
> > I have try the followings in my VHDL code:
> >
> > ....
> > attribute       INIT :  string;
> > attribute       INIT    of      REG_W:  label is "0000000000011111";
> >
> > begin
> > ....
> >
> > but the synopsys dc synthsis tools still post the following error:
> >
> > Warning: Attribute INIT not supported for synthesis  on line 125  (VHDL-2040)
> > Warning: Attribute INIT not supported for synthesis  on line 126  (VHDL-2040)
> > ...
> >
> > where 125 is the second line with label
> >
> > what should I do? help me please. thanks in advance!
> >
> > ---- Brittle

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34994
Subject: Re: Innoveda and ISE Alliance 4.1i ?
From: billnowicky@yahoo.com (Bill Nowicky)
Date: 17 Sep 2001 10:16:55 -0700
Links: << >>  << T >>  << A >>
I did the custom install and found all part libraries except for the
CoolRunner family.  Does Xilinx support Coolrunner design under
Innoveda Viewdraw?

Bill Nowicky

"pete dudley" <padudle@spinn.net> wrote in message news:<tq2hhqc00lhp21@corp.supernews.com>...
> I want to say thanks to Philip Frieden with help on this issue. Xilinx does
> still supply Innoveda Viewdraw libraries with the 4.1i release.
> 
> The trick is to select Custom install option while running the Xilinx
> installation program. The Custom install gives the option to select Innoveda
> libraries while the Typical install defaults to not installing them.
> 
> Anyway, life is good again.
> 
> --
> Pete Dudley
> 
> "Pete Dudley" <padudle@sandia.gov> wrote in message
> news:9nld5u$5en$1@sass1828.sandia.gov...
> > I just installed ISE Alliance 4.1i and find no support for Innoveda tools.
> > There are no Viewdraw libraries shipped with the software and no Innoveda
> > Interface Guide in the online documentation. There is still a Mentor
> > Graphics Interface Guide.
> >
> > Has Xilinx stopped working with Innoveda? I would consider that a shame.
> >
> > --
> > Pete Dudley
> >

Article: 34995
Subject: Re: Virtex-2 availability
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 17:17:26 GMT
Links: << >>  << T >>  << A >>
Do those DCM features work in the currently available XC2V40 silicon?

Austin Lesea wrote:

> Rick,
>
> The 2V3000, 2V1000, and 2V6000 are are available in the sample material
> right now.
>
> We chose the release the parts such that for development, one could start
> with the 2V3000, and drop into the smaller parts for production.  The
> packaging roadmap ensures compatibility.
>
> And now for my own little comment:
>
> The 2V40 is also available.  Poor little 2V40, all but ignored as its
> larger cousins are passing it by.  The 2V40 costs less than the "robot
> clock" chips, and does a heck of a lot lot more.  Anyone need variable
> phase shift, fixed phase shift, skew management, multiple skew and duty
> cycle corrected clock output driver that is programmable?
>
> Austin
>
> Rick Filipkiewicz wrote:
>
> > Has anyone seen the XC2V1500/2000 parts yet or have any idea when they
> > are due to hit the streets ?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34996
Subject: Re: Altera survey
From: Ray Andraka <ray@andraka.com>
Date: Mon, 17 Sep 2001 17:21:34 GMT
Links: << >>  << T >>  << A >>
I got an evaluation device, not a board.  Since it is in a BGA package, it is
quite hard to evaluate without producing a board.  Makes a nice skipping stone
however (I'm sure it will skip on water much better than the beeper in that beer
commercial).

Nial Stewart wrote:

> Jon wrote:
> >
> > Of those who took the trouble to take part in their survey some months ago
> > how many of you actually got the promised Acex evaluation board ?
> >
> >         Jon
>
> Jon,
>
> I recently received a ByteblasterMV cable, the latest CD romdata
> sheet and a sample of a 7XXXB ( I think) device.
>
> I couldn't remember what this was for, should I be waiting
> for an eval board too? :-).
>
> Nial.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34997
Subject: Re: Virtex-2 availability
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 17 Sep 2001 10:29:35 -0700
Links: << >>  << T >>  << A >>



John,

Good questions.  I'll answer them.

Austin

John_H wrote:

> I'd love variable phase shift, but...
> I haven't gotten good detail from the available DCM literature:
>   How long (if at all) does it take to settle from this delay-line-switched
> phase change?

It takes 84 clocks on the CLKIN input, plus three on the PSCLK input to effect a
change (increment or decrement).  If those are tied together (commonly done)
that is 87 clocks.  You MUST wait for PSDONE before PSEN is asserted to inc or
dec again.

For fixed phase shift, PSEN, PSCLK, and PSINCDEC are all set to '0', and a fixed
offset value specified.

Of curious coincidence, for recovery of DDR data at ~333 MHz (666 Mb/s), the
fixed value is 42 ..... must be some form of "last message" here ....

As well, often misunderstood, is that not every increment or decrement results
in a phase change.  For example, if the clock period was 5.12 nS, then each
numeric value is ~ 20 ps.  Since the tap value is ~50 ps, it will only change
phase after every 2 or 3 inc's or dec's.  At lower frequencies, every inc or dec
results in a phase change.

>
>   Can the phase shift be "wrapped around" such that decrementing past -255
> ends up back at zero?

No.  The phase shift increments until it overflows (sticks at 255), or
decrements until 0 (then sticks at 0).  An external counter is required if you
want to keep track of it.  If you PSOVERFLOW, the unit needs a RESET to go
again.

I know, I know, what a pain (but there were good reasons for not doing what you
suggest)!  We are looking at using two DCM's to provide a continous phase shift
application:  as one increments, the other decrements, so that when the overflow
point is approached, you trade off to the other DCM by using the BUFGMUX to
select the one that now has room to increment (or decrement).

>
>   If there is a wrap, is there a specified phase hit more than one delay tap
> in size?

No wrap, no issue.  Tracking between two DCM's becomes the issue then, but with
the two getting their CLKFB from the same net, it should be less than the
overall DCM offset error.

>
>
> I love what the part might bring to my design but the info's a little
> incomplete just yet.

True.  We are working on numerous app notes.  Unfortunately, we keep thinking of
new and great stuff even while we are writing....

>
>
> Austin Lesea wrote:
>
> > The 2V40 is also available.  Poor little 2V40, all but ignored as its
> > larger cousins are passing it by.  The 2V40 costs less than the "robot
> > clock" chips, and does a heck of a lot lot more.  Anyone need variable
> > phase shift, fixed phase shift, skew management, multiple skew and duty
> > cycle corrected clock output driver that is programmable?




Article: 34998
Subject: Re: Virtex-2 variable DPS availability
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 17 Sep 2001 10:37:08 -0700
Links: << >>  << T >>  << A >>
Ray,

The only features that do not work per the data sheet are the synthesizer
(limited M/D values -- see the errata sheet), and the variable phase shifter is
broken.

The fixed phase shift works fine.  The residual jitter is also about 25% larger
than the production silicon (a little tweaking needed to be done).

The variable phase shift does shift, but it will get "stuck" at some point, and
shift no further.  If you need to vary a small amount (+ or -) about a fixed
point, and that fixed point isn't in the wrong place (if you really want the
details, I can email them to you on where the sticking spot is) it works fine.

Austin

Ray Andraka wrote:

> Do those DCM features work in the currently available XC2V40 silicon?
>
> Austin Lesea wrote:
>
> > Rick,
> >
> > The 2V3000, 2V1000, and 2V6000 are are available in the sample material
> > right now.
> >
> > We chose the release the parts such that for development, one could start
> > with the 2V3000, and drop into the smaller parts for production.  The
> > packaging roadmap ensures compatibility.
> >
> > And now for my own little comment:
> >
> > The 2V40 is also available.  Poor little 2V40, all but ignored as its
> > larger cousins are passing it by.  The 2V40 costs less than the "robot
> > clock" chips, and does a heck of a lot lot more.  Anyone need variable
> > phase shift, fixed phase shift, skew management, multiple skew and duty
> > cycle corrected clock output driver that is programmable?
> >
> > Austin
> >
> > Rick Filipkiewicz wrote:
> >
> > > Has anyone seen the XC2V1500/2000 parts yet or have any idea when they
> > > are due to hit the streets ?
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com


Article: 34999
Subject: Re: INIT attribute of SRL16E
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 17 Sep 2001 10:39:46 -0700
Links: << >>  << T >>  << A >>
Ray,

You are correct.   The intial state of the SRL is settable by the bitstream loading the
values into the LUT's.  So, it sounds like it is synthesis issue solely.  If you do
create a user set or reset on the SRL, then it will implement in CLBs, not LUT memory
used as a shift register, or error out (depending on the synthesizer used).

Austin

Ray Andraka wrote:

> If the SRL16E is instantiated, this will work to initialize it on power up (but not
> for subsequent global resets).  I am assuming that REG_W is an instantiated SRL16E.
> If it is, then I don't see anything wrong with your code.  It may be DC doesn't
> properly support user attributes, or that the INIT attribute has already been defined
> elsewhere.  Also, IIRC, the INIT attribute for an SRL16E should be a hex string, not
> a binary string (I don't think this is your problem though, as the synthesis should
> just pass whatever string you give it through to the edif netlist).  This does work
> for synplicity and leonardo.  Maybe you need to switch tools.
>
> Austin Lesea wrote:
>
> > The SRL16 has no sets or resets, so...
> >
> > If you which to use sets or resets (ie an intial value), the synthesis can not
> > use the SRL16.  Some synthesizers are smart enough to then re-target the SRL16 to
> > FF's, rather than use the LUT shift register.
> >
> > Austin
> >
> > khtsoi@pc90026.cse.cuhk.edu.hk wrote:
> >
> > > Hi,
> > >
> > > I have try the followings in my VHDL code:
> > >
> > > ....
> > > attribute       INIT :  string;
> > > attribute       INIT    of      REG_W:  label is "0000000000011111";
> > >
> > > begin
> > > ....
> > >
> > > but the synopsys dc synthsis tools still post the following error:
> > >
> > > Warning: Attribute INIT not supported for synthesis  on line 125  (VHDL-2040)
> > > Warning: Attribute INIT not supported for synthesis  on line 126  (VHDL-2040)
> > > ...
> > >
> > > where 125 is the second line with label
> > >
> > > what should I do? help me please. thanks in advance!
> > >
> > > ---- Brittle
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com




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