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Messages from 35200

Article: 35200
Subject: Re: Virtex2 slice level instantiation in verilog question
From: Ray Andraka <ray@andraka.com>
Date: Tue, 25 Sep 2001 20:43:04 GMT
Links: << >>  << T >>  << A >>
You are talking about the xorcy.  Yes, it can be done but is generally not
worth the extra effort.  You need to instantiate carry chain components
muxcy and xorcy to do this.  The muxcy inputs get tied off to 0 and 1 at
the CLB boundaries, but be careful.  Last time I tried this (about a year
ago I think), the mapper connected the muxcy 1 input to a '1' generated in
another slice and passed in via the cin rather than using the bx input
tied off to '1'.  That winds up with the same number of slices as the
synthesized solution, and it is a bit slower because of the carry chain
connections.
I think there is also a floorplanner issue with getting and keeping the
xorcy in the top half of the slice, as the floorplanner likes to move it
to the bottom where it won't route.  The more recent service packs may
have fixed this, but I doubt it (again, I looked at this last about a year
ago).  You can force the implementation through the FPGA editor as a hard
macro, but then it is a chunk that you can't functionally simulate.
Unless there is a real need for squeezing out the last luts, you are
better off using the more conventional 2 level solution generated by
synplicity.



"J.Ho" wrote:

> Hi all,
>
> I am trying to instantiate specific elements inside a Virtex 2 slice
> in verilog, such as XORG, GYMUX.  Does anyone know if that is possible
> with synthesis and PAR tools?
>
> For example, if I want a 8-input xor gate, Synplicity would just map
> it across 3 LUTs.  But if you look at the virtex slice, there is an
> XOR gate that you can route the output of the 2 4-input LUTS to.  If I
> can force the tool to use those resources, then I can fit a 8-input
> XOR in one slice instead of two.
>
> I know this is really low level, but if the hardware is there, why
> waste it?
>
> Thanks,
>
> Jon

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35201
Subject: Re: Xilinx 4.1 software
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Tue, 25 Sep 2001 15:01:45 -0600
Links: << >>  << T >>  << A >>
Hello Tom,

Your speed files for service pack 8 on 3.3i may have been more advanced
than those of 4.1i.  The first service pack for 4.1i contains these same
speed
files.  Did you attempt to run your design with service pack 1 on 4.1i?

This may be the reason you are seeing the discrepancy.
I hope this helps.

Best regards,
Kamal Patel

Tom Brooks wrote:

> So, I installed Xilinx 4.1i software today and
> my results were much worse than with Xilinx
> 3.3i.  I have a 5 ns path that was turned into
> a 7 ns path with the new software.  So, I'm
> going back to 3.3i.


Article: 35202
Subject: FPGA'2002: Paper Deadline Friday
From: tessier@spock.ecs.umass.edu (Russell Tessier)
Date: 25 Sep 2001 21:16:03 GMT
Links: << >>  << T >>  << A >>

Submissions due: September 28, 2001
web site: http://www.ecs.umass.edu/ece/fpga2002


                   FPGA 2002: Call for Papers
Tenth ACM International Symposium on Field-Programmable Gate Arrays

	             Monterey Beach Hotel
                     Monterey, California
                     February 24-26, 2002

Authors are invited to submit English language PDF of their paper 
(12 pages maximum) and panel proposals by September 28, 2001 by 
E-mail to fpga2002@xilinx.com.  Notification of acceptance will 
be sent by November 21, 2001.  

Address questions to:

Steve Trimberger,  Program Chair, FPGA 2002
Email: fpga2002@xilinx.com


Article: 35203
Subject: Re: SmartMedia
From: "Paul J. Menchini" <mench@mench.com>
Date: Tue, 25 Sep 2001 17:24:20 -0400
Links: << >>  << T >>  << A >>
Andrew Gray wrote:

> Does anyone know how to read a file from a SmartMedia card in VHDL?

Since no one else seems to have responded, I'll give it a shot.  Do you
mean "read the file from a piece of hardware written in VHDL", or do you
mean "read the file from a VHDL simulation"?

In the former, you must have an appropriate interface and control logic.

In the latter case, you'll need the appropriate driver for your system
and also must consult with your simulator manual to determine how to
access devices from the simulator.

Or, did I completely misunderstand your question?

Paul



Article: 35204
Subject: WANTED source code of CPLD on TI 5402 DSK
From: pzip007@hotmail.com (BF)
Date: Tue, 25 Sep 2001 23:07:57 GMT
Links: << >>  << T >>  << A >>
I want to build my DSP board based on 5402 DSK so that CCS can work on
it. I got the schematic from the CDROM of CCS, but don't know the
source code of CPLD. Where can I find it?
Thanks.

Article: 35205
Subject: Re: Virtex2 slice level instantiation in verilog question
From: Ray Andraka <ray@andraka.com>
Date: Tue, 25 Sep 2001 23:39:10 GMT
Links: << >>  << T >>  << A >>
see my reply.  I don't believe schematics alone would have made a difference,
here.  You need to use the carry chain primitives, and I am pretty sure the
mapper maps the '1' carry in to a separate LUT, so you end up with 3 LUTs
anyway (It did last year when I was trying to do exactly this for an 8 input
xor).  As it turns out, IIRC the more conventional 3 LUTs (2 layers of logic)
winds up being slightly faster if all LUTs are in the same CLB because of the
delay incurred getting on the carry chain.

These days I am using VHDL with a fair amount of structural instantiation,
much the same way I did schematics.  This gives most of the same advantages,
plus gives you the ability to make a function self sizing and
parameterizable.  Verilog still falls short for this low level work because of
the lack of a generate statement and somewhat clumsy attribute handling (used
for the RLOCs).

Bryan wrote:

> >
> > I know this is really low level, but if the hardware is there, why
> > waste it?
> >
>
> The same question I ask myself every time somebody tries to convince me to
> use verilog instead of schematic capture.
>
> Bryan

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 35206
Subject: Re: comp.arch.fpga : Unusual clock divider ckt
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 26 Sep 2001 02:02:32 GMT
Links: << >>  << T >>  << A >>
On Tue, 25 Sep 2001 09:38:08 -0700, Peter Alfke
<peter.alfke@xilinx.com> wrote:

>
>
>Allan Herriman wrote:
>
>> Note that in no case does the jitter actually get as high as one
>> period of the input clock.
>>
>
>That is in the nature of DDS.
>Max jitter = one clock period.
>If that is acceptable, go for it.

The maximum jitter is always *less than* one clock period for a DDS
with a fixed phase increment value.
However, for a reasonable size of phase accumulator the jitter will
approximate 1 clock period.  This leads to the common misconception
that it is identically equal to one clock period.

I'm being anal again.  Sorry.

Regards,
Allan.

Article: 35207
Subject: Re: Virtex2 slice level instantiation in verilog question
From: hooiwai@yahoo.com (J.Ho)
Date: 25 Sep 2001 19:13:46 -0700
Links: << >>  << T >>  << A >>
Ray,

Thanks for taking your time in sharing your experience.  I did not
realise that XORG printed in the Virtex2 data sheet is actually XORCY,
so I assume that by using XORCY, XORG and GYMUX will be
instantiated/routed as a combo then.

Also thanks for pointing out the "1" (bx/cin)-routing issue, didn't
realise that either, almost got nailed.

I wonder if there is an LOC function that I can specify to pin the
XORCY up top...  After all, the bottom one is called XOR"F" and the
top one is  XOR"G".

Well, yeah, I am trying to squeeze as much out of a small area as
possible.  This portion is slow, so timing would be ok.  I guess for
now I will settle for the two level instantiation.

Jon



Ray Andraka <ray@andraka.com> wrote in message news:<3BB0ED33.E5A24E93@andraka.com>...
> You are talking about the xorcy.  Yes, it can be done but is generally not
> worth the extra effort.  You need to instantiate carry chain components
> muxcy and xorcy to do this.  The muxcy inputs get tied off to 0 and 1 at

Article: 35208
Subject: Re: Xilinx 4.1 software
From: Alan Nishioka <alann@accom.com>
Date: Tue, 25 Sep 2001 19:17:11 -0700
Links: << >>  << T >>  << A >>
But did it get this result twice as fast (as advertised)?

Alan Nishioka
alann@accom.com


Tom Brooks wrote:

> So, I installed Xilinx 4.1i software today and
> my results were much worse than with Xilinx
> 3.3i.  I have a 5 ns path that was turned into
> a 7 ns path with the new software.  So, I'm
> going back to 3.3i.


Article: 35209
Subject: Re: FPGA with embedded Memory
From: "Peter Ormsby" <faepete.deletethis@mediaone.net>
Date: Wed, 26 Sep 2001 03:04:48 GMT
Links: << >>  << T >>  << A >>
Peter Lang <Peter.Lang@rmvmachinevision.de> wrote in message
news:9oq0iu$ia$03$1@news.t-online.com...
> Hello,
> I am looking for an FPGA with embedded Memory.
> There should be 16 times of a 8Kx8 Ram.
> I found the Xilinx XCV812E.
> Does anybody has experience with that chip?
> Is it available now and in future?
> I found a price of about $1000 US.
> Are there any cheaper alternatives?
> thanks
> peter

Altera has the EPXA4 with 128K BYTES of single-ported RAM, 64K BYTES of
dual-ported RAM, and 104 4K bit blocks.  You get an ARM9 processor and about
16,000 LEs with it too.  I'm not sure about the price as the part isn't
quite available yet (the bigger EPXA10 is available today, but that has more
than twice as much memory).  Check with your local rep/distributor for more
info.

-Pete-



Article: 35210
Subject: Handle C
From: akshaymishra@rediffmail.com (Akshay)
Date: 25 Sep 2001 21:11:25 -0700
Links: << >>  << T >>  << A >>
Hi,
    I have no idea of implentation on FPGA's but am interested to
undertake a small project. I have heard about Handle C being an easy
to use HDL (kind of if not exactly a HDL).
    I plan to make a turbo encoder with Handle C. Will it be possible
using Handle C. Can you suggest a good tutorial on Handle C ?

Thanx in advance,
Akshay Mishra.
SPANN Lab.
IIT Bombay.
URL: www.ee.iitb.ac.in/uma/~akshay/

Article: 35211
Subject: Re: fir filter on ASIC
From: kkdeep@mailcity.com (kuldeep)
Date: 25 Sep 2001 22:12:48 -0700
Links: << >>  << T >>  << A >>
thanx robert but unfortunately i cannot change the coefficients to
suit this method :-( so i have to look for some other method. any more
pointers will be appriciated.
--kuldeep


"RM" <yeren@gmx.de> wrote in message news:<9oq2pu$i9q$1@f40-3.zfn.uni-bremen.de>...
> the following reference (you can get more by google'ing with FIR BIT SERIAL
> ftp://ftp.ittc.ukans.edu/pub/projects/DSP/FPGA/Bit_Serial.pdf
> is intended for FPGA use, but it _might_ be suitable for asic, too, because
> it
> is on designs that only include bit shift operations and additions instead
> of
> multiplications. Bad side effect: you will have to calculate a new filter
> that
> meets the restrictions of the method..
> robert
> 
> "kuldeep" <kkdeep@mailcity.com> schrieb im Newsbeitrag
> news:a0f016a9.0109250458.7bb874f1@posting.google.com...
> > i have to implement a 64 tap FIR filter with fixed coefficients in
> > hardware. I have found some architecture suitable for fpga (using LUTs
> > of fpga) which don't use multipliers. can somebody point me to
> > architecture suitable for ASIC?. Since the coefficients are fixed, i
> > want to optimize or avoid the multipliers.The input sample rate is 16
> > MHz with 12 bits (in 2s complement).
> > thanx
> > kuldeep

Article: 35212
Subject: Re: Handle C
From: "Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in>
Date: Wed, 26 Sep 2001 11:18:33 +0530
Links: << >>  << T >>  << A >>
Hi Akshay,
        If you haven't seen this page, see:

http://www.celoxica.com/products/technical_papers/index.htm

There is a tutorial and few papers (some on FPGA implementation as
well). I myself haven't used Handle C and don't intend to either,
b'cos I am big fan of VHDL (and Verilog). Also do a  search on
http://groups.google.com/advanced_group_search with Handle C as key
words and on "comp.arch.fpga" there was a long... thread on this topic
sometime back.

Good Luck.

Srinivasan

"Akshay" <akshaymishra@rediffmail.com> wrote in message
news:937606cb.0109252011.6aef0bf4@posting.google.com...
> Hi,
>     I have no idea of implentation on FPGA's but am interested to
> undertake a small project. I have heard about Handle C being an easy
> to use HDL (kind of if not exactly a HDL).
>     I plan to make a turbo encoder with Handle C. Will it be
possible
> using Handle C. Can you suggest a good tutorial on Handle C ?
>
> Thanx in advance,
> Akshay Mishra.
> SPANN Lab.
> IIT Bombay.
> URL: www.ee.iitb.ac.in/uma/~akshay/

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India (http://www.vlsisrini.com)




Article: 35213
Subject: Virtex 2 : using IOB registers
From: Anand <anand@indranetworks.com>
Date: Wed, 26 Sep 2001 00:37:19 -0700
Links: << >>  << T >>  << A >>
Is there a way to instantiate and use IOB registers for output, input as well as tristate control enable signal from a single IOB ? 

Ive tried the implementation option 'Pack I/O registers for Inputs and Outputs in IOBs' and it dosent seem to work reliably

Article: 35214
Subject: Re: Handle C
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 26 Sep 2001 08:44:58 +0100
Links: << >>  << T >>  << A >>
"Srinivasan Venkataramanan" <svenka3@siliconsystems.co.in> writes:

> Hi Akshay,
>         If you haven't seen this page, see:
> 
> http://www.celoxica.com/products/technical_papers/index.htm
> 
> There is a tutorial and few papers (some on FPGA implementation as
> well). I myself haven't used Handle C and don't intend to either,
> b'cos I am big fan of VHDL (and Verilog). Also do a search on
> http://groups.google.com/advanced_group_search with Handle C as key
> words and on "comp.arch.fpga" there was a long... thread on this topic
> sometime back.

Small point, but worth mentioning if you want to use it as a search
term - the language is spelt "Handel C" (like the composer, not like opening a
door :-)

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Automotive Technical Centre, Solihull, UK

Article: 35215
Subject: Gated clocks and shortage of clock buffers
From: "Harjo Otten" <h.otten@rohill.geen.spam.nl>
Date: Wed, 26 Sep 2001 09:45:09 +0200
Links: << >>  << T >>  << A >>
Hi,

We're creating an PCI interface card that hold 8 serial ports. In my FPGA
desing (Spartan II) I've created two (for every port) three processes. One
that shifts data in, one that shifts data out and one that gets data from
and sends data to the PCI core (Xilinx).

These shifter processes use a clock frequency divided from the 'master
clock'. Now here's my problem: I get a lot of gated clocks when I implement
it like this, but since the frequency is very low (128K max )every thing
works fine. When I try to remove these gated clocks (I'm still not sure on
how to do this, but usually I try to implement clock buffers) I get the
message that there are not enough clock buffers available. I must say that
sounds pretty logical to me since there are only 4 clockbuffers in our
Spartan and at least 9 clocks (one for every port, and one for the master
clock).
Does anybody have any idea on how to remove the gated clocks in this desing,
or should I just ignore them ?? I've seen different comments on gated clock
questions lately, so I'm a bit confused.....

thanx,

H.




Article: 35216
Subject: Re: WANTED source code of CPLD on TI 5402 DSK
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 26 Sep 2001 08:45:56 +0100
Links: << >>  << T >>  << A >>
pzip007@hotmail.com (BF) writes:

> I want to build my DSP board based on 5402 DSK so that CCS can work on
> it. I got the schematic from the CDROM of CCS, but don't know the
> source code of CPLD. Where can I find it?  Thanks.

It may or may not help, but I found some ABEL code for the 6711 DSK
CPLD on the CD somewhere.

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Automotive Technical Centre, Solihull, UK

Article: 35217
Subject: Re: Virtex 2 : using IOB registers
From: Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore>
Date: Wed, 26 Sep 2001 10:44:57 +0200
Links: << >>  << T >>  << A >>
Anand wrote:

> Is there a way to instantiate and use IOB registers for output, input as well as tristate control enable signal from a single IOB ?
>
> Ive tried the implementation option 'Pack I/O registers for Inputs and Outputs in IOBs' and it dosent seem to work reliably

I made finally yesterday :-)   :

http://d6.design.chalmers.se/jctmp/jctmp/iob.vhd
and
http://d6.design.chalmers.se/jctmp/jctmp/constraints.ucf

Go to the answer data base of Xilinx, answer record #2207 tells you all you need.
The -pr b option of map can be switched on in the dialog before
implementaion.  If you use the ucf file, you don't need it anyway.
(please don't take the usage of the three BUFGs "enableBuf0_0 enableBuf1_0
and tristateBuf too serious, my problem is that all these signals have
to drive around 64 devices. I tried to dublicate the driver, but I don't know
how to tell the synthesis toll not to remove the duplicate logic)

-jc-


Article: 35218
Subject: how to dublicate logic?
From: Jens-Christian Lache <lache@tu-harburg.de_removeTheUnderscore>
Date: Wed, 26 Sep 2001 10:49:51 +0200
Links: << >>  << T >>  << A >>
Hi!
To reduce the fanout of a tristate signal leading to 64 iobs I
tried dublicate this signal. How do I tell
the synthesis tool now not to remove my dublicated logic?
( I tried to use a BUFG as well, but that didn't work at all)
thanks for your help,
-jc-


Article: 35219
Subject: Re: FPGA with embedded Memory
From: "Peter Ormsby" <faepete.deletethis@mediaone.net>
Date: Wed, 26 Sep 2001 11:54:45 GMT
Links: << >>  << T >>  << A >>

Peter Ormsby <faepete.deletethis@mediaone.net> wrote in message
news:kBbs7.26913$Q6.1418489@typhoon.mn.mediaone.net...
> Peter Lang <Peter.Lang@rmvmachinevision.de> wrote in message
> news:9oq0iu$ia$03$1@news.t-online.com...
> > Hello,
> > I am looking for an FPGA with embedded Memory.
> > There should be 16 times of a 8Kx8 Ram.
> > I found the Xilinx XCV812E.
> > Does anybody has experience with that chip?
> > Is it available now and in future?
> > I found a price of about $1000 US.
> > Are there any cheaper alternatives?
> > thanks
> > peter
>
> Altera has the EPXA4 with 128K BYTES of single-ported RAM, 64K BYTES of
> dual-ported RAM, and 104 4K bit blocks.  You get an ARM9 processor and
about
> 16,000 LEs with it too.  I'm not sure about the price as the part isn't
> quite available yet (the bigger EPXA10 is available today, but that has
more
> than twice as much memory).  Check with your local rep/distributor for
more
> info.
>
> -Pete-

Oops:  The EPXA4's smaller blocks are actually only 2K bits in size, rather
than the 4K bit size I stated above.  Sorry about the mistake.

-Pete-



Article: 35220
Subject: Re: Virtex II current consumption
From: Patrick Hibbs <phibbs@ti.com>
Date: Wed, 26 Sep 2001 08:22:50 -0500
Links: << >>  << T >>  << A >>
I have to admit ... your numbers seem a little high.
The current consumption will (obviously) depend on what
you've implemented -- clock frequency, % utilized, toggle 
rate, etc.  Make sure you haven't made any (large) generalizations
in the spreadsheet.

I can tell you that I've commonly seen 5 to 6 watts with 
the XCV2000E(1.8v core) (apples vs oranges :~( ).

Also, I've killed a few 2000E's by starving them of current.
Make sure to have voltage regulators that can handle the 
current demands.

Pat

Jonas Weiss wrote:
> 
> Good morning everybody,
> I'm developping a PC card with 2x XC2V1000 (optionally XC2V3000) on it.
> I extrapolated the results of an old run of XILINXs power estimator
> excel sheet which results in a rather high current for the 1.5V core
> supply of roughly 16A (8Amps each).
> If anybody has experience on powering these devices, could you confirm
> such a high current consumption?
> 
> Thanks a lot.
> 
> Jonas

Article: 35221
Subject: Re: Logical constraints of LUT
From: Patrick Hibbs <phibbs@ti.com>
Date: Wed, 26 Sep 2001 08:25:37 -0500
Links: << >>  << T >>  << A >>

You'll have to re-instantiate with the block rams.
Make sure to use the floorplanner if you're concerned
with placement.

Pat

Noddy wrote:
> 
> Hi,
> 
> I was wondering how/if it were possible to make a distributed memory LUT
> created as an RPM to be placed within the RAM memory blocks of a Spartan II.
> Each LUT is 128 deep, 8 bit wide.
> 
> adrian

Article: 35222
Subject: Re: How does Altera FLEX 10k communicate with PC?
From: Armin Mueller <armin.mueller@stud.uni-karlsruhe.de>
Date: Wed, 26 Sep 2001 15:42:45 +0200
Links: << >>  << T >>  << A >>
Ru-Chin Tsai wrote:

> But how can I let FLEX 10k to communicate with PC?
> Which interface should I choice(ISA or PCI or others)?
> Does any exist PCI or ISA interface Soft-IP I can get?

Depends on you. ISA is easy but rather slow. PCI doesn't
even fit in a 10K10 part, whatever you use.

Armin

Article: 35223
Subject: Re: Gated clocks and shortage of clock buffers
From: NotMe <not-given@invalid.com>
Date: Wed, 26 Sep 2001 13:43:14 GMT
Links: << >>  << T >>  << A >>
Clock gating's largest benefit is to reduce power consumption in 
silicon.  If you are on PCI and in an FPGA this does not matter to you.

What the FPGA wants you to do is to have a single clock from which all 
your FFs are clocked.  When a particular part of your design is waiting 
out time because you need to run at a lower frequency, it arranges to 
clock the Q of those flipflops back into the D, ie, it works like a 
clock enable input while you wait.

Your life becomes much simpler both in silicon and FPGA designs if you 
worship the God of Synchronous Design like this and try to keep to just 
the one clock, using clock enable type logic where necessary.


|Hi,
|
|We're creating an PCI interface card that hold 8 serial ports. In my 
FPGA
|desing (Spartan II) I've created two (for every port) three processes. 
One
|that shifts data in, one that shifts data out and one that gets data 
from
|and sends data to the PCI core (Xilinx).
|
|These shifter processes use a clock frequency divided from the 'master
|clock'. Now here's my problem: I get a lot of gated clocks when I 
implement
|it like this, but since the frequency is very low (128K max )every 
thing
|works fine. When I try to remove these gated clocks (I'm still not sure 
on
|how to do this, but usually I try to implement clock buffers) I get the
|message that there are not enough clock buffers available. I must say 
that
|sounds pretty logical to me since there are only 4 clockbuffers in our
|Spartan and at least 9 clocks (one for every port, and one for the 
master
|clock).
|Does anybody have any idea on how to remove the gated clocks in this 
desing,
|or should I just ignore them ?? I've seen different comments on gated 
clock
|questions lately, so I'm a bit confused.....
|
|thanx,
|
|H.
--
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Article: 35224
Subject: Pentium 3 vs Pentium 4 benchmarks
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 26 Sep 2001 14:55:22 +0100
Links: << >>  << T >>  << A >>
After the recent discussions on performance of Pentium4 and Athlon
based systems, I decided to do some benchmarking.  Not having an
Athlon, I tested my current box and a P4 box we have around the place.
I'm hoping to get an Athlon on loan to test as well...

Main tests run were:
 o HDL compile (Modelsim PE5.5)
 o HDL simulate (Modelsim PE5.5)
 o Synthesis (Synplify 6.2.4)
 o Place and Route (Altera Max Plus 2 10.1)

All on a current design of mine which is 64% of LEs and ~50% of EABs
in a FLEX10K100E.

For interest I also ran a couple of PCB autorouting tests of the board
this FPGA is on.

The two test systems were:
System 1: Pentium 3,  800MHz,  512MB PC100 SDRAM
System 2: Pentium 4, 1700MHz, 1024MB PC800 RDRAM

Results, all times in hours:minutes:seconds
Benchmark	System 1   System 2	% increase {=(2-1)/1}
PCB fanout	0:00:49	   0:00:37	124%	
PCB route	0:13:08	   0:12:04	108%	
HDL compile	0:02:23	   0:01:43	128%	
HDL simulate	0:04:31	   0:03:38	120%	
Synthesis	0:01:19	   0:01:16	104%	
P&R		0:06:25	   0:05:54	108%	
Mean					115%	

Certainly isn't much on the synth/P&R times, or my PCB routing.
Interestingly, system 1's processor meter was pegged at 100% all
through the routing, but system 2 dropped to 98% or 99% occasionally -
maybe due to the CPU having to wait for data due to RAMBUS latency?

Comments or requests for more detail (if I can!) welcome....

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Automotive Technical Centre, Solihull, UK




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