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Messages from 36400

Article: 36400
Subject: Hex numbers in VHDL
From: "Andrew Gray" <andrewgray@iafrica.com>
Date: Thu, 8 Nov 2001 12:27:16 +0200
Links: << >>  << T >>  << A >>
Hi

Is it possible to initialise a std_logic_vector using a hex number instead
of a binary one?

e.g.
temp <= "0x0F0F"
instead of
temp <=  "0000111100001111"

or in an array:
array_x_y:=(("0x0F","0xF0"),("0x55","0xAA"));
instead of
array_x_y := (("00001111","11110000"),("01010101","10101010"));

Thanks

Andrew



Article: 36401
Subject: VHDL testbench question
From: "Andrew Gray" <andrewgray@iafrica.com>
Date: Thu, 8 Nov 2001 12:30:04 +0200
Links: << >>  << T >>  << A >>
Hi

Is it possible to read a data file into a test bench and use it as one of
the data inputs to your design?
Is it possible to write from one of the outputs of your design into a file?

Thanks

Andrew



Article: 36402
Subject: Re: Question about pipelining a design
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 08 Nov 2001 21:34:17 +1100
Links: << >>  << T >>  << A >>
The Ashendon vhdl book describes pipelining, and others would too.

In a process, you have:

process
begin
  reg1_in<=func1(data_in);
  reg2_in<=func2(reg1_out);
  reg3_in<=func2(reg2_out);
  data_out<=func3(reg3_out);

wait until rising_edge(clk);
  reg1_out<=reg1_in;
  reg2_out<=reg2_in;
  reg3_out<=reg3_in;
end process;



Marty wrote:
> 
> I am working on a waveform generator that gets data from a dual-port RAM,
> and outputs it. It also has timing and jump instructions in the RAM data.
> The goal is to run at 50 MHz.  The RAM, is 64K deep, and 15 nS access time.
> 
> I can get the machine to simulate at 33 MHz, but not at 50 MHz.  I think the
> way to solve this is to redesign the machine in a pipelined form.
> I have fit the non pipelined design into an Altera 7512AE.
> Some of the problems are getting the machine to do relative jumps - absolute
> jumps work.
> 
> Does anyone know of any tools to help visualize or design a project like this?
> 
> Marty

Article: 36403
Subject: Re: Hex numbers in VHDL
From: "Panu H" <panuh[@]cs.tut.fi>
Date: Thu, 8 Nov 2001 12:46:44 +0200
Links: << >>  << T >>  << A >>
"Andrew Gray" <andrewgray@iafrica.com> wrote in message
news:3bea6077.0@news1.mweb.co.za...
> Is it possible to initialise a std_logic_vector using a hex number instead
> of a binary one?
>
> e.g.
> temp <= "0x0F0F"
> instead of
> temp <=  "0000111100001111"

I think it depends a bit on the used development framework. This should
work:

temp <= To_UX01(x"0F0F"); (or sometimes just temp <= x"0F0F";)

I haven't tried it on arrays.

-- Panu





Article: 36404
Subject: Re: Virtex2 gate-level simulation: SDF and timing errors
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Thu, 08 Nov 2001 10:49:34 GMT
Links: << >>  << T >>  << A >>
On 7 Nov 2001 22:06:31 -0800, assaf_sarfati@yahoo.com (Assaf Sarfati)
wrote:

>allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3be88ba4.6211972@netnews.agilent.com>...
>> On 6 Nov 2001 06:42:09 -0800, assaf_sarfati@yahoo.com (Assaf Sarfati)
>> wrote:
>> 
>> >Hi everyone,
>> >
>> >I am trying to simulate the gate-level VHDL file generated by Xilinx
>> >P&R tools. My test design is a bunch of counters connected to an 
>> >inferred distributed-RAM. The target device is a Virtex-2 chip.
>> >
>> >When I simulate the gate-level VHDL by itself, I get timing violation 
>> >warnings (sometimes) when writing to the distributed-RAM; watching the
>> >simulator waveforms, it appears that the clock to the RAM has a 100-pS
>> >phase difference to the counters' clock (the clock is routed as a 
>> >global clock net).
>> >
>> >When I add the gate-level SDF file to the simulation, all the timing
>> >violation warnings disappear (for all cases: min, max and typ).
>> >
>> >Trying to trace the generated VHDL code, I see that signals are routed
>> >through buffer entities, with built-in delays; apparently the VHDL
>> >design itself contains all required delays.
>> >
>> >Why would adding the SDF to the simulation make errors _disappear_? 
>> >it should be a more thorogh timing-check and find _more_ timing
>> >errors.
>> >
>> >Can anyone explain?
>> 
>> There are clock delays built in to the simprim (& unisim) components
>> that are present regardless of whether you use the SDF.  These delays
>> can cause hold time problems, and using the SDF will delay the data
>> signals sufficiently to avoid the hold time issues.
>> 
>> You can disable these delays in your simulator.  (If using Modelsim,
>> try vsim +notimingchecks)
>> 
>> Regards,
>> Allan.
>
>Aren't there also delays built-in for the data signals in the
>time_sim.vhd file? 

You say you looked at the generated gate level VHDL file (I assume
that's what you mean by "time_sim.vhd") and saw delays in the VHDL.

I'm using Alliance 3.x, and there are no delays in the code generated
by ngd2vhdl, and the documentation doesn't describe any options for
adding delays.

Are you sure you are looking at the file generated by ngd2vhdl and not
some other tool (such as your VHDL synthesiser)?

>(BTW, I use Active-HDL; I haven't tried to find
>how to disable timing checks - I've seen that I can modify a constant
>in the Virtex library source to disable these checks, if they become
>too nagging).

What is the "Virtex library source?"  Do you mean the simprim or
unisim source?  If so, I don't recommend changing it.  Your changes
may be lost when you install a service pack.

Regards,
Allan.

Article: 36405
Subject: Re: Hex numbers in VHDL
From: Alan Fitch <alan.fitch@doulos.com>
Date: Thu, 8 Nov 2001 11:00:14 +0000
Links: << >>  << T >>  << A >>
In article <3bea6077.0@news1.mweb.co.za>, Andrew Gray
<andrewgray@iafrica.com> writes
>Hi
>
>Is it possible to initialise a std_logic_vector using a hex number instead
>of a binary one?
>
>e.g.
>temp <= "0x0F0F"
>instead of
>temp <=  "0000111100001111"
>
>or in an array:
>array_x_y:=(("0x0F","0xF0"),("0x55","0xAA"));
>instead of
>array_x_y := (("00001111","11110000"),("01010101","10101010"));
>
>Thanks
>
>Andrew
>
>
Yes it is, in VHDL 93 only. You can say

temp <= X"0F0F";

and similarly for your array.

There's a couple of features 

  - you can use underscores in the literal for readability
  - you can specify O for octal, B for binary instead of the X if you
want to

and there's a "negative" feature

 - the literal (using X for hex) can only be a multiple of 4 bits wide
 - it won't work on std_logic_vector in VHDL87 (though it will work on
bit_vector)

regards

Alan

-- 
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                           Email: alan.fitch@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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                   **********************************

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Article: 36406
Subject: Re: VHDL testbench question
From: "Srinivasan Venkataramanan" <srinivasan@siliconsystems.co.in>
Date: Thu, 8 Nov 2001 17:19:47 +0530
Links: << >>  << T >>  << A >>
Hi,
    As this is a very FAQ, see FAQ @
http://www.eda.org/comp.lang.vhdl/FAQ1.html

About your HEX no. use VHDL'93 and

slv <= X"FF";

HTH,
Srinivasan
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)


"Andrew Gray" <andrewgray@iafrica.com> wrote in message
news:3bea607c.0@news1.mweb.co.za...
> Hi
>
> Is it possible to read a data file into a test bench and use it as
one of
> the data inputs to your design?
> Is it possible to write from one of the outputs of your design into
a file?
>
> Thanks
>
> Andrew
>
>



Article: 36407
Subject: ITU G.273.1 Codec in Virtex XCV400E ?
From: Francisco Camarero <francisco.camarero@acterna.com>
Date: Thu, 08 Nov 2001 13:20:51 +0100
Links: << >>  << T >>  << A >>


Hello!

  This is a question about planing. How long would you
estimate that is needed, and what kind of tools are the
best to implement a ITU G.273.1 CODEC (VoIP) in a 
Virtex XCV400E ?

Thanks!

Article: 36408
Subject: Re: Quadrature Encoder Sampling Time
From: Falser Klaus <kfalser@IHATESPAMdurst.it>
Date: Thu, 8 Nov 2001 13:59:37 +0100
Links: << >>  << T >>  << A >>
In article <385a6ee1.0111071641.6fe7244b@posting.google.com>, anon7864
@hushmail.com says...
... 
> I am trying to deduce the minimal sampling rate for a hand-turned knob
> that is a 2 channel, 16 position device. 
...
> 
> The spec sheet on the encoders we use says that the maximum RPM is
> 100. A call to the factory reveals that: "Encoder section - 300 RPM
> max, average manual operation is in the range of 1 to 16 RPM max.
> ...tested (Per MIL-3786/39) @rate of 10 cycles per miv, which is 20
> RPM (One cycle is a rotation thru all positions and full return.)"
> 
....
> position_time=200ms/16positions=13msec
> 
> Shannon's theorem says that scan_rate=13msec/2=6msec (round down)
....

First, if 16 position means that one quadrature signal cycles 16 times 
per revolution, you need to double your sampling rate since the other 
quadrature signal is shifted by 90 degrees (you need at least 4 sampling 
point per cycle).

I would however recommend to sample the signals at 10 to 20 times of 
their cycling rate. In your case it should not make a big difference 
if you sample you signal at 10 KHz instead of 1KHz or 500 Hz.

Don't forget that the quadrature signals are asynchronous to your clock. 
You have to add a synchronizer to avoid metastability before 
you feed the quadrature signals to the FSM.  
Adding a digital filter would be even better.

Hope this helps

-- 
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMEdurst.it

Article: 36409
Subject: Maxplus error
From: "Andrew Gray" <andrewgray@iafrica.com>
Date: Thu, 8 Nov 2001 15:28:19 +0200
Links: << >>  << T >>  << A >>
Hi I declared a VHDL array in Maxplus as follows:

type nik_table_i  is array (0 to 63) of std_logic_vector(23 downto 0);

constant Ni0 : nik_table_i :=
("000010110101000001001111","000010101011111010110100","00001010001001100111
1001","000010011000011111111011",
"000010001110001110011101","000010000011100111000011","000001111000101011010
111","000001101101011101000100",
"000001100001111101111000","000001010110001111100110","000001001010010100000
001","000000111110001100111111",
"000000110001111100010111","000000100101100100000010","000000011001000101111
010","000000001100100011111011",
"000000000000000000000000","111111110011011100000101","111111100110111010000
110","111111011010011011111110",
"111111001110000011101001","111111000001110011000001","111110110101101011111
111","111110101001110000011010",
"111110011110000010001000","111110010010100010111100","111110000111010100101
001","111101111100011000111101",
"111101110001110001100011","111101100111100000000101","111101011101100110000
111","111101010100000101001100",
"111101001010111110110001","111101000010010100010001","111100111010000111000
000","111100110010011000010000",
"111100101011001001001101","111100100100011010111111","111100011110001110100
111","111100011000100101000011",
"111100010011011111001011","111100001110111101110000","111100001011000001100
000","111100000111101011000001",
"111100000100111010110101","111100000010110001010110","111100000001001110111
010","111100000000010011110000",
"111100000000000000000000","111100000000010011110000","111100000001001110111
010","111100000010110001010110",
"111100000100111010110101","111100000111101011000001","111100001011000001100
000","111100001110111101110000",
"111100010011011111001011","111100011000100101000011","111100011110001110100
111","111100100100011010111111",
"111100101011001001001101","111100110010011000010000","111100111010000111000
000","111101000010010100010001");


when I tried to compile I got the following error:

Unsupported feature error: aggregates are supported only for types that map
to an array of bits.

Does any one know how to fix this

Thanks

Andrew



Article: 36410
Subject: Re: FPGA BGA and decoupling
From: Keith R. Williams <krw@btv.ibm.com>
Date: Thu, 8 Nov 2001 08:45:16 -0500
Links: << >>  << T >>  << A >>
In article <3BE9A5FE.BD8E9F26@flukenetworks.com>, 
mike.treseler@flukenetworks.com says...
> "Keith R. Williams" wrote:
> 
> > > On the back side of the board.
> > > Make an GND rectangle on the bottom layer.
> > > Make a rectangular VCC ring enclosing it.
> > > Surface mount capacitors straddle the gap.
> > 
> > Ok, a couple more questions about this.
> > 
> > -  How to connect these rings to the VCC/Gnd planes?  I'd assume there
> > would have to be a *lot* of vias to the appropriate planes.
> 
> One via per ball on the perimeter.
>  
> > -  What about multiple I/O technologies?  The Virtex-E (FG680) design I
> > did used four I/O voltages.  Partial "rings" opposite the banks?  that
> > still leaes two rings for VIO and Vcore.
> 
> Sound reasonable to me.

Sounds ugly to me. ;-)
> 
> > -  Do the tools used to place the capacitors like the rings?  I thought
> > they wanted islands such that the surface tension of the melted solder
> > automagically positioned the caps.
> 
> You lay the caps parallel in the gap, not on the ring.

How about the lateral position?  It was my understanding that the 
pads/solder centered the components in both axis. Obvioulsy I haven't 
done this, but I would think you'd give up lateral position accuracy 
the process.

> > -  This strategy would seem to eliminate one I/O plane since the
> > decoupling ring isolates the I/O.  Is there another trick here? I'd
> > hate to make the back a ground plane.  It makes ECs harder. ;-)
> 
> You need 10 layers to handle the IOs on a big BGA.
> Yes, the real planes are internal layers.

Sure, I already use ten planes (five power) on the Virtex-E design.  
Adding solid rings to the back for decoupling would eliminate one of my 
signal planes.  Though it's not a high speed plane it is still useful.

> > It still seems the caps are a good distance from the center pins.  The
> > center of the FG680 package made a very good place to pack with caps
> > (and terminators).
> 
> I expect that the GND and power planes make the exact
> cap position much less critical than in the two-layer TTL days.

When were these days?  ;-)  Even in the TTL days I used a minimum of 
four and more often six or eight planes.

----
  Keith 

Article: 36411
Subject: Re: FPGA Wish list
From: Reinoud <dus@wanabe.nl>
Date: Thu, 08 Nov 2001 14:23:24 GMT
Links: << >>  << T >>  << A >>
Rob Finch wrote:
> I've have thought it through more carefully and realized it just doesn't
> make sense to provide on chip dram. Once again I have posted something and
> regretted it. I've managed to prevent myself from posting most of my dumb
> ideas, but this one escaped me. Sorry.

It's not a dumb idea at all.  There are applications that benefit
hugely from on-chip DRAM, because of the reduced latency, the much
higher bandwidth that can be achieved, and reduced board size and
cost.  An obvious example is integrated frame buffer / texture cache
on a (3D) graphics chip.  So please don't regret posting this idea,
the combination with an FPGA is interesting and merits discussion.

That said, I completely agree with Peter Alfke that it is not
practical to embed DRAM on commodity FPGAs at this point in time. I
would even add arguments to his list: DRAM is noise and temperature
sensitive, unreliable, and a bitch to test; this would seriously
reduce reliability of the FPGA under many circumstances.  Hey, it's
hard enough already to keep them up and running :-).  Also, the
number of applications that would benefit from the on-chip DRAM is
limited.  So yes, SRAM is the way to go for now.

Regards,

- Reinoud

Article: 36412
Subject: Re: How dense are FPGA/CPLD's
From: Ray Andraka <ray@andraka.com>
Date: Thu, 08 Nov 2001 14:40:22 GMT
Links: << >>  << T >>  << A >>
THat's pretty funny coming from Altera.  If you look at the routing structure of an Altera FPGA, it
looks remarkably CPLD-like.  I think a better definition would focus on the structure of the logic
elements.  FPGAs tend to have small logic elements, typically 4 inputs where CPLDs tyupically have
fairly wide and-or structures reminiscent of the original MMI PALs

Russell Shaw wrote:

>
> There's a .pdf on the altera site that categorizes FPGAs as things
> with segmented interconnects, whereas CPLDs don't have segments,
> making routing easier.
>
>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36413
Subject: Re: count and divide Idea needed
From: Ray Andraka <ray@andraka.com>
Date: Thu, 08 Nov 2001 14:43:55 GMT
Links: << >>  << T >>  << A >>
It would help if you posted the error message.  I don't see the error, but
they don't always jump out at me out of context.

Banana wrote:

> I implement your code in this way :
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity raycounter3 is
>         port(clk                :       in std_logic   ;
>                  clk33                  :       out std_logic  ;
>                  count_output   :       out std_logic_vector(1 downto 0)
>                  );
> end raycounter3;
>
> architecture raycounter3_arch of raycounter3 is
> begin
>         signal cnt              :       std_logic_vector(1 downto 0);
>         signal cnt0_fe  :       std_logic;
>         begin
>                 process(clk)
>                 begin
>                 if clk'event and clk='1' then
>                         cnt<= cnt(0) & not(cnt(0) or cnt(1));
>                 end if;
>                 end process;
>
>                 process(clk)
>                 begin
>                 if clk'event and clk='0' then
>                         cnt0_fe<=cnt(0);
>                 end if;
>                 end process;
>
>                 count_output<=cnt;
>                 clk33<=cnt(0) or cnt0_fe;
>         end;
> end raycounter3_arch ;
>
> but seems there's an error in the first instruction
>         signal cnt              :       std_logic_vector(1 downto 0);
>
> what you think about ??

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36414
Subject: Re: about ise4.1 solaris install
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Thu, 08 Nov 2001 08:13:33 -0700
Links: << >>  << T >>  << A >>
Hello,

You may want to try this command prior to installation:

unsetenv LANG

Regards,
Kamal Patel

wrth wrote:

> when i install ISE4.1 for Solaris7,it says:
> Exception occurred during event dispatching:
> java.util.MissingResourceException: can't find resource for ResourceBundle_zh_CN
>         at java.lang.Throwable.<init>(Compiled Code)
>         at java.lang.Exception.<init>(Compiled Code)
>         at java.lang.RuntimeException.<init>(Compiled Code)
>         at java.util.MissingResourceException.<init>(Compiled Code)
>         at java.util.ResourceBundle.getBundle(Compiled Code)
>         at java.util.ResourceBundle.getBundle(Compiled Code)
>         at com.xilinx.install.QuestionDialog.getString(Compiled Code)
>         at com.xilinx.install.QuestionDialog.<init>(Compiled Code)
>         at com.xilinx.install.QuestionDialog.<init>(Compiled Code)
>         at com.xilinx.install.setup.storeDD(Compiled Code)
>         at com.xilinx.install.setup.panel5Nextbutton_MouseClicked(Compiled Code)
>         at com.xilinx.install.setup$SymMouse.mouseClicked(Compiled Code)
>         at java.awt.Component.processMouseEvent(Compiled Code)
>         at java.awt.Component.processEvent(Compiled Code)
>         at java.awt.Button.processEvent(Compiled Code)
>         at java.awt.Component.dispatchEventImpl(Compiled Code)
>         at java.awt.Component.dispatchEvent(Compiled Code)
>         at java.awt.EventDispatchThread.run(Compiled Code)


Article: 36415
Subject: Re: How dense are FPGA/CPLD's
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 08 Nov 2001 16:02:19 GMT
Links: << >>  << T >>  << A >>


Russell Shaw wrote:

>
> There's a .pdf on the altera site that categorizes FPGAs as things
> with segmented interconnects, whereas CPLDs don't have segments,
> making routing easier.

Beware of marketing fluff.
They just wanted to indicate a distinction from Xilinx, while the two companies were embroiled in a
patent war.
"If it looks like an FPGA, behaves like an FPGA, is generally considered to be an FPGA", then they
might as well call it an FPGA, and admit that they copied the Xilinx concept.
Well, the patent fight is settled. Altera paid up, and perhaps they will now use a more reasonable
nomenclature.

Peter Alfke


Article: 36416
Subject: Re: Virtex2 gate-level simulation: SDF and timing errors
From: Ray Andraka <ray@andraka.com>
Date: Thu, 08 Nov 2001 16:12:36 GMT
Links: << >>  << T >>  << A >>
Allan,

There is a generic in the unisims, TimingChecksOn I think it is, that I set to false.  Doing that disables the timing
checks, and more importantly the delays in the functional simulations with unisims.  WIthout disabling that, I've had
problems in designs that have a mix of instantiated flip-flops and inferred ones where one or the other clocks in the new
data on the same clock edge it is changing on in the driving function.  I suspect that generic is what he is talking about.

Allan Herriman wrote:

> On 7 Nov 2001 22:06:31 -0800, assaf_sarfati@yahoo.com (Assaf Sarfati)
> wrote:
>
> >allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3be88ba4.6211972@netnews.agilent.com>...
> >> On 6 Nov 2001 06:42:09 -0800, assaf_sarfati@yahoo.com (Assaf Sarfati)
> >> wrote:
> >>
> >> >Hi everyone,
> >> >
> >> >I am trying to simulate the gate-level VHDL file generated by Xilinx
> >> >P&R tools. My test design is a bunch of counters connected to an
> >> >inferred distributed-RAM. The target device is a Virtex-2 chip.
> >> >
> >> >When I simulate the gate-level VHDL by itself, I get timing violation
> >> >warnings (sometimes) when writing to the distributed-RAM; watching the
> >> >simulator waveforms, it appears that the clock to the RAM has a 100-pS
> >> >phase difference to the counters' clock (the clock is routed as a
> >> >global clock net).
> >> >
> >> >When I add the gate-level SDF file to the simulation, all the timing
> >> >violation warnings disappear (for all cases: min, max and typ).
> >> >
> >> >Trying to trace the generated VHDL code, I see that signals are routed
> >> >through buffer entities, with built-in delays; apparently the VHDL
> >> >design itself contains all required delays.
> >> >
> >> >Why would adding the SDF to the simulation make errors _disappear_?
> >> >it should be a more thorogh timing-check and find _more_ timing
> >> >errors.
> >> >
> >> >Can anyone explain?
> >>
> >> There are clock delays built in to the simprim (& unisim) components
> >> that are present regardless of whether you use the SDF.  These delays
> >> can cause hold time problems, and using the SDF will delay the data
> >> signals sufficiently to avoid the hold time issues.
> >>
> >> You can disable these delays in your simulator.  (If using Modelsim,
> >> try vsim +notimingchecks)
> >>
> >> Regards,
> >> Allan.
> >
> >Aren't there also delays built-in for the data signals in the
> >time_sim.vhd file?
>
> You say you looked at the generated gate level VHDL file (I assume
> that's what you mean by "time_sim.vhd") and saw delays in the VHDL.
>
> I'm using Alliance 3.x, and there are no delays in the code generated
> by ngd2vhdl, and the documentation doesn't describe any options for
> adding delays.
>
> Are you sure you are looking at the file generated by ngd2vhdl and not
> some other tool (such as your VHDL synthesiser)?
>
> >(BTW, I use Active-HDL; I haven't tried to find
> >how to disable timing checks - I've seen that I can modify a constant
> >in the Virtex library source to disable these checks, if they become
> >too nagging).
>
> What is the "Virtex library source?"  Do you mean the simprim or
> unisim source?  If so, I don't recommend changing it.  Your changes
> may be lost when you install a service pack.
>
> Regards,
> Allan.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36417
Subject: Re: Can I enhance this Counter 4 and Counter 6 ???
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 8 Nov 2001 17:59:35 +0100
Links: << >>  << T >>  << A >>

"Banana" <cappellainfuocata@yahoo.it> schrieb im Newsbeitrag
news:d23ae64d.0111072310.5a688c42@posting.google.com...
> I need a counter that counts 0 , 1 , 2 , 3 and also divide the
> incoming clock by four,

???
A counter with the sequence 0,1,2,3, does already dive the incomming clock
by 4. Its the same. And it takes just 2 FFs and a carry chain (is
practically free).

> for this I use the following code , my question is that there is a
> more simple way to do the
> same, in any case something that give it more speed and less area. I
> don't want to use DLL.

Even the smallest FPGA has 2 free FFs for that counter ;-)

> By the way I use a really similar code to obtain the same with a
> counter modulo 6
> In that case this is the code , the question is the same, what about
> the answer ??

The same, the mod 6 counter takes 2 FFs and 3 LUTs, not wot wort to cry.

--
MfG
Falk




Article: 36418
Subject: Re: Can Xilinx recognize the critical path in the design
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 8 Nov 2001 18:02:12 +0100
Links: << >>  << T >>  << A >>

"Kuan Zhou" <zhouk@rpi.edu> schrieb im Newsbeitrag
news:Pine.SOL.3.96.1011108021708.6365A-100000@rcs-sun1.rcs.rpi.edu...
> Hi,
>    I did a fir design but don't know what's the critical
> path in my design.Can Xilinx tool has someway to mesure and
> recognize it?

Depends on your definition of "critical". The tools can "only" find the path
with the longest delay in a synchronous design. What they cant do, is to
look for bad design style (except detecting gated clocks or so).

--
MfG
Falk





Article: 36419
Subject: Xilinx dedicated IO pins
From: "jakab tanko" <jtanko@ics-ltd.com>
Date: Thu, 8 Nov 2001 12:10:34 -0500
Links: << >>  << T >>  << A >>
Hi all,

Could somebody please tell me how to prevent the xlnx P&R
tool (Alliance 3.1i) from assigning the dedicated pins on a spartan2
(D0/DIN,
BUSY/DOUT ..etc) to user IO, I want to keep the dedicated
pins dedicated...I spent the better part of the day searching the
xlnx site but got nowhere
Thanks,
jakab



Article: 36420
Subject: Re: Hex numbers in VHDL
From: "Tony Benham" <tonyb@nospam.kerrisway.freeserve.co.uk>
Date: Thu, 8 Nov 2001 17:14:46 -0000
Links: << >>  << T >>  << A >>
I deal in digital video which uses 10 bit vectors. I often want to assign a
hex no to a 10 bit slv, but I've not found a neat way of doing it. VHDL 93
supports this for slv's that are multiples of 4 bits, but seems to not deal
with other nos of bits. Is there any way of dealing wth this ? ie I want to
do "slv(9 DOWNTO 0) <= Hex 3AC ;" in effect ?
Cheers
Tony

"Alan Fitch" <alan.fitch@doulos.com> wrote in message
news:tycOpJA+Wm67YBr0@doulos.co.uk...
> In article <3bea6077.0@news1.mweb.co.za>, Andrew Gray
> <andrewgray@iafrica.com> writes
> >Hi
> >
> >Is it possible to initialise a std_logic_vector using a hex number
instead
> >of a binary one?
> >
> >e.g.
> >temp <= "0x0F0F"
> >instead of
> >temp <=  "0000111100001111"
> >
> >or in an array:
> >array_x_y:=(("0x0F","0xF0"),("0x55","0xAA"));
> >instead of
> >array_x_y := (("00001111","11110000"),("01010101","10101010"));
> >
> >Thanks
> >
> >Andrew
> >
> >
> Yes it is, in VHDL 93 only. You can say
>
> temp <= X"0F0F";
>
> and similarly for your array.
>
> There's a couple of features
>
>   - you can use underscores in the literal for readability
>   - you can specify O for octal, B for binary instead of the X if you
> want to
>
> and there's a "negative" feature
>
>  - the literal (using X for hex) can only be a multiple of 4 bits wide
>  - it won't work on std_logic_vector in VHDL87 (though it will work on
> bit_vector)
>
> regards
>
> Alan
>
> --
> Alan Fitch
> DOULOS Ltd.
> Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United
Kingdom
> Tel: +44 1425 471223                           Email:
alan.fitch@doulos.com
> Fax: +44 1425 471573                             Web:
http://www.doulos.com
>
>                    **********************************
>                    **  Developing design know-how  **
>                    **********************************
>
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reserves
> all rights of privilege in  respect thereof. It is intended for the  use
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> the addressee only. If you are not the intended  recipient please delete
it
> from  your  system, any  use, disclosure, or copying  of this  document
is
> unauthorised. The contents of this message may contain personal views
which
> are not the views of Doulos Ltd., unless specifically stated.
>
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>



Article: 36421
Subject: Re: Hex numbers in VHDL
From: Tim Hubberstey <sendme@no.spam>
Date: Thu, 08 Nov 2001 17:56:44 GMT
Links: << >>  << T >>  << A >>
Tony Benham wrote:
> 
> I deal in digital video which uses 10 bit vectors. I often want to assign a
> hex no to a 10 bit slv, but I've not found a neat way of doing it. VHDL 93
> supports this for slv's that are multiples of 4 bits, but seems to not deal
> with other nos of bits. Is there any way of dealing wth this ? ie I want to
> do "slv(9 DOWNTO 0) <= Hex 3AC ;" in effect ?

Create a function:

-------
function hex10 
  ( hex12 : std_logic_vector(11 downto 0))
return std_logic_vector is
begin
  return hex12(9 downto 0);
end hex10;
-------

and use:

slv(9 downto 0) <= hex10(X"3AC");
-- 
Tim Hubberstey, P.Eng. . . . . . . . . . . . . . .  Marmot Engineering
Vancouver, BC, Canada  . . . . . Hardware/Software Consulting Engineer

Article: 36422
Subject: Re: Hex numbers in VHDL
From: "Tony Benham" <tonyb@nospam.kerrisway.freeserve.co.uk>
Date: Thu, 8 Nov 2001 18:06:12 -0000
Links: << >>  << T >>  << A >>
Thanks Tim, that works a treat !
Tony

"Tim Hubberstey" <sendme@no.spam> wrote in message
news:3BEAC75C.641E19B@no.spam...
> Tony Benham wrote:
> >
> > I deal in digital video which uses 10 bit vectors. I often want to
assign a
> > hex no to a 10 bit slv, but I've not found a neat way of doing it. VHDL
93
> > supports this for slv's that are multiples of 4 bits, but seems to not
deal
> > with other nos of bits. Is there any way of dealing wth this ? ie I want
to
> > do "slv(9 DOWNTO 0) <= Hex 3AC ;" in effect ?
>
> Create a function:
>
> -------
> function hex10
>   ( hex12 : std_logic_vector(11 downto 0))
> return std_logic_vector is
> begin
>   return hex12(9 downto 0);
> end hex10;
> -------
>
> and use:
>
> slv(9 downto 0) <= hex10(X"3AC");
> --
> Tim Hubberstey, P.Eng. . . . . . . . . . . . . . .  Marmot Engineering
> Vancouver, BC, Canada  . . . . . Hardware/Software Consulting Engineer



Article: 36423
Subject: Re: Xilinx dedicated IO pins
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 08 Nov 2001 19:10:01 +0100
Links: << >>  << T >>  << A >>
"jakab tanko" <jtanko@ics-ltd.com> writes:

> Hi all,
> 
> Could somebody please tell me how to prevent the xlnx P&R
> tool (Alliance 3.1i) from assigning the dedicated pins on a spartan2
> (D0/DIN,
> BUSY/DOUT ..etc) to user IO, I want to keep the dedicated
> pins dedicated...I spent the better part of the day searching the
> xlnx site but got nowhere
> Thanks,

Use

CONFIG PROHIBIT = <pin> ;

in your .ucf-file.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 36424
Subject: Testing of EPX780QC132 needed
From: Jon Schneider <jschneider@cix.ceeowe.ewekay>
Date: Thu, 08 Nov 2001 18:53:24 +0000
Links: << >>  << T >>  << A >>
I am after somebody as local as possible in the UK, preferably East
Anglia to test a tray of the above devices for blankness and program a
few.

The reason being that we have acquired a few lifted ones, suspect them
to be programmed and don't want to put them down on a board first.

	Jon



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