Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 36450

Article: 36450
Subject: reply
From: "Emil Blaschek" <emil.blaschek@siemens.at>
Date: Fri, 9 Nov 2001 08:47:00 +0100
Links: << >>  << T >>  << A >>

From: "Andrew Gray" <andrewgray@iafrica.com>
Subject: Hex numbers in VHDL
Date: Donnerstag, 08. November 2001 11:27

Hi

Is it possible to initialise a std_logic_vector using a hex number instead
of a binary one?

e.g.
temp <= "0x0F0F"
instead of
temp <=  "0000111100001111"

or in an array:
array_x_y:=(("0x0F","0xF0"),("0x55","0xAA"));
instead of
array_x_y := (("00001111","11110000"),("01010101","10101010"));

Thanks

Andrew


  CONSTANT VERSION_REGISTER : std_logic_vector(15 downto 0) :=
std_logic_vector(conv_unsigned

                                       (16#0061#,16));

Try this




Article: 36451
Subject: Re: Implementation of filter with three set of coeffs
From: cappellainfuocata@yahoo.it (Banana)
Date: 8 Nov 2001 23:52:56 -0800
Links: << >>  << T >>  << A >>
Ok, the question in another form :

Normally How you send the coefficient to a filter in VHDL ???

Thanks 

    Banana

Article: 36452
Subject: Is ALtera using segmented routing in Mecury?
From: ndeshmukh@yahoo.com (nitin)
Date: 9 Nov 2001 00:40:23 -0800
Links: << >>  << T >>  << A >>
It is kind of strange why some vertical routing resources in Mercury
directly drive some vertical resource.

e.g:

Leap Lines drive column as well as priority columns...

Priority columns drive priority columns as well as columns...

Columns drive columns too...


Does this somehow suggest some segmented architecture on vertical
resources...?

Ciao,
Nitin.

Article: 36453
Subject: Carry chain in Virtex II
From: ndeshmukh@yahoo.com (nitin)
Date: 9 Nov 2001 00:47:14 -0800
Links: << >>  << T >>  << A >>
Anybody have any ideas why Virtex II CLB has two carry chains passing
through it linking two slices and each and propagating in columns from
top to bottom...?

Why didn't they link all fourslices in just one chain and joined CLBs
in one column together and so on in different columns...

It would be nice if some one with some insight into this matter can
shed some light on it...


Thanx in advance...

Ciao,
Nitin

Article: 36454
Subject: Re: Xilinx machine readable package info
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 09 Nov 2001 09:49:45 +0100
Links: << >>  << T >>  << A >>
"Leon Heller" <leon_heller@hotmail.com> writes:

> "Petter Gustad" <newsmailcomp1@gustad.com> wrote in message
> news:87zo5yp87r.fsf@filestore.home.gustad.com...
> >
> > I'm working on a program to aid me in the tedious allocation of pins
> > for a Virtex-II device. But I need to obtain package information,
> > presumably in machine readable form. I can use partgen to generate a
> > plain ASCII file, but this does not contain any information regarding
> > the bank number for each pin. Is there an ASCII (or documented binary
> > file) file where I can find this information?
> 
> http://www.xilinx.com/products/virtex/vpackages.htm

Thanks, the Virtex II package files can be found at:

http://www.xilinx.com/products/virtex/v2packages.htm

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 36455
Subject: RLOC on RAMB4_Sn_Sn
From: khtsoi@cse.cuhk.edu.hk
Date: 9 Nov 2001 09:23:39 GMT
Links: << >>  << T >>  << A >>
Hi,

Could someone please shows how to place a block ram? The situation is:

There is a RAM4_Sn_Sn components in the design as well as some other
simple logics. All these will be a cell which will be used in a larger
design. I can use RLOC attribute to fix the location of the CLB components.
But the map process keep prompting error about RLOC on the block RAM.
All I want is to place the CLB logics closer to the block RAM. I am using
Synopsys Design Compiler to synthsis and Xilinx Alliance3.1i to implement.
The lines of RLOC are listed below:
--synopsys dc_script_begin
--set_attribute J_UNIT0 RLOC "R27C10" -type string
--set_attribute T_UNIT0 RLOC "R27C11" -type string
--set_attribute KEY_REG RLOC "R7C2" -type string
--synopsys dc_script_end
I have tried to use "RAMB4_R7C2" instead, but no different.
Please help me! Thanks in advance!

---- Brittle

PS I am using Xilinx XCV1000E-HQ240-6
PPS Is a single route (fanout=1) between 2 close CLBs (R0C0 to R0C1 through
the fast horizontal lines) cost 0.601R(ns) is normal?

Article: 36456
Subject: Unknown Timing Sim Warnings
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Fri, 09 Nov 2001 10:27:25 +0100
Links: << >>  << T >>  << A >>
Hello!

During a timing simulation with Foundation Timing Simulator I get the
following messages:

"undetermined input pin state"

and

"undetectable clock pulse"

Can anybody explain what these messages stand for?
Is there a problem in the FPGA design, the .EDN model or is it a problem
of the stimulus?

Michael


Article: 36457
Subject: Re: Hex numbers in VHDL
From: Alan Fitch <alan.fitch@doulos.com>
Date: Fri, 9 Nov 2001 09:35:40 +0000
Links: << >>  << T >>  << A >>
In article <3beabd8f$0$230$cc9e4d1f@news.dial.pipex.com>, Tony Benham
<tonyb@nospam.kerrisway.freeserve.co.uk> writes
>I deal in digital video which uses 10 bit vectors. I often want to assign a
>hex no to a 10 bit slv, but I've not found a neat way of doing it. VHDL 93
>supports this for slv's that are multiples of 4 bits, but seems to not deal
>with other nos of bits. Is there any way of dealing wth this ? ie I want to
>do "slv(9 DOWNTO 0) <= Hex 3AC ;" in effect ?
>Cheers
>Tony

Depends what you mean by neat...

You can use

library ieee;
use ieee.numeric_std.all;

entity...

architecture...
  signal s: std_logic_vector(9 downto 0);
begin

   s <= std_logic_vector(to_unsigned(16#3AC#, 10);

end;

i.e. use the based integer format and convert it to unsigned and then to
std_logic_vector.

You should be able to use S'LENGTH instead of 10 as well.


It looks horrible though :-(

I suppose you could hide the details behind a function, e.g.

s <= tohex(16#3AC#,10);

regards

Alan

   
>
>"Alan Fitch" <alan.fitch@doulos.com> wrote in message
>news:tycOpJA+Wm67YBr0@doulos.co.uk...
>> In article <3bea6077.0@news1.mweb.co.za>, Andrew Gray
>> <andrewgray@iafrica.com> writes
>> >Hi
>> >
>> >Is it possible to initialise a std_logic_vector using a hex number
>instead
>> >of a binary one?
>> >
>> >e.g.
>> >temp <= "0x0F0F"
>> >instead of
>> >temp <=  "0000111100001111"
>> >
>> >or in an array:
>> >array_x_y:=(("0x0F","0xF0"),("0x55","0xAA"));
>> >instead of
>> >array_x_y := (("00001111","11110000"),("01010101","10101010"));
>> >
>> >Thanks
>> >
>> >Andrew
>> >
>> >
>> Yes it is, in VHDL 93 only. You can say
>>
>> temp <= X"0F0F";
>>
>> and similarly for your array.
>>
>> There's a couple of features
>>
>>   - you can use underscores in the literal for readability
>>   - you can specify O for octal, B for binary instead of the X if you
>> want to
>>
>> and there's a "negative" feature
>>
>>  - the literal (using X for hex) can only be a multiple of 4 bits wide
>>  - it won't work on std_logic_vector in VHDL87 (though it will work on
>> bit_vector)
>>
>> regards
>>
>> Alan
>>
>> --
>> Alan Fitch
>> DOULOS Ltd.
>> Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United
>Kingdom
>> Tel: +44 1425 471223                           Email:
>alan.fitch@doulos.com
>> Fax: +44 1425 471573                             Web:
>http://www.doulos.com
>>
>>                    **********************************
>>                    **  Developing design know-how  **
>>                    **********************************
>>
>> This e-mail and any  attachments are  confidential and Doulos Ltd.
>reserves
>> all rights of privilege in  respect thereof. It is intended for the  use
>of
>> the addressee only. If you are not the intended  recipient please delete
>it
>> from  your  system, any  use, disclosure, or copying  of this  document
>is
>> unauthorised. The contents of this message may contain personal views
>which
>> are not the views of Doulos Ltd., unless specifically stated.
>>
>>
>>
>>
>>
>>
>>
>>
>
>

-- 
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                           Email: alan.fitch@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.









Article: 36458
Subject: Re: "Illegal assignment" message, NEED HELP, PLEASE!!!
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Fri, 09 Nov 2001 10:35:45 +0100
Links: << >>  << T >>  << A >>
Jaime Andres Aranguren Cardona a écrit :
> 
> Hi Nicolas,
> 
> Well, what I am trying to do is to rise high the clk_rb_int
> signal when there is a rising edge on the we_intern or the
> re_intern signals.
> 
> OK, it should be like the system clock signal (inverted), but
> shouldn't rise before we_intern or re_intern rise high as well.
> 
> Please help me with this stuff.

Hi Jaime
OK, you want your signal to rise when your rd or wr signals go high but when do
you want it to go low?

Code suggestion for synchronous edge detection:

process(clk)
if rising_edge(clk) then
  reg_input_signal <= input_signal;
  del_input_signal <= reg_input_signal;
  r_edge <= not del_input_signal and reg_input_signal;
  f_edge <= del_input_signal and not reg_input_signal;
end if;

This will produce a one clock period long pulse when input_signal toggles.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 36459
Subject: Re: Hex numbers in VHDL
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Fri, 9 Nov 2001 09:46:32 +0000
Links: << >>  << T >>  << A >>
In article <3beabd8f$0$230$cc9e4d1f@news.dial.pipex.com>, Tony Benham
<tonyb@nospam.kerrisway.freeserve.co.uk> writes
>I deal in digital video which uses 10 bit vectors. I often want to assign a
>hex no to a 10 bit slv, but I've not found a neat way of doing it. VHDL 93
>supports this for slv's that are multiples of 4 bits, but seems to not deal
>with other nos of bits. Is there any way of dealing wth this ? ie I want to
>do "slv(9 DOWNTO 0) <= Hex 3AC ;" in effect ?

Yes, it's irritating.

There's not much choice but to do the usual

  slv(9 downto 0) <= std_logic_vector(to_unsigned(16#3AC#, 10));

Since I have a relatively low boredom threshold, especially
when typing, in a situation like yours I'd package that as
a function:

  function to_slv10(x: integer) return std_logic_vector is
  begin
    return std_logic_vector(to_unsigned(x, 10));
  end;

Synthesis tools seem to cope with this OK.
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 36460
Subject: Xilinx unconnected logic
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Fri, 09 Nov 2001 11:19:51 +0100
Links: << >>  << T >>  << A >>
Hi all

I was wondering what was done with all the unused logic in Xilinx Virte-E. We
have some strange instability problems and some engineers blem internal
oscillations of unused logic inside the chip.
With the 4000 families, there was an option that allowed to tie all unused
interconnect so that it wouldn't mess but this option is no longer there.
I'm puzzled... Any help welcome :o)

Thanks in advance
-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 36461
Subject: Re: Xilinx dedicated IO pins
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 09 Nov 2001 11:21:51 +0100
Links: << >>  << T >>  << A >>
"jakab tanko" <jtanko@ics-ltd.com> writes:

> I don't have a problem with all dedicated pins, just the JTAG and master
> serial
> configuration pins; suppose one of your JTAG pins ends up shared with a data
> pin driven from a RAM (no tri-state RAM outputs); there will be a
> conflict
> on that pin with multiple drivers ....
> Anyway, the suggestion from Magnus with the .UCF file worked with a little
> twist:
> I also had to go and manualy delete the .map file then P&R again, othervise
> the map file would not reflect the changes

Actually, you would haver to re-run the translate step too, that's
where the .ucf file is read.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 36462
Subject: Re: Fifo books
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Fri, 09 Nov 2001 21:39:21 +1100
Links: << >>  << T >>  << A >>


Peter Alfke wrote:
> 
> Russell Shaw wrote:
> I found some other interesting things too:
> 
> > http://www.geocities.com/deepakgeorge2000/vlsi_book/Asynch1.pdf
> > http://www.geocities.com/deepakgeorge2000/vlsi_book/async_fifo2.pdf
> 
> I looke at it and found it quite wordy. The author belabors
> metastability, and does not understand that the leading edge of Full
> and Empty is always a synchronous signal in the time domain of
> interest. Only the trailing edge is asynchronous, but there
> double-synchronizing is easy. Also, the generation of Grey addresses
> is described in an unnecessarily complicated way.
> I find my design so much simpler and less cluttered, if I may say so
> :-)
> See
> http://www.xilinx.com/support/techxclusives/fifo-techX18.htm
> 
> Peter Alfke ( >30 years of FIFO experience, starting with the
> Fairchild 3341 )

Thanks, a nice article (and the asynchronous flag one too).
I might comment that this bit isn't always so:
"there is no alternative to the proper timing of the
 EMPTY flag, since the system needs to read even the
 very last word stored in the FIFO"

Sometimes you use fifos to get measurement data (like i was),
that then gets filtered or averaged. In that case, there's a
continuous stream of data going thru the fifo, so a pessimistic
empty flag would be ok. When the data is stopped, the system isn't
doing anything, and a few samples left in the fifo wouldn't
matter.

I found this book has fifo examples, and looks like a good one
to get:
  Digital Systems Design With Vhdl and Synthesis : 
                                        An Integrated Approach
                                        by K. C. Chang

http://www.amazon.com/exec/obidos/ASIN/0769500234/qid=1005302144/sr=8-1/ref=sr_8_3_1/102-7754698-1070516

Article: 36463
Subject: Decoupling capacitors on Virtex II
From: "Philippe Robert" <PhilippeR@sundance.com>
Date: Fri, 9 Nov 2001 10:59:05 -0000
Links: << >>  << T >>  << A >>
Hi there,

I found an application note on the Xilinx website (xapp158) about decoupling
capacitors. It is explained that high frequency and mid-frequency capacitors
are required.

For the high frequency capacitor, I will use 100nF. It says in that app to
fit 1 100nF cap per Vcc. (I have counted as Vcc pins  Vccio, Vccaux and
Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !!
Can someone tell me of my calculation is right ?

For mid-frequency caps, I will use 10uF tant, but the app note does not say
how many of them to fit.
Does anyone know ?

Thanks for your help.
Philippe.




Article: 36464
Subject: Log2(x) for vhdl?
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Fri, 09 Nov 2001 22:01:41 +1100
Links: << >>  << T >>  << A >>
Hi all,

There's an exponent operator (**), but no log-base-2 (from what
i could see). Such a function (with integer result) would be useful
would it not?:

constant MAXADDR: natural:=1000;
.
.
.
signal addrcntr:unsigned(LOG2(MAXADDR) downto 0);

LOG2 should round upwards.

Could a function be written to do it?

Article: 36465
Subject: Re: Log2(x) for vhdl?
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Fri, 09 Nov 2001 11:24:32 GMT
Links: << >>  << T >>  << A >>
On Fri, 09 Nov 2001 22:01:41 +1100, Russell Shaw
<rjshaw@iprimus.com.au> wrote:

>Hi all,
>
>There's an exponent operator (**), but no log-base-2 (from what
>i could see). Such a function (with integer result) would be useful
>would it not?:
>
>constant MAXADDR: natural:=1000;
>.
>.
>.
>signal addrcntr:unsigned(LOG2(MAXADDR) downto 0);
>
>LOG2 should round upwards.
>
>Could a function be written to do it?

You mean like the ones in this thread?
http://groups.google.com/groups?threadm=iWOC4.143%249o.293380%40news.magma.ca

Regards,
Allan.

Article: 36466
Subject: Re: Log2(x) for vhdl?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 09 Nov 2001 14:54:54 GMT
Links: << >>  << T >>  << A >>
THis is one I wrote a few years ago.  I keep it in my common library so
that it is always available.

function Log2( input:integer ) return integer is
 variable temp,log:integer;
 begin
  temp:=input;
  log:=0;
  while (temp /= 0) loop
   temp:=temp/2;
   log:=log+1;
   end loop;
   return log;
  end function log2;


Russell Shaw wrote:

> Hi all,
>
> There's an exponent operator (**), but no log-base-2 (from what
> i could see). Such a function (with integer result) would be useful
> would it not?:
>
> constant MAXADDR: natural:=1000;
> .
> .
> .
> signal addrcntr:unsigned(LOG2(MAXADDR) downto 0);
>
> LOG2 should round upwards.
>
> Could a function be written to do it?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36467
Subject: Re: Maxplus error
From: "C.Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Fri, 9 Nov 2001 16:09:25 +0100
Links: << >>  << T >>  << A >>
Hi Andrew,
I made something comparable according to the delcaration:

TYPE RAGARRAY IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (11 DOWNTO 0);
SIGNAL RAG_ARRAY : RAGARRAY;

but...

the problem is, that You could not delcare a "constant" that way, You
have to use a signal instead. If You still wnat to use the constant,
You must split Your array into 64 constants...

Just my two cent's, Carlhermann



Article: 36468
Subject: Re: Xilinx unconnected logic - always connected!
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 09 Nov 2001 07:26:14 -0800
Links: << >>  << T >>  << A >>
Nicolas,

All of the internal inputs use what is called a "half latch."

After configuration, all unused inputs were held high by the start up sequence
control transistors, and the half latches stick the high on their inputs (an
inverter driving the gate of a weak pmos transistor pulling the input up to Vdd).

Sorry, no oscillations possible.  The 'instabilities' are likely bad signal
integrity, unaccounted for jitter on the clocks, or other paths where timing is
not being met. Also do not forget that buses on printed circuit boards may have
cross talk induced delay variations as the data pattern changes of up to a
nanosecond or more.

 http://support.xilinx.com/support/techxclusives/slack-techX21.htm

may be of interest.

Austin

Nicolas Matringe wrote:

> Hi all
>
> I was wondering what was done with all the unused logic in Xilinx Virte-E. We
> have some strange instability problems and some engineers blem internal
> oscillations of unused logic inside the chip.
> With the 4000 families, there was an option that allowed to tie all unused
> interconnect so that it wouldn't mess but this option is no longer there.
> I'm puzzled... Any help welcome :o)
>
> Thanks in advance
> --
> Nicolas MATRINGE           IPricot European Headquarters
> Conception electronique    10-12 Avenue de Verdun
> Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
> Fax +33 1 46 52 53 01      http://www.IPricot.com/


Article: 36469
Subject: Virtex 2 parts availability???
From: "Austin Franklin" <austin@dark98room.com>
Date: Fri, 9 Nov 2001 11:11:50 -0500
Links: << >>  << T >>  << A >>
Hi,

What is the largest Virtex 2 part that anyone physically has in hand?

What promises have you received for delivery of parts?

I have a client who wants to use the large V2 parts (6000), but we can't get
a consistent answer from the distributor WRT delivery.  I got VERY badly
burnt last year with promises for V3200 delivery that never
materialized...so I am leery of making any commitments to clients about
parts that I don't have in hand.

Any info would be appreciated.

Thanks!




Article: 36470
Subject: Re: RLOC on RAMB4_Sn_Sn
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Fri, 09 Nov 2001 16:13:40 GMT
Links: << >>  << T >>  << A >>
BRAMs, very unfortunately, can't have relative locations.  BRAMs can only be
placed with absolute LOCs.

<khtsoi@cse.cuhk.edu.hk> wrote in message
news:9sg7ar$7q5$1@eng-ser1.erg.cuhk.edu.hk...
> Hi,
>
> Could someone please shows how to place a block ram? The situation is:
>
> There is a RAM4_Sn_Sn components in the design as well as some other
> simple logics. All these will be a cell which will be used in a larger
> design. I can use RLOC attribute to fix the location of the CLB
components.
> But the map process keep prompting error about RLOC on the block RAM.
> All I want is to place the CLB logics closer to the block RAM. I am using
> Synopsys Design Compiler to synthsis and Xilinx Alliance3.1i to implement.
> The lines of RLOC are listed below:
> --synopsys dc_script_begin
> --set_attribute J_UNIT0 RLOC "R27C10" -type string
> --set_attribute T_UNIT0 RLOC "R27C11" -type string
> --set_attribute KEY_REG RLOC "R7C2" -type string
> --synopsys dc_script_end
> I have tried to use "RAMB4_R7C2" instead, but no different.
> Please help me! Thanks in advance!
>
> ---- Brittle
>
> PS I am using Xilinx XCV1000E-HQ240-6
> PPS Is a single route (fanout=1) between 2 close CLBs (R0C0 to R0C1
through
> the fast horizontal lines) cost 0.601R(ns) is normal?



Article: 36471
Subject: How to convert unsigned integer into std_logic_vector in VHDL design?
From: "JianYong Niu" <cop00jn@shef.ac.uk>
Date: Fri, 9 Nov 2001 16:15:16 -0000
Links: << >>  << T >>  << A >>
Hi, All,

In a signal assignment I have to convert an unsigned integer into
std_logic_vector. Is there any convert function that can be used to achieve
that?

The synthesizer I used is Synplify Pro. I assume the standard pakage
"ieee.std_logic_arith" could support the convert function
"conv_std_logic_vector()", but unfortunately synthesizer generated an error
that "No matching overload for conv_std_logic_vector".

Any suggestions?

Thanks a lot in advance!!!


--
Jianyong Niu
---------------------------
Rolls-Royce UTC
ACSE, Univ of Sheffield
B20 Amy Johnson Building
Mappin St.
Sheffield S1 3JD, UK
Tel: +44 (0)114 2225236
Fax: +44 (0)114 2225138
Email: jyniu@acse.shef.ac.uk




Article: 36472
Subject: Re: Counter detects both edge of clock?? (verilog)
From: "Pallek, Andrew [CAR:CN34:EXCH]" <apallek@americasm01.nt.com>
Date: Fri, 09 Nov 2001 11:30:06 -0500
Links: << >>  << T >>  << A >>
First invert the clock

assign clkn = ~clk;

then use the positive edges of each clock

always @ (posedge clk or posedge clkn)
counter <= counter +1;


dfx2001 wrote:

> who knows how to detect both edges (rising and falling edge) of clock in
> verilog?
>
> always @(posedge clk or negedge clk)
> counter <= counter + 1; //only count 1, not 2
>
> Thanks.


Article: 36473
Subject: Re: Decoupling capacitors on Virtex II
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 09 Nov 2001 11:48:14 -0500
Links: << >>  << T >>  << A >>
Philippe Robert wrote:
> 
> Hi there,
> 
> I found an application note on the Xilinx website (xapp158) about decoupling
> capacitors. It is explained that high frequency and mid-frequency capacitors
> are required.
> 
> For the high frequency capacitor, I will use 100nF. It says in that app to
> fit 1 100nF cap per Vcc. (I have counted as Vcc pins  Vccio, Vccaux and
> Vccint pins). I end up with 64 cpas for a XC2V1000-FG456 !!
> Can someone tell me of my calculation is right ?
> 
> For mid-frequency caps, I will use 10uF tant, but the app note does not say
> how many of them to fit.
> Does anyone know ?
> 
> Thanks for your help.
> Philippe.

I personally think that Xilinx is using a lot of overkill in their goal
of 1 cap per vcc. This is a noble goal, but rather impractical on the
packages with very fine pitch balls. When there are two or three pins
together, I would use one 100 nF cap per clump of pins. 

How many 10 uF caps to use is not really the right question. With the
bulk medium freq caps, you only need one per board. That is because they
have high impedance at high frequencies. The cap impedance is much
higher than the circuit impedance even when at the other side of the
board from the chip. So you can get by with a single bulk cap per board.
Just use one that is large enough and has a low ESR. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 36474
Subject: Location constraint error message?
From: "Dave Brown" <dbrown@novatel.ca>
Date: Fri, 9 Nov 2001 10:10:42 -0700
Links: << >>  << T >>  << A >>
Hi,
    I'm getting the following contraint error message when I try to
implememnt my design on a spartanXL 05-4vq100, using Xilinx ISE 4.1:

ERROR:OldMap:40 - Bad format for LOC constraint P74 on symbol "MY_INPUT"
(pad
   signal=MY_INPUT). No such site for this device.  This may also indicate
   that a non-constrainable site (such as a VCC, GND, mode, configuration,
or
   other special-purpose pin) has been used as a site name.

I've checked, and PIN 74 is the configuration CCLK, but according to the
data sheet, I should be able to use this as an input after configuration.
Anyone have any ideas why this is happening? Also, here's the line from the
.ucf file I use.

NET "MY_INPUT" LOC = "P74";

Thanks for any help,
Dave





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search