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Messages from 36600

Article: 36600
Subject: Re: Virtex 2 parts availability???
From: "James C. Schwalbe" <schwalbe@compuserve.com>
Date: Tue, 13 Nov 2001 00:00:07 -0500
Links: << >>  << T >>  << A >>
I have heard that Xilinx is having difficulty yielding on the 6000 parts and
will not be able to deliver on any parts larger than this.  They do not have
the redundancy built into the dye that Altera has therefore making it more
difficult to get reasonable yields on the larger parts.

Jim

"Austin Franklin" <austin@dark98room.com> wrote in message
news:tuo027tbr1fn64@corp.supernews.com...
> Hi,
>
> What is the largest Virtex 2 part that anyone physically has in hand?
>
> What promises have you received for delivery of parts?
>
> I have a client who wants to use the large V2 parts (6000), but we can't
get
> a consistent answer from the distributor WRT delivery.  I got VERY badly
> burnt last year with promises for V3200 delivery that never
> materialized...so I am leery of making any commitments to clients about
> parts that I don't have in hand.
>
> Any info would be appreciated.
>
> Thanks!
>
>
>



Article: 36601
Subject: Re: PLL in Altera's Apex20K
From: "James C. Schwalbe" <schwalbe@compuserve.com>
Date: Tue, 13 Nov 2001 00:06:13 -0500
Links: << >>  << T >>  << A >>
As you have pointed out, the "X" suffix indicates that the PLLs have been
tested and are enabled.  While all the devices have the silicon for the
PLLs, only those devices that pass testing for the PLL will get the "X"
suffix.  If they don't pass the test, the PLLs are disabled.  This doesn't
mean you can use them at a lower speed, you cannot access them at all.

For details on how the power pins should be treated, go to www.altera.com
and look at the Pinouts section.  Grab the .pdf file for the actual device
you are considering, and it will tell you not only how to connect up the
power pins, but and special purpose pins, unused, pins, etc.

Jim

"Markus Fras" <fras@mppmu.mpg.de> wrote in message
news:3BEFA18B.74EB47EF@mppmu.mpg.de...
> In Altera's Apex20K devices with speed grades -1X and -2X there is a PLL
> integrated.
> But how about the other devices? Are there also PLLs inside which are just
not
> operational within the specifications, but still might work within lower
limits?
> And how are the power-pins for the PLL treated?



Article: 36602
Subject: Fast Fourier Transformation - camera data
From: Thomas Wambera <thomas@wambera.de>
Date: Tue, 13 Nov 2001 07:49:03 GMT
Links: << >>  << T >>  << A >>
Hello ng!

I am looking for an open Core which contains functions as Fast Fourier Transformation (possibly the Butterfly algorithm).
Does anybody know about?

My other problem is that I have to implement a 2 dimensional analysis of Camera data. Every row can be calculated 
during measurement, but the y-direction (the coloums) have to be stored and calculated later. Does anybody have an 
idea what would be the best possibility to do so? The main problem is the mass of data, with an greyscale camera (8 
bit/pixel) and a picture of 512x512 an immense memory is needed. The other problem is the data format, it should be 
float, but is that precise enough to calculate with?

One possibility to save memory would be in-place calculating, but is it anyhow possible to realize with an fpga or should 
it be done in a pc ?

If you would use an fpga, could the block ram be the "candidate" for storing the data or is it to less memory, also in the 
"E" series of Virtex?

Thanks for your interest!

-- 
T |-| ( ) |\/| /-\ S         thomas@wambera.de   
www.madmusic.de              www.kripps.de
www.klangkollektiv.com       






Article: 36603
Subject: Re: Funny voltage levels
From: Nial Stewart <nials@britain.agilent.com>
Date: Tue, 13 Nov 2001 08:17:34 +0000
Links: << >>  << T >>  << A >>
Russell Shaw wrote:
> 
> Nial Stewart wrote:
> 
> > > However, i
> > > think there might be a clock-alignment problem somewhere.
> >
> > There shouldn't be. If you've used a global clock input pin
> > for your clock they guarantee set up and hold times from
> > egister to register. it's then just a matter or making
> > sure you're writing good synchronous code.
> 
> Actually, i was using the global clock pin for a 20MHz clock,
> then the 5MHz clock i used for everything comes from a vhdl
> x4 counter, so i'll need to check that clock routing.

Russell,

You'd be better using the 20MHz clock and enabling your
circuit every 4th clock with the output of your /4
counter.

This way you know the setup and hold between registers 
should be OK and all you need worry about is functionality.

Nial.

Article: 36604
Subject: Re: Incrementing counter from state-machine
From: "Srinivasan Venkataramanan" <srinivasan@siliconsystems.co.in>
Date: Tue, 13 Nov 2001 14:17:21 +0530
Links: << >>  << T >>  << A >>
Hi,

"Russell Shaw" <rjshaw@iprimus.com.au> wrote in message
news:3BF064BA.D3841344@iprimus.com.au...
>
>
<SNIP>
> > > <2>     wait until clk'event and clk='1';
> >
> > I wouldn't use this in synthesizeable code.
> > This is eqivalent to process(Clk) and leed to synchronous FF.
>
> From what i've seen, its quite valid for synthesizeable code. Its
> in Bhasker: A VHDL Synthesis Primer, and in the leonardo synthesis
> manual.

    I have used this without any problems, infact it is much easier
not to worry about the Sensitivity list, but anyway for the
Synchronous processes the maximum sensitivity list size is 2, so even
though your tool may issue warnings, it is fine.

>
> > [..]
> > >         when 2=>
> > >             if ptr<16
> > >             then
> > > <1>             ptr_en<='1';        -- inc ptr
> > >                 next_state<=1;
> >
> > This is a Mealy description in a mainly Moore automate. First
place to get
> > problems, but should do in this case..
> >
> > > state_proc:
> > >     process(reset,clk,next_state)
> >
> > This is your problem.
> > If you want to sysnthesize your code, you've got two [1] kinds of
proces:
> > one for Logik and one for Register. If you want to get Register,
your
> > process should be sensitive to Clk and Reset, if you want to get
logik, you
> > should be sensitive to every signal that effects the signals
changed during
> > the process. Mixing both styles like your process creates latches.
>
> But with synthesis, i think *everything* that gets assigned a value
> within a process, has to be in the sensitivity list or leonardo
gives
> warnings.

   That's only for Combinatorial blocks, as such Synthesis tools don't
understand (while parsing, anyway) the difference in the beginning so
they do emit warnings - which can *safely* be ignored.

> Only with a "wait until" line, does the process not have a
> sensitivity list.
>

  Agreed, but off late I don't use this style, I prefer using clk,
reset in the sensitivity list.

Regards,
Srinivasan

---
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)




Article: 36605
Subject: Synopsys+Xilinx vs Synplicity
From: khtsoi@cse.cuhk.edu.hk
Date: 13 Nov 2001 09:01:21 GMT
Links: << >>  << T >>  << A >>
Hi,

Someone told me that tools from Synplicity is better than the Synopsys
Xilinx combination in FPGA place and route process. I am sick with the
bad routing design in Alliance3.1i. Also, it takes me more than 1 day
to par a design using only 45% slices of a XCV1000E (on a Sun E4500).

I really hope someone can give me some advices about the performance
of the Synplicity tools. I will use it on either or both Sun E4500 with
SunOS and P4 1.4GHz PC with Win/Linux. Does anyone has experience on
implementing a design in similar size under these environment? Also,
most of my current design is developed under Synopsys Design Compiler
which cannot be synthsised directly on FPGA Express. Can the Synplicity
tools under the synopsys coding style? Last, is there any performance
differences between the commercial version and evaluation version?

---- Brittle

PS I am now downloading the evaluation version of Synplify.

Article: 36606
Subject: Re: Jpeg 2000
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Tue, 13 Nov 2001 10:11:24 +0100
Links: << >>  << T >>  << A >>
The Altera NIOS core supports custom instructions. We've made some
experiments with it and it worked very well for us. This features seems to
be ideal for your hardware/sofware co-design approach. Check out the
following link for more information on it.

http://www.altera.com/products/devices/excalibur/features/exc-nios_cpu_archi
tecture.html#custom_instructions

Regards
Wolfgang
http://www.elca.de

"Eduardo Augusto Bezerra" <eduardob@acm.org> schrieb im Newsbeitrag
news:3BF02987.4BB68312@sussex.ac.uk...
> Hello
>
> We are trying to do a hardware implementation of JPEG2000 to be used for
> at least 15fps video. From the algorithm, it looks to us like a
> hardware/software co-design seems more feasilble than a pure hardware
> implementation. Any thoughts on this?
>
> We are also thinking of using a Virtex-II FPGA as a prototyping platform
> perhaps
> with an embedded processor. Other options we are investigating are
> Altera and
> Actel FPGAs but we would be happy for your advice on this subject.
>
> Many thanks
>
> Marianne.
>
> --
> Altek Technologies Ltd.
> East Sussex Advanced Technology Hub
> Ashdown House
> Brighton
> BN1 9RT
>
> tel. +44 (0)1273 877703



Article: 36607
Subject: Re: Incrementing counter from state-machine
From: thomas.stanka@de.bosch.com (Thomas Stanka)
Date: 13 Nov 2001 09:12:01 GMT
Links: << >>  << T >>  << A >>
HI,

Russell Shaw <rjshaw@iprimus.com.au> wrote:
> Thomas Stanka wrote:
>> I wouldn't use this in synthesizeable code.
>> This is eqivalent to process(Clk) and leed to synchronous FF.
> 
> From what i've seen, its quite valid for synthesizeable code. Its
> in Bhasker: A VHDL Synthesis Primer, and in the leonardo synthesis
> manual.

Of course its valid and get synthesised. But you have to be aware that you 
get a FF with synchronouns reset. Further on, you use Latches with asynch. 
reset for state. 
If my code didnt work while mixing both registertypes I would start with 
having a very close look upon these.
 
> But with synthesis, i think *everything* that gets assigned a value
> within a process, has to be in the sensitivity list or leonardo gives
> warnings. Only with a "wait until" line, does the process not have a
> sensitivity list.

No, as I wrote, there are two kinds of process, that every sythesistool 
should know (never worked with leonardo, but I expect leonardo to behave 
"normal") clocked process wich systhesis to register and logic process.
in clocked process, only clk (and reset for asych. reset) should occoure in 
the sensitivity list.

> The latches should just hold ptr_en and ptr_reset, because they're
> not assigned in every case option.

The latches were synthesised for state ! (I missed that your code also 
infer latches for ptr_*)
The latches for prt_en and ptr_reset are unnecessary if you set them per 
default in top of the process.

process
begin
prt_reset<='0';
prt_en<='0';
case...
  when xx =>
     ptr_en<='1';
...

bye Thomas





-- 
Thomas Stanka BC/EMD4
Space Communications Systems
Bosch SatCom
thomas.stanka@de.bosch.com

Article: 36608
Subject: Re: Virtex 2 parts availability???
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 13 Nov 2001 10:19:15 +0100
Links: << >>  << T >>  << A >>
"James C. Schwalbe" <schwalbe@compuserve.com> writes:

> I have heard that Xilinx is having difficulty yielding on the 6000 parts and
> will not be able to deliver on any parts larger than this.  They do not have
> the redundancy built into the dye that Altera has therefore making it more
> difficult to get reasonable yields on the larger parts.

Wouldn't it be possible for Xilinx to sell us defective parts for a
lower price with a UCF or similar describing the defects so that we
could use the parts for prototyping?

If this defect list management was implemented in the download
procedure one could do this with any part. However the part could be
considered defective if this the defect was located in a critical path
or in any way so that the performance would be lower than a specified
limit for that path, or if the design would not fit. It would be
pretty bad if a 6000 part had a lower usable gate count than a 3000
tough...

Hard disk vendors do have been doing this for years.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 36609
Subject: FPGA synthesis
From: Madhura <madhura@controlnet.co.in>
Date: Tue, 13 Nov 2001 03:00:17 -0700
Links: << >>  << T >>  << A >>
How to give the sxnf files generated by dc-shell to FPGA compiler to generate VHDL netlist?

Article: 36610
Subject: Re: ZX81 production run, is there any interest?
From: McMeikan <mcmeikan@touch88.com.au>
Date: Tue, 13 Nov 2001 18:55:53 +0800
Links: << >>  << T >>  << A >>
OK done.  will all interested please join.

If you have some skills please consider joining even if its just to give
advice when we go wrong.

Initial goal is to design an easy to build gate array based ZX-81, I can
supply some XC30xx chips for the initaial developers.


              http://groups.yahoo.com/group/zxgate
              mailto://zxgate-subscribe@yahoogroups.com
            mailto://zxgate@yahoogroups.com
    cya,    Andrew...

Speedy Zero Two wrote:

> <Big Snip>
>
> All,
>
> Has anyone thought of setting up a specific group for this.
> Seems there is loads of interest but no coordination.
>
> I'm interested too
>
> Dave (via comp.arch.fpga)


Article: 36611
Subject: Re: Clock Divider or Multiplier ???
From: "John Adair" <newsanswer@removethisenterpoint.co.uk>
Date: Tue, 13 Nov 2001 11:12:37 -0000
Links: << >>  << T >>  << A >>
If you use Virtex II it is not a problem. It can do F x (m/n) on the fx
output where I believe you can use values m = 2 to 32, n = 1 to 32.
Alternatively divide your clock then do a simple multiply internally using 2
DCMs. Be careful of minimum/maximum frequency limitations although I don't
think in your case there is an issue.

Another way to tackle this is to multiply your 120 MHz using the DCM to 240
MHz and generate clock enables to simulate 60 MHz and 80 MHz. This approach
has the advantage of having only one clock domain so no problems passing
data between domains. We have customer designs operating at these
frequencies with minimal problems. However you may need to pipeline or
replicate the clock enable signals to meet 240 MHz timing.


John Adair
Enterpoint Ltd.
Unit 4
Malvern Hills Science Park
Geraldine Road
Malvern
Worcestershire
United Kingdom
www.enterpoint.co.uk

The views expressed in this message are those of the writer and not
necessarily those of Enterpoint Ltd.. The use of information in this message
is without warranty and persons using the information are advised to make
their own checks as to it's validity. No responsibility will be accepted for
any incorrect, inaccurate or missleading information supplied.


#BASUKI ENDAH PRIYANTO# <PH892987@ntu.edu.sg> wrote in message
news:8D5C8824989A21458FFF1C3CE9902036058AF145@mail12.main.ntu.edu.sg...
> Dear all,
>
> My circuit need various frequency clock. Is it common to built Clock
> Multiplier ?
> I think it is easier to built clock divider rather than clock
> multiplier.
>
> For examples, My circuit need clock source 60 MHZ and 80 MHz, Therefore
> If I have one 120 MHz clock source, I just need to built 1/3 clock
> divider and 1/2 clock divider. But another way is by using 20 MHz clock
> source then I built 3x clock multiplier and 4x clock multiplier.
>
> I really appreciate for your advices/suggestion.
>
> Thanks
>
> Buzz
>
>



Article: 36612
Subject: Elliptic Curves
From: "fede" <fedeg@terra.es>
Date: Tue, 13 Nov 2001 13:55:30 +0100
Links: << >>  << T >>  << A >>
Hi

Are there anybody who implemented elliptic curves cryptographic algorithms
in some fpga?
thanks



Article: 36613
Subject: Re: FPGA synthesis
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 13 Nov 2001 14:35:55 +0100
Links: << >>  << T >>  << A >>
Madhura <madhura@controlnet.co.in> writes:

> How to give the sxnf files generated by dc-shell to FPGA compiler to
> generate VHDL netlist?

Isn't it easier to generate the VHDL netlist from dc-shell directly?
write -format vhdl -hierarchy -output myfile.vhdl top

Assuming that you have a license which will let you do so...

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 36614
Subject: Xilinx port warnings
From: "Kris Nichols" <kris@nichols.com>
Date: Tue, 13 Nov 2001 10:35:47 -0500
Links: << >>  << T >>  << A >>
Hey there,
                      My development environment is the following:
Xilinx Foundation ISE 3.3i (ELITE)
ModelSIM 5.5c
Windows NT (SP6)

In using the XST synthesis tool for implementation, I get a bunch of the
following repetative warnings:

WARNING : (HDL__0005). Signal <name_of_signal> is assigned but never used.
WARNING : (HDL__0002). Input <name_of_signal> is never used.

When I create a testbench using 'HDL Bencher' for my design, the
'functional' simulation is successful.  However attempts to run a 'timing'
simulation fail with the following ModelSIM messages:

# WARNING[1]: activ_func_sigmoid_tb.vhd(50): No default binding for
component: "activ_func_sigmoid". (Port "input_value" is not on the entity)

Since the 'timing' simulation is dependent on the SDF (Standard Delay
File) produced from the implementation of my design (i.e. an entity called
'activ_func_sigmoid') in the Xilinx environment, could the Xilinx warning
messages shown above lead to some of my ports not being implemented
properly??  Can you explain what these two Xilinx messages mean in
detail??  Any advice you have would be much appreciated.  Thanks for your
time.

Kris Nichols






Article: 36615
Subject: 'Timing' simulation in ModelSIM
From: "Kris Nichols" <kris@nichols.com>
Date: Tue, 13 Nov 2001 10:37:20 -0500
Links: << >>  << T >>  << A >>
Hey there,
    It seems I have another challange to overcome in attempting 'timing'
simulations in ModelSIM.  Please recall that my environment is the
following:
ModelSIM SE 5.5c
Xilinx Foundation ISE 3.3i (ELITE)
Windows NT (SP6)

I get the following reported errors from ModelSIM when running a testbench
(i.e. activ_func_sigmoid_tb.vhd) on an entity called 'activ_func_sigmoid':
--------------------------------------------------
###### activ_func_sigmoid_tb.vhd(50): );
# WARNING[1]: activ_func_sigmoid_tb.vhd(50): No default binding for
component: "activ_func_sigmoid". (Port "input_value" is not on the entity)
# -- Compiling configuration activ_func_sigmoid_cfg
# -- Loading entity testbench
# -- Loading architecture testbench_arch of testbench
# vsim -lib work -sdfmax /UUT=activ_func_sigmoid_ppar.sdf testbench
# //  ModelSim SE 5.5c Jun 22 2001
# //
# //  Copyright (c) Mentor Graphics Corporation, 1982-2001, All Rights
Reserved.
# //                       UNPUBLISHED, LICENSED SOFTWARE.
# //            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //          PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# //  Copyright (c) Model Technology Incorporated 1990-2001, All Rights
Reserved.
# //
# Loading E:/Modeltech_5.5c/win32/../std.standard
# Loading E:/Modeltech_5.5c/win32/../ieee.std_logic_1164(body)
# Loading E:/Modeltech_5.5c/win32/../ieee.std_logic_arith(body)
# Loading E:/Modeltech_5.5c/win32/../ieee.std_logic_unsigned(body)
# Loading uog.uog_fp_exp(body)
# Loading uog.uog_fp_arith(body)
# Loading E:/Modeltech_5.5c/win32/../std.textio(body)
# Loading E:/Modeltech_5.5c/win32/../ieee.std_logic_textio(body)
# Loading work.testbench(testbench_arch)
# ** Warning: Component uut is not bound.
#    Time: 0 ns  Iteration: 0  Region: /testbench
# ERROR: activ_func_sigmoid_ppar.sdf: The design does not have an instance
named '/UUT'.
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./activ_func_sigmoid_tb.tdo PAUSED at line 8
--------------------------------------------------

It seems that ModelSIM doesn't believe that a input port called
'input_value' doesn't exist in the entity, when in fact this port does
exist.  Do you have any suggestions on how I can overcome this problem??
I just wanted to point out that a 'functional' simulation works
successfully with the same 'activ_func_sigmoid' VHDL source file and its
respective testbench.  Perhaps there's problems with the SDF (Standard
Delay Format) file that's produced by the Xilinx environment, which the
'timing' simulation depends on.  I did notice that Xilinx produced some
warnings during implementation that were as follows:

---------------------------------------------------
Synthesizing Unit <activ_func_sigmoid>.
    WARNING : (ADVISOR__0001). Extracting 32-bit latch for signal
<output>.
WARNING : (HDL__0005). Signal <intermediate_mult2<31>> is assigned but
never used.
WARNING : (HDL__0005). Signal <intermediate_mult2<30>> is assigned but
never used.
:
etc.
----------------------------------------------------

I'll be checking with the fellas at Xilinx to see if these warnings lead
to the incorrect implementation of ports.  However, any input you have on
this problem would be much appreciated.  Thanks for your time.

Kris Nichols



Article: 36616
Subject: Re: ideas
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Tue, 13 Nov 2001 08:32:43 -0800
Links: << >>  << T >>  << A >>
On Fri, 9 Nov 2001 12:15:18 -0600, Samuel Bogale <sb9@cec.wustl.edu>
wrote:

>
>
>Can someone suggest ideas what FPGA can be used for? 
>
>-Sam
>
>
>

Many of the ceramic PGA parts make excellent x-acto knife sharpeners,
almost as good as Pentium I chips.

John


Article: 36617
Subject: Place your orders....
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 13 Nov 2001 08:37:33 -0800
Links: << >>  << T >>  << A >>
Lies, lies, and damned lies,

2V6000's are yielding just fine.

Just because Altera can't figure out how to make parts without redundancy
doesn't mean we can't either.

It may be that you can't get any right now because we hadn't plan to ship this
many this quarter.

Think about it:  if you have redundancy, then you don't have to improve yields,
because you can tolerate really bad yields.  Beware the feature you ask for:  it
may "yield" unexpected results!

Oh, by the way, really bad yielding lots are usually cause for concern for
reliability engineers.

Austin

"James C. Schwalbe" wrote:

> I have heard that Xilinx is having difficulty yielding on the 6000 parts and
> will not be able to deliver on any parts larger than this.  They do not have
> the redundancy built into the dye that Altera has therefore making it more
> difficult to get reasonable yields on the larger parts.
>
> Jim
>
> "Austin Franklin" <austin@dark98room.com> wrote in message
> news:tuo027tbr1fn64@corp.supernews.com...
> > Hi,
> >
> > What is the largest Virtex 2 part that anyone physically has in hand?
> >
> > What promises have you received for delivery of parts?
> >
> > I have a client who wants to use the large V2 parts (6000), but we can't
> get
> > a consistent answer from the distributor WRT delivery.  I got VERY badly
> > burnt last year with promises for V3200 delivery that never
> > materialized...so I am leery of making any commitments to clients about
> > parts that I don't have in hand.
> >
> > Any info would be appreciated.
> >
> > Thanks!
> >
> >
> >


Article: 36618
Subject: Re: Incrementing counter from state-machine
From: Nial Stewart <nials@britain.agilent.com>
Date: Tue, 13 Nov 2001 16:50:33 +0000
Links: << >>  << T >>  << A >>
Jim wrote:
> 
>  If for any reason, the synthesis tool doesn't
> pick the global clock buffer for your clock, you can always add a global
> buffer marco in your code to force the tool to use one. Or try to use a
> better synthesis tool.

Jim,

With Altera's Acex devices (and all others I'm aware of) you're tied to 
using dedicated GClk pins. If you don't use them for your clocks you're 
stuffed.

Nial.

Article: 36619
Subject: Re: Incrementing counter from state-machine
From: jaroslawk@hotmail.com (Jerry)
Date: 13 Nov 2001 09:15:21 -0800
Links: << >>  << T >>  << A >>
Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:<3BF064BA.D3841344@iprimus.com.au>...
> > the process. Mixing both styles like your process creates latches.
> 
> But with synthesis, i think *everything* that gets assigned a value
> within a process, has to be in the sensitivity list or leonardo gives
> warnings. Only with a "wait until" line, does the process not have a
> sensitivity list.
>  

Russell,

Please note that VHDL synthesizers generate stupid warnings about signals
missing from the sensitivity list during initial syntax check of the code.
Those warnings are justified only for processes describing COMBINATORIAL
logic. In that case all signals _used_on_the_right-hand_side_ of assignments
should be in the sensitivity list. For clocked processes, such requirements 
are clear violation of common sense and basic VHDL rules. Issuing those
warnings is even more ridiculous if you consider that VHDL synthesizers
usually do not check sensitivity list while infering logic...
I do hope that somebody will kick synthesis tool vendors in the ass to remove
those stupid warnings - it worked (with loooong waiting time) to force
FPGA Express to support rising_edge/falling_edge functions...

Good luck,

Jerry

Article: 36620
Subject: Re: Xilinx s/w upgrade 4.1 problems
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 13 Nov 2001 18:19:42 +0100
Links: << >>  << T >>  << A >>
"Jim Bittman" <jmbj@bittware.com> schrieb im Newsbeitrag
news:3BF01451.5DD62639@bittware.com...

[ Complaints about Xilinx Sotware update ]

> I could go on, but here we have a seriously under-utilized device and a
> LOT of work
> to upgrade the software.  What gives - are we unique or is everyone just
> accepting

Hmmm, we did the upgrade too and had a LOT of trouble. Even with pure VHDL
designs. The Xilinx Software guys will have a LOT of bugs to fix :-(

> this as the necessary pain to upgrade???

As always, never change a running system. If your old Software runs O.K.
leave it this way, at least to the end of your current projects.

--
MfG
Falk





Article: 36621
Subject: Re: Place your orders....
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 13 Nov 2001 19:17:26 +0100
Links: << >>  << T >>  << A >>
Austin Lesea <austin.lesea@xilinx.com> writes:

> Lies, lies, and damned lies,
> 
> 2V6000's are yielding just fine.

I'm glad to hear that. My comment was not a confirmation on the rumor,
just a technical question. Would it be possible to by cheap partially
defective parts like I described, or would the logistics and support
be way to expensive to make it worth it?

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 36622
Subject: Clock Skew
From: #BASUKI ENDAH PRIYANTO# <PH892987@ntu.edu.sg>
Date: Wed, 14 Nov 2001 02:23:53 +0800
Links: << >>  << T >>  << A >>

When I synthesize my VHDL code, I have warning message that clock skew
may be happened in my design.
How to prevent clock skew ?

Do I need additional circuit / block diagram ?

Need advice.


Best regards,

Basuki


Article: 36623
Subject: Re: Timing constraints for multiple clock logic paths
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 13 Nov 2001 18:35:46 +0000
Links: << >>  << T >>  << A >>


G wrote:

> Hi,
> I'm using a Spartan II-50-5 with Base Express 3.3.08i.   I have a design where
> a main state machine sends out clock enables to registers in other areas.  A
> data path I have between two sets of registers contains combinatorial logic that
> takes ~17ns to complete.  My clock is 9ns.  Since I control when the clock
> enables happen in the main state machine, I know I have plenty of time to let
> that path chug.  How do I convey this information to the Xilinx tools?
> The par comes back saying that the 9ns clock can't be met because of these
> extra long paths.  I'd rather not pipeline the logic because that would use up
> a lot of FF's, which are already getting scarce.  Bigger/faster parts are also
> out due to cost.
>
> Thanks for any ideas or pointers,
>

You need a special timespec to cover the path. If TSClk is the name of the main
9nsec. PERIOD spec then it'll look something like in the UCF

TIMESPEC TS_myspec = FROM RegGrp1 TO RegGrp2  TSClk*2;

This works since a FROM/TO timespec has a higher priority than a PERIOD one
(assuming you are using a PERIOD spec).

Its really worth studying the constraints sections of the Development System
Reference Guide and the Libraries Guide esp. the bit about timespec priorities.

But BEWARE multicycle timespecs can catch you out if your code changes but the UCF
doesn't, its pretty hard to find ways of relating the two.




Article: 36624
Subject: Re: 'Timing' simulation in ModelSIM
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 13 Nov 2001 10:35:47 -0800
Links: << >>  << T >>  << A >>
Kris Nichols wrote:

> I get the following reported errors from ModelSIM when running a testbench
> (i.e. activ_func_sigmoid_tb.vhd) on an entity called 'activ_func_sigmoid':
> --------------------------------------------------
> ###### activ_func_sigmoid_tb.vhd(50): );
> # WARNING[1]: activ_func_sigmoid_tb.vhd(50): No default binding for
> component: "activ_func_sigmoid". (Port "input_value" is not on the entity)
. . .

> # ** Warning: Component uut is not bound.
> #    Time: 0 ns  Iteration: 0  Region: /testbench
> # ERROR: activ_func_sigmoid_ppar.sdf: The design does not have an instance
> named '/UUT'.

> 
> It seems that ModelSIM doesn't believe that a input port called
> 'input_value' doesn't exist in the entity, when in fact this port does
> exist. 

What it is trying to say is that *because* of port input_value,
your component UUT does not match the entity activ_func_sigmoid
prefectly, so your UUT is unplugged.

> Do you have any suggestions on how I can overcome this problem??

Either get the default binding to work by matching all the names
or use a configuration.

Here's one I used in a similar situation:
I ended up putting the delay model (.vho)
in a separate library to keep the identical
entity names from clashing.
----------------------------------------

configuration vital of test_xszero is
   for sim
      for dut:socket
         use entity vho.xszero(\ep1k50fc256-1\);
      end for;
   end for;
end configuration vital;

configuration fast of test_xszero is
   for sim      
      for dut:socket 
         use entity work.xszero(synth);
      end for;
   end for;
end configuration fast;
----------------------------------------
Modelsim was happy with both configs:
> vsim fast
  or
> vsim -sdfmax dut=xszero.sdo vital


   -Mike Treseler



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