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Messages from 36675

Article: 36675
Subject: Re: High Speed PWM?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Thu, 15 Nov 2001 11:14:47 +0100
Links: << >>  << T >>  << A >>
There are analog delay lines that can be attached externally - I made
such a design, to be viewed on one of my electonic pages.
These delay lines that offer sub-ns resolution are 30$ each, which
may restrict their use to advanced gear.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com

VR wrote:
> 
> Hey all.
> 
>
> 
> I was discussing this very issue with an engineer the other day who told
> me he was able to implement PWM control in an FPGA (a Spartan or something
> <= Virtex) along with several FIR filters AND not need a clock greater
> than 20MHz and also went on to mention he was able to get 1ns resolution
> of the duty cycle.
>

Article: 36676
Subject: Re: High Speed PWM?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 15 Nov 2001 23:16:47 +1300
Links: << >>  << T >>  << A >>
VR wrote:
> 
> Hey all.
> 
> I'm dealing with an interesting problem -- something I'm sure a lot of
> other people have come across...
> 
> The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is
> 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what
> I am seeking for the duty cycle control.
> 
> My implementation (and essentially all I've come across) use a counter
> that counts pulse-widths and after that some kind of "customization" sets
> the output.
> 
> The customization varies -- some people like to use a comparator and latch
> the output, others, like the Xilinx App note, like to use the Terminal
> Count on the counter and set an S-R flip-flop. My implementations in the
> past have essentially been like Xilinx's terminal count idea.
> 
> The problem however, is how to get >=200kHz with 10-bit control; for a
> 200kHz waveform one needs a 200kHz * 2^10 = 204.8MHz clock to clock the
> pulse-wdith counter! Even with PLLs and DLLs a 16-bit PWM would be murder.

By using a (nom) 50% clock, that can become the LSB, and you can halve 
the Max freq, bringing it down to 100MHz

> 
> I was discussing this very issue with an engineer the other day who told
> me he was able to implement PWM control in an FPGA (a Spartan or something
> <= Virtex) along with several FIR filters AND not need a clock greater
> than 20MHz and also went on to mention he was able to get 1ns resolution
> of the duty cycle.
>
> He was also clear that it was proprietary information and could not give
> me the specifics. I have every reason to believe he is not lying, that he
> has actually accomplished high-speed high-resolution PWM in an FPGA.
> 
> My interest in this problem has now increased exponentially (much like the
> clock needed for "standard" PWM implementations).
> 
> So the million dollar question is how might he have done it? I've been
> thinking of all sorts of things, but I still can't find an elegant
> solution.
> 
> The best I've been able to come with is this:
> 
> If one could get a 1ns delay out of an element, these elements could be
> strung together and at each "tap" feed the output into a 256:1 MUX or a
> 1024:1 MUX. The clock would be fed into the input of the 1st delay element
> and the selector bits on the MUX would give the desired PW.
> 
> That might be a good idea for a VLSI design, but not for an FPGA...
> 
> Anyway, I'm not sponsoring a competition, just wanted to hear some ideas
> ;).

 Top end FPGA's have such fractional clock steppers, but even the bottom
( right down to CPLD ) can use a calibrated delay line system, giving
high apparent clock rates.

 With PWM, it is usually the % that is critical, not the Freq, and if
you
target a N/M PWM, where BOTH N and M can vary, you can get finer 
( but more complex ) control.
 eg 50/100 = 50%, 50/101 = 49.5% - an 'apparent' PWM ratio of 1:200.

 This does have some freq deviation in the PWM out.

 Another technique, application dependant, is to dither many cycles of
PWM, 
for more (averaged) resolution. 
 If its used for a DAC, or power supply, this can be ideal.

 eg we have use UARTs as PWM generators, for DAC's, where the base
resolution
was 5 steps, then used /32 picket fence interpolate, for a 160 step DAC.
 So long as the dither is above the downstream filter bandwidth, it's
largely
invisible.

 If it's for a DAC app, then another solution is to split (say) a 12 Bit 
PWM into two 6 bit ones, and summ at the analog integrator.
 ( this does not work on a SMPS app )

- jg

Article: 36677
Subject: Re: interleaver delay question
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Thu, 15 Nov 2001 11:16:53 +0100
Links: << >>  << T >>  << A >>
FYI, a RAM cell is a Flipflop

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com

Allan Herriman wrote:
> 
> Yes, that's a lot of flip flops.  But I've never seen a large
> interleaver use flip flops for storage.
> 
> Try RAM.  It's much cheaper per bit.  You could use an external ram,
> or you could use ram inside an FPGA.
> Your application would use less than 10% of the ram on one of the
> larger FPGA devices.
>

Article: 36678
Subject: Re: High Speed PWM?
From: Francisco Camarero <francisco.camarero@acterna.com>
Date: Thu, 15 Nov 2001 11:27:09 +0100
Links: << >>  << T >>  << A >>

I have usually used PWM for motor control, where the duty cycle can be
redefined to be the average of the duty cycles among several cycles.

Under this assumption one can add some jitter to the switching time,
and in this way increase the 'apparent' resolution. 

Example: 

Let's assume a clock that is 4 times faster than the PWM to generate.
With 1-cycle definition of the duty cycle you can achieve following
duty cycles: 0%, 25%, 50%, 75% and 100%.
With a 2-cycle definition you can achieve:
  0%, 12.5%, 25%, 37.5%, 50%, 62.5%, 75%, 87.5% and 100%

Would this be an approach for you?



VR wrote:
> 
> Hey all.
> 
> I'm dealing with an interesting problem -- something I'm sure a lot of
> other people have come across...
> 
> The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is
> 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what
> I am seeking for the duty cycle control.
> 
> My implementation (and essentially all I've come across) use a counter
> that counts pulse-widths and after that some kind of "customization" sets
> the output.
> 
> The customization varies -- some people like to use a comparator and latch
> the output, others, like the Xilinx App note, like to use the Terminal
> Count on the counter and set an S-R flip-flop. My implementations in the
> past have essentially been like Xilinx's terminal count idea.
> 
> The problem however, is how to get >=200kHz with 10-bit control; for a
> 200kHz waveform one needs a 200kHz * 2^10 = 204.8MHz clock to clock the
> pulse-wdith counter! Even with PLLs and DLLs a 16-bit PWM would be murder.
> 
> I was discussing this very issue with an engineer the other day who told
> me he was able to implement PWM control in an FPGA (a Spartan or something
> <= Virtex) along with several FIR filters AND not need a clock greater
> than 20MHz and also went on to mention he was able to get 1ns resolution
> of the duty cycle.
> 
> He was also clear that it was proprietary information and could not give
> me the specifics. I have every reason to believe he is not lying, that he
> has actually accomplished high-speed high-resolution PWM in an FPGA.
> 
> My interest in this problem has now increased exponentially (much like the
> clock needed for "standard" PWM implementations).
> 
> So the million dollar question is how might he have done it? I've been
> thinking of all sorts of things, but I still can't find an elegant
> solution.
> 
> The best I've been able to come with is this:
> 
> If one could get a 1ns delay out of an element, these elements could be
> strung together and at each "tap" feed the output into a 256:1 MUX or a
> 1024:1 MUX. The clock would be fed into the input of the 1st delay element
> and the selector bits on the MUX would give the desired PW.
> 
> That might be a good idea for a VLSI design, but not for an FPGA...
> 
> Anyway, I'm not sponsoring a competition, just wanted to hear some ideas
> ;).
> 
> Thanks,
> VR.

Article: 36679
Subject: Re: interleaver delay question
From: Andrew MacCormack <andrewm@tality.com>
Date: Thu, 15 Nov 2001 10:56:54 +0000
Links: << >>  << T >>  << A >>
Rene Tschaggelar wrote:
> 
> FYI, a RAM cell is a Flipflop
> 
As the old joke goes:

"what's the difference between an elephant and a post box?"
"I don't know, what is the difference between an elephant and a post
box?"
"Oh, well, I won't send YOU to post this letter then"

A DRAM cell will usually be a single transistor, an SRAM cell is usually
two inverters with maybe gating transistors and a flipflop is two
latches, a latch being made up of at least 2 NAND or NOR gates. There's
more to it than that, but the point is that they are very different!

so I won't send YOU to design my convolutional interleaver... :-)



-- 
  ___#---   Andrew MacCormack               andrewm@tality.com
  L_   _|   Senior Design Engineer
    | |     Tality, Alba Campus, Livingston EH54 7HH, Scotland
    ! |     Phone: +44 1506 595360        Fax: +44 1506 595959
             
T A L I T Y                http://www.tality.com

Article: 36680
Subject: Re: Decoupling capacitors on Virtex II
From: "Philippe Robert" <PhilippeR@sundance.com>
Date: Thu, 15 Nov 2001 14:04:25 -0000
Links: << >>  << T >>  << A >>
Hi all,

Thanks for your answers. It did help me.
I have to confess that I have just been graduated and in consequence I do
not have much experience. There is something that confuses me is that you
guys are talking about bypass or decoupling capacitors.
What's the difference ?

Do you have any recent book to advice me about PCBs and high speed systems ?

Thanks for your help again.
Philippe.


"Russell Shaw" <rjshaw@iprimus.com.au> wrote in message
news:3BF068F4.F78E7495@iprimus.com.au...
> It should be easy to verify if your board will be ok. Just remove
> the caps around one chip, power-up, and look at glitch levels on
> the pins/pads with a high-speed cro (you'll need to have a good
> ground-pin on the cro probe). If the glitching is less than 10%
> of VCC, or adding the caps makes little difference, the caps
> aren't really needed. Its important that the power-ground
> planes are large in area, and adjacent (higher capacitance,
> lower pulse impedance). Standard 2/4-layer board probably
> wouldn't be good enough.
>
> Austin Lesea wrote:
> >
> > Russell,
> >
> > You must enjoy dangerous living ....
> >
> > And, the inductance of the flip chip packages is 5 to 8 times less than
that of
> > the wire bonded packages as there are no wires, just hundreds and
hundreds of tiny
> > solder balls over the entire top surface of the die connecting to ground
and
> > Vcc's.
> >
> > Austin
> >
> > Russell Shaw wrote:
> >
> > > pete dudley wrote:
> > > >
> > > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface
mount, like
> > > > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up
to 10uF
> > > > tantalums...
> > > >
> > > > We use terminated differential signalling for the high speed stuff
if
> > > > possible to cancel the ground bounce and use slew rate control on
the rest.
> > > >
> > > > On the highest end of the switching spectrum the ground/power planes
help
> > > > you and my guess is that 100pF or smaller chip caps do nothing for y
ou.
> > > >
> > > > Once we built some multiprocessor boards that ran about 150MHz but
the caps
> > > > were bad so we removed all of them. The boards ran fine without any
> > > > decoupling. I'd like to try that experiment again with high speed
fpga's.
> > > >
> > > > I like Austin's idea of tuning the caps to the operating frequency.
> > >
> > > With *thin* layers (such as in 8 layer boards etc), all the caps
> > > can be left off except one electro per board. The VCC and GND planes
> > > must be adjacent to provide very low planar transmission line
> > > impedance (lumped capacitance is meaningless at fast edges).
> > >
> > > A bit of track to bypass caps and vias hardly matters relative
> > > to the inductance in many internal bond wires.



Article: 36681
Subject: Re: Decoupling capacitors on Virtex II
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 15 Nov 2001 14:20:32 +0000
Links: << >>  << T >>  << A >>
"Philippe Robert" <PhilippeR@sundance.com> writes:

> Hi all,
> 
> Thanks for your answers. It did help me.
> I have to confess that I have just been graduated and in consequence I do
> not have much experience. There is something that confuses me is that you
> guys are talking about bypass or decoupling capacitors.
> What's the difference ?
> 

None in my experience.

> Do you have any recent book to advice me about PCBs and high speed systems ?
> 

Try High Speed Digital design - a handbook of black magic
 by Howard Johnson and Martin Graham. 
Buying link from Howard Johnson's site 
http://www.signalintegrity.com/books.htm

Cheers,
Martin
-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 36682
Subject: Re: ASRC (asynchronus sample rate conversion)
From: bevans@best.com (Brad Evans)
Date: 15 Nov 2001 06:59:54 -0800
Links: << >>  << T >>  << A >>
Another place to look is here:
http://www-s.ti.com/sc/psheets/slws130/slws130.pdf

This is a datasheet of a Graychip (now TI) digital resampler chip
developed awhile back and has some discussion of the interpolation
filter employed (4,096 15-tap sets). Used mostly for baud-timing
schemes in QAM demodulators and for sample rate adjustment of data
between different systems.

Brad Evans
http://www.graychip.com

Article: 36683
Subject: Re: Synopsys+Xilinx vs Synplicity
From: "Lee Weston" <lee.weston@philips.com>
Date: Thu, 15 Nov 2001 15:05:43 -0000
Links: << >>  << T >>  << A >>
Hi Brittle,

I use Synplify PRO 7 for synthesis of vhdl targeted for Synopsys DC (ie for
an ASIC). Apart from changing the obvious like pragmas to Synplicity equiv.
or if the design uses Synopsys attributes etc. I've had no real problems.

Compile times are quick on the PC. Resulting clock speed is the best I've
seen for the design. I target Altera 20K devices so I can't comment on a
route for Xilinx layout.

kind regards

Lee.

<khtsoi@cse.cuhk.edu.hk> wrote in message
news:9sqnh1$j6u$1@eng-ser1.erg.cuhk.edu.hk...
> Hi,
>
> Someone told me that tools from Synplicity is better than the Synopsys
> Xilinx combination in FPGA place and route process. I am sick with the
> bad routing design in Alliance3.1i. Also, it takes me more than 1 day
> to par a design using only 45% slices of a XCV1000E (on a Sun E4500).
>
> I really hope someone can give me some advices about the performance
> of the Synplicity tools. I will use it on either or both Sun E4500 with
> SunOS and P4 1.4GHz PC with Win/Linux. Does anyone has experience on
> implementing a design in similar size under these environment? Also,
> most of my current design is developed under Synopsys Design Compiler
> which cannot be synthsised directly on FPGA Express. Can the Synplicity
> tools under the synopsys coding style? Last, is there any performance
> differences between the commercial version and evaluation version?
>
> ---- Brittle
>
> PS I am now downloading the evaluation version of Synplify.



Article: 36684
Subject: Re: Decoupling capacitors on Virtex II
From: Keith R. Williams <krw@btv.ibm.com>
Date: Thu, 15 Nov 2001 11:10:17 -0500
Links: << >>  << T >>  << A >>
In article <3bf3ccab@peer1.news.newnet.co.uk>, PhilippeR@sundance.com 
says...
> Hi all,
> 
> Thanks for your answers. It did help me.
> I have to confess that I have just been graduated and in consequence I do
> not have much experience. There is something that confuses me is that you
> guys are talking about bypass or decoupling capacitors.
> What's the difference ?

Decoupling capacitors go from power to ground to decouple the sink 
(local voltage) from the inductance of the source (power network).  
Bypass capacitors go from power to ground to bypass AC noise from power 
to ground.  It's all how you were brought up and how you look at 
things. ;-)  

Actually, both are useful ways to look at the same problem.

----
  Keith 

Article: 36685
Subject: Re: Decoupling capacitors on Virtex II
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 15 Nov 2001 08:40:51 -0800
Links: << >>  << T >>  << A >>
More to consider than just bypassing....

 http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=si_pcbcheck

Austin

Philippe Robert wrote:

> Hi all,
>
> Thanks for your answers. It did help me.
> I have to confess that I have just been graduated and in consequence I do
> not have much experience. There is something that confuses me is that you
> guys are talking about bypass or decoupling capacitors.
> What's the difference ?
>
> Do you have any recent book to advice me about PCBs and high speed systems ?
>
> Thanks for your help again.
> Philippe.
>
> "Russell Shaw" <rjshaw@iprimus.com.au> wrote in message
> news:3BF068F4.F78E7495@iprimus.com.au...
> > It should be easy to verify if your board will be ok. Just remove
> > the caps around one chip, power-up, and look at glitch levels on
> > the pins/pads with a high-speed cro (you'll need to have a good
> > ground-pin on the cro probe). If the glitching is less than 10%
> > of VCC, or adding the caps makes little difference, the caps
> > aren't really needed. Its important that the power-ground
> > planes are large in area, and adjacent (higher capacitance,
> > lower pulse impedance). Standard 2/4-layer board probably
> > wouldn't be good enough.
> >
> > Austin Lesea wrote:
> > >
> > > Russell,
> > >
> > > You must enjoy dangerous living ....
> > >
> > > And, the inductance of the flip chip packages is 5 to 8 times less than
> that of
> > > the wire bonded packages as there are no wires, just hundreds and
> hundreds of tiny
> > > solder balls over the entire top surface of the die connecting to ground
> and
> > > Vcc's.
> > >
> > > Austin
> > >
> > > Russell Shaw wrote:
> > >
> > > > pete dudley wrote:
> > > > >
> > > > > Our bread and butter decoupling cap is .01uF (10nF) 0805 surface
> mount, like
> > > > > 1 per 4 VCC on fpga's, and we back them up with a few larger caps up
> to 10uF
> > > > > tantalums...
> > > > >
> > > > > We use terminated differential signalling for the high speed stuff
> if
> > > > > possible to cancel the ground bounce and use slew rate control on
> the rest.
> > > > >
> > > > > On the highest end of the switching spectrum the ground/power planes
> help
> > > > > you and my guess is that 100pF or smaller chip caps do nothing for y
> ou.
> > > > >
> > > > > Once we built some multiprocessor boards that ran about 150MHz but
> the caps
> > > > > were bad so we removed all of them. The boards ran fine without any
> > > > > decoupling. I'd like to try that experiment again with high speed
> fpga's.
> > > > >
> > > > > I like Austin's idea of tuning the caps to the operating frequency.
> > > >
> > > > With *thin* layers (such as in 8 layer boards etc), all the caps
> > > > can be left off except one electro per board. The VCC and GND planes
> > > > must be adjacent to provide very low planar transmission line
> > > > impedance (lumped capacitance is meaningless at fast edges).
> > > >
> > > > A bit of track to bypass caps and vias hardly matters relative
> > > > to the inductance in many internal bond wires.


Article: 36686
Subject: Re: Xpower and vcd files
From: Dennis McCrohan <mccrohan@xilinx.com>
Date: Thu, 15 Nov 2001 09:01:21 -0800
Links: << >>  << T >>  << A >>
Steven Derrien wrote:

> Hello,
>
> I was wondering if someone had been playing with the new XPoxer tool. As
> far as I understood form the documentation, getting precise power
> estimations requires the design beeing simulated to produce a VCD report
> file (for toggle rates). I have two question regarding this :
>
> 1) I guess that one has to simulate the VHDL model of the annotated
> placed & routed design; and trace all primitives activity for a while to
> get a good idea of the circuit behavior, however, for large design, this
> is likely to be VERY time consuming, if not impossible due to the tool
> stability or PC memory limits. Can someone give his opinion about this ?
>
> 2) Xilinx support says one has to use Modelsim to guarantee proper work
> of the tool
> Alas, we only have Synopsys VHDL simulator, which can also produce VCD
> report file, but which is not 'officilially' supported by the tool. Has
> anybody experienced Xpower/VSS compatibilty problems ?
>
> Thanks,
>
> Steven
>
> PS: Xilinx rep. are welcome to answer these questions :))

Oh, man, I probably shouldn't ;-)

I'll start with the standard disclaimer that in this newsgroup, I speak only
for myself, and most definitely not for Xilinx.

That done, I'll  confess to being one of the developers on the XPower team.
When we designed the simulation interface for XPower, we knew we had two
principle problems:
1. That simulation data, particularly in ASCII format, for any real design
is huge.
2. That we had access to a limited number of simulators, and a limited
amount of time for testing simulators.

The VCD file format was chosen because it is an industry standard and widely
available. The obvious downside is the file is anything but compact. Our
decision to officially support only ModelSim was driven by the fact that
that simulator is what we OEM with our tools, and the development team (me
again) had easy access to it. We spend a lot of time discussing how we
should phrase our support for other simulators. Fact of the matter is, since
the VCD format is specified in the IEEE Verilog LRM, in theory, any
simulator's output should work in XPower. In practice, minor variations in
the format produced by different simulators can cause problems, and we don't
want to warrant what we can't test thoroughly.

Looking forward to our future releases, we are actively working on several
fronts. Internally to XPower, we've worked to clean up our code a bit and
make it more efficient. We (the developers) are seeing good improvements in
run time already from this. We are getting access to additional simulators,
and testing with them. And finally, we are looking at alternatives to the
VCD format for interfacing with simulators.

That said, I would certainly be interested in hearing from you on your
experiences using the Synopsys simulator. I'd also be happy to accept your
design files (NGD and VCD) if you are willing to let us have them for
testing purposes.

-Dennis McCrohan
Xilinx CPLD Software



Article: 36687
Subject: CAM
From: tadesa@hotmail.com (Tadesa)
Date: 15 Nov 2001 10:06:20 -0800
Links: << >>  << T >>  << A >>
Where can i find what CAM is and how to implement it? Can I write to it?

regards,
Tadesa

Article: 36688
Subject: Re: CAM
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 15 Nov 2001 11:38:56 -0800
Links: << >>  << T >>  << A >>
CAM stands for Content Addressable Memory.
When you read from it, you specify the stored data, and the CAM outputs the
location where such data is stored. ( that's opposite from a normal RAM)
CAMs are much more complicated to design and build than "ordinary" RAMs,
especially if you include the "don't care" option for the data that you present,
and also when you have to deal with the fact that the requested data may be
stored in more than one location.
Peter Alfke
========================
Tadesa wrote:

> Where can i find what CAM is and how to implement it? Can I write to it?
>
> regards,
> Tadesa


Article: 36689
Subject: How can I solve the "clock" warning of synplify.
From: "duola" <deerlux@hotmail.com>
Date: Thu, 15 Nov 2001 11:56:50 -0800
Links: << >>  << T >>  << A >>
When I synthesized my design using Synplify I got the following warning:"Net
G_3 appears to
be a clock source which was not identified. Assuming default frequency" Does
it mater? How can I solve the problem?




Article: 36690
Subject: Why can not I find the 2S200PQ208 in the aldec's Spartan2 familly?
From: "duola" <deerlux@hotmail.com>
Date: Thu, 15 Nov 2001 12:06:52 -0800
Links: << >>  << T >>  << A >>
I use Synplify's batch mode in Aldec's Active HDL.But I cannot find
2S200PQ208 in the synthesis option.It can be found in Synplify's main
environment.Is there any problems in Active HDL or Synplify?




Article: 36691
Subject: Re: High Speed PWM?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 15 Nov 2001 12:07:38 -0800
Links: << >>  << T >>  << A >>
Don't count us out!
Virtex-II has an interesting feature in the digital clock manager that lets you
step the clock phase in increments of 1/256 of the clock period.
Assume a 40 MHz clock, then each increment is close to 100 picoseconds.
( You can get as fine as 50 ps @ 80 MHz ). And each device has at least 4 of
these DCMs, even in the tiny Virtex-II40.
I would do the 6 MSBs with a counter, then use the DCM for the 4 LSBs,
fine-stepping with better resolution than you are asking for.
The limitation is that the phase-stepping of one increment ( say 100 ps at 40
MHz) takes up to 85 clock ticks. So you cannot change your setting instantly,
but you can do it easily at your 200 kHz rate.

Think about it, and use the simple evaluation board with a Virtex-II40 on it,
available from the Xilinx distributors.

Fun project!

Peter Alfke, Xilinx Applications.
==================================
VR wrote:

> Hey all.
>
> I'm dealing with an interesting problem -- something I'm sure a lot of
> other people have come across...
>
> The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is
> 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what
> I am seeking for the duty cycle control.
>
> My implementation (and essentially all I've come across) use a counter
> that counts pulse-widths and after that some kind of "customization" sets
> the output.
>
> The customization varies -- some people like to use a comparator and latch
> the output, others, like the Xilinx App note, like to use the Terminal
> Count on the counter and set an S-R flip-flop. My implementations in the
> past have essentially been like Xilinx's terminal count idea.
>
> The problem however, is how to get >=200kHz with 10-bit control; for a
> 200kHz waveform one needs a 200kHz * 2^10 = 204.8MHz clock to clock the
> pulse-wdith counter! Even with PLLs and DLLs a 16-bit PWM would be murder.
>
> I was discussing this very issue with an engineer the other day who told
> me he was able to implement PWM control in an FPGA (a Spartan or something
> <= Virtex) along with several FIR filters AND not need a clock greater
> than 20MHz and also went on to mention he was able to get 1ns resolution
> of the duty cycle.
>
> He was also clear that it was proprietary information and could not give
> me the specifics. I have every reason to believe he is not lying, that he
> has actually accomplished high-speed high-resolution PWM in an FPGA.
>
> My interest in this problem has now increased exponentially (much like the
> clock needed for "standard" PWM implementations).
>
> So the million dollar question is how might he have done it? I've been
> thinking of all sorts of things, but I still can't find an elegant
> solution.
>
> The best I've been able to come with is this:
>
> If one could get a 1ns delay out of an element, these elements could be
> strung together and at each "tap" feed the output into a 256:1 MUX or a
> 1024:1 MUX. The clock would be fed into the input of the 1st delay element
> and the selector bits on the MUX would give the desired PW.
>
> That might be a good idea for a VLSI design, but not for an FPGA...
>
> Anyway, I'm not sponsoring a competition, just wanted to hear some ideas
> ;).
>
> Thanks,
> VR.


Article: 36692
Subject: Re: High Speed PWM?
From: VR <fastpwm@isfastpwmpossible.com>
Date: Thu, 15 Nov 2001 23:15:46 +0000 (UTC)
Links: << >>  << T >>  << A >>
VR <fastpwm@isfastpwmpossible.com> wrote:
> Hey all.

> I'm dealing with an interesting problem -- something I'm sure a lot of
> other people have come across...

> The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is
> 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what
> I am seeking for the duty cycle control.

BTW, for those who are wondering, THIS IS NOT A HOMEWORK ASSIGNMENT.

This is actually for a personal project and for the record, all questions
I post in this newsgroup & other groups are related to one or more
personal projects, not school work.

Thanks,
VR.

Article: 36693
Subject: Re: High Speed PWM?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 15 Nov 2001 16:20:38 -0800
Links: << >>  << T >>  << A >>
Strange world.
First you sign with initials only, plus a fake e-mail address,
then you receive several friendly and constructive answers.
But then you find it necessary to tell us it's not homework...
Makes one wonder...
Peter Alfke
========================
VR wrote:

> VR <fastpwm@isfastpwmpossible.com> wrote:
> > Hey all.
>
> > I'm dealing with an interesting problem -- something I'm sure a lot of
> > other people have come across...
>
> > The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is
> > 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what
> > I am seeking for the duty cycle control.
>
> BTW, for those who are wondering, THIS IS NOT A HOMEWORK ASSIGNMENT.
>
> This is actually for a personal project and for the record, all questions
> I post in this newsgroup & other groups are related to one or more
> personal projects, not school work.
>
> Thanks,
> VR.


Article: 36694
Subject: jtag programming xilinx cpld
From: "Daniel Nilsson" <e9danneREMOVE_THIS@etek.chalmers.se>
Date: Fri, 16 Nov 2001 04:14:42 +0100
Links: << >>  << T >>  << A >>
Hi.
I need info on the various op-codes used in jtag accessing xc95xx cpld:s to
test my homedeveloped jtag access software, the opcodes I am particularly
interrested in are:

idcode
bypass
extest
highz
sample/preload

I am also interrested in the lengths of the opcodes (how many bits)

/Daniel Nilsson, M.Sc.EE student



Article: 36695
(removed)


Article: 36696
Subject: Re: High Speed PWM?
From: Eric <erv_fedupwith_spam@sympatico.ca>
Date: Thu, 15 Nov 2001 22:59:30 -0500
Links: << >>  << T >>  << A >>
Hi,

You might read this page :

http://www.free-ip.com/lib1/dac.html
and the Xilinx delta-sigma DAC app note :
http://www.xilinx.com/xapp/xapp154.pdf
and ADC made with it :
http://www.xilinx.com/xapp/xapp155.pdf

Suitability depends on the acceptable
settling time, and SNR at 200 Khz.
Active analog post filtering would also
improve the situation.

Also, the 1 ns resolution on the duty
cycle might be an averaged value.

hope this helps with your "not a homework" project.

Eric.

------------------------------------------------

VR a écrit :

> Hey all.
>
> I'm dealing with an interesting problem -- something I'm sure a lot of
> other people have come across...
>
> The issue is how to get a high speed (>=200kHz) 10-bit PWM signal. That is
> 200kHz is the frequency of the PWM waveform, and 10-bit resolution is what
> I am seeking for the duty cycle control.
>
> My implementation (and essentially all I've come across) use a counter
> that counts pulse-widths and after that some kind of "customization" sets
> the output.
>
> The customization varies -- some people like to use a comparator and latch
> the output, others, like the Xilinx App note, like to use the Terminal
> Count on the counter and set an S-R flip-flop. My implementations in the
> past have essentially been like Xilinx's terminal count idea.
>
> The problem however, is how to get >=200kHz with 10-bit control; for a
> 200kHz waveform one needs a 200kHz * 2^10 = 204.8MHz clock to clock the
> pulse-wdith counter! Even with PLLs and DLLs a 16-bit PWM would be murder.
>
> I was discussing this very issue with an engineer the other day who told
> me he was able to implement PWM control in an FPGA (a Spartan or something
> <= Virtex) along with several FIR filters AND not need a clock greater
> than 20MHz and also went on to mention he was able to get 1ns resolution
> of the duty cycle.
>
> He was also clear that it was proprietary information and could not give
> me the specifics. I have every reason to believe he is not lying, that he
> has actually accomplished high-speed high-resolution PWM in an FPGA.
>
> My interest in this problem has now increased exponentially (much like the
> clock needed for "standard" PWM implementations).
>
> So the million dollar question is how might he have done it? I've been
> thinking of all sorts of things, but I still can't find an elegant
> solution.
>
> The best I've been able to come with is this:
>
> If one could get a 1ns delay out of an element, these elements could be
> strung together and at each "tap" feed the output into a 256:1 MUX or a
> 1024:1 MUX. The clock would be fed into the input of the 1st delay element
> and the selector bits on the MUX would give the desired PW.
>
> That might be a good idea for a VLSI design, but not for an FPGA...
>
> Anyway, I'm not sponsoring a competition, just wanted to hear some ideas
> ;).
>
> Thanks,
> VR.


Article: 36697
Subject: Pinning in Lattice Design Expert
From: "Gunther May" <g.may@tu-bs.de>
Date: Fri, 16 Nov 2001 12:05:23 +0100
Links: << >>  << T >>  << A >>
Hello FPGA experts,

could you please help me in this problem:
I would like to design a simple GAL 16V8 for decoding gray code to binary; I
need 4 input and 4 output pins for that. Where do I have to set the physical
pins of the device on which I would like to map these functions?
I found an example, where that was done in an abel test vector file like
that:

"Inputs
 a0   pin 2;
 a1   pin 3;
 a2   pin 4;
 a3   pin 5;

"Outputs
 b0   pin 12;
 b1   pin 13;
 b2   pin 14;
 b3   pin 15;

Somwhere later in the design cycle there were complete different pin numbers
assigned to the functions.
Are these declarations correct or do I have to do them somewhere else? Or
are there different enumerations of the pins (I used the phyiscal pin
numbers of the device).

Thank you very much,
Gunther May





Article: 36698
Subject: Re: jtag programming xilinx cpld
From: "Jim" <johnsonw10@hotmail.com>
Date: Fri, 16 Nov 2001 13:06:53 GMT
Links: << >>  << T >>  << A >>
The info can be found in BSDL files. The following is taken from
xc95108.bsd. Check http://www.xilinx.com/support/sw_bsdl.htm for other
devices.

 "BYPASS ( 11111111)," &
 "CONLD ( 11110000)," &
 "EXTEST ( 00000000)," &
 "FERASE ( 11101100)," &
 "FPGM ( 11101010)," &
 "FVFY ( 11101110)," &
 "HIGHZ ( 11111100)," &
 "IDCODE ( 11111110)," &
 "INTEST ( 00000010)," &
 "ISCEN ( 11101000)," &
 "SAMPLE ( 00000001)," &
 "USERCODE ( 11111101)" ;

"Daniel Nilsson" <e9danneREMOVE_THIS@etek.chalmers.se> wrote in message
news:9t1vrr$6s4$1@eol.dd.chalmers.se...
> Hi.
> I need info on the various op-codes used in jtag accessing xc95xx cpld:s
to
> test my homedeveloped jtag access software, the opcodes I am particularly
> interrested in are:
>
> idcode
> bypass
> extest
> highz
> sample/preload
>
> I am also interrested in the lengths of the opcodes (how many bits)
>
> /Daniel Nilsson, M.Sc.EE student
>
>



Article: 36699
Subject: Re: CAM
From: tadesa@hotmail.com (Tadesa)
Date: 16 Nov 2001 06:25:52 -0800
Links: << >>  << T >>  << A >>
I see what CAM is, but if you are using xilinx-Virtex family fpga (I
read the documentation) how can i use it? do i have to build the CAM?
If it is already there how can i use it? (in VHDL)

Many Thanks
-Tadesa


Peter Alfke <peter.alfke@xilinx.com> wrote in message news:<3BF419D0.1156DD19@xilinx.com>...
> CAM stands for Content Addressable Memory.
> When you read from it, you specify the stored data, and the CAM outputs the
> location where such data is stored. ( that's opposite from a normal RAM)
> CAMs are much more complicated to design and build than "ordinary" RAMs,
> especially if you include the "don't care" option for the data that you present,
> and also when you have to deal with the fact that the requested data may be
> stored in more than one location.
> Peter Alfke
> ========================
> Tadesa wrote:
> 
> > Where can i find what CAM is and how to implement it? Can I write to it?
> >
> > regards,
> > Tadesa



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