Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hello, Foundation ISE4.1 comes with FPGA Express, when I'm right. Is this FPGA Express restricted to Xilinx devices? Or can one use it for Altera, provided the libraries are available? I have installed an older version of Viewlogic with FPGA Express used for Altera's and now I'm wandering what happens if I install Foundation beside it. What happens to enviroment variables, which libraries will be found by which program. Best would be to use only the new version of FPGA Express and tell it to use both Xilinx and Altera libs. Is that possible? Cheers, ER!K -- Dr. Erik Lins, Projektleiter HighTronix GmbH, 35578 Wetzlar Telefon 06441-952010, Telefax -952012 e.lins@hightronix.de, www.hightronix.deArticle: 36801
Hi, Experts, Here is a challenge of implementing a design generated from Xilinx System Generator. The design kit I used are as follows: Matlab5.3R11 Xilinx System Generator 1.1 Synplify Pro 6.2.4 Xilinx Foundation 3.1i Celoxica DK1 (Handel C3.0) FPGA Board: Celoxica RC1000-PP The design is basically a algorithm that contains some fixed-point adders and multipliers and a register at the output of the model. An feedback loop was used to take the register output back to one of the adder's input port (similarly like an integrate loop). It was constructed using Xilinx Blocksets in Matlab Simulink Enviroment. Xilinx System Generator was used to generate VHDL codes from the model. The VHDL codes generated by SysGen can be synthesized and implemented successfully on a Xilinx XCV1000BG560-4 chip. Now I want to instanciated these codes with a top-level FPGA card entity. The FPGA card entity works as the interface between the FPGA chip and outside RAMs which are on a Celoxica RC1000-PP card. The problem is that the implementation tool removed all of the logics blocks generated by Systen Generator. To verify the problem, I tested the FPGA card interface entity(Top-Level entity of this design) with other VHDL codes generated from a different model, which contains adders and multipliers, but no registered feedback loops, and found that it works well. No logic Blocks (adders/multipliers) were removed away in this implementation. To summerize the description of the design and the problem with it: 1. A simulink model consists of adders and constant multipiers, a resetable register at the output end of the model, and a feedback loop from the register out port to one of an adder's input port. 2. Code generated from the above model can be synthesized and implemented correctly on Xilinx XVC1000BG560-4 chip if no FPGA card interface is added to the design. 3. Codes generated from the model with FPGA card interface can not be implemented correctly. All of the logic blocks in the model were removed away; 4. Codes generated from a different model, which contains no registers at the output end and no feedback loops, can be implemented correctly with the FPGA card interface. I assume the problems come from the register and feedback loop used in the first simulink model. But I dont know how to solve the problem!!! Could anybody please help me to crack it down? I can email the design file archive for a quick referece. Thanks a lot in advance!! -- Jianyong Niu ------------------------------- Rolls-Royce UTC ACSE, Univ of Sheffield B20 Amy Johnson Building Mappin St. Sheffield S1 3JD, UK Tel: +44 (0)114 2225236 Fax: +44 (0)114 2225138 Email: jyniu@acse.shef.ac.uk Jianyong Niu --------------------------------------------------- Rolls-Royce UTC ACSE, Univ of Sheffield B20 Amy Johnson Building Mappin St. Sheffield S1 3JD, UK Tel: +44 (0)114 2225236 Fax: +44 (0)114 2225138 Email: jyniu@acse.shef.ac.ukArticle: 36802
Leon Heller wrote: > Sorry, I've just checked the Xilinx version. It is only for small designs. > > -- > Leon Heller, G1HSM leon_heller@hotmail.con > http://www.geocities.com/leon_heller > Low-cost Altera Flex design kit: http://www.leonheller.com It will work with much larger designs. It just runs slower.Article: 36803
Hmm, why don't you use the CLKDLLs for this. It can be set up to produce a divide by
3 clock. That divided clock can be used to increment a sequencer to generate count_3.
At 165 Mhz, you are near the upper limit of the clock range for a -4 part. The
connection from init_count to dount_delayed is from a rising edge to falling edge FF,
so you only have half the period (about 2 ns) to work with. That absolutely needs to
be floorplanned and cannot have any logic between the registers to work at 165 in this
part. The count delayed will have to be in the adjacent slice to count_init to take
advantage of the fast intra-CLB routing. The gating for your count output and
clk_div_3 outputs will skew the output timing significantly wrt your clocks.
Antonio wrote:
> Good Morning,
> I've the following counter divider 3 , my problem is that it works
> only at a maximum of 150MHz while I need to keep it working to 165 MHz
> at least on a Xilinx XCV1000 BG560 -4 . I try to use Synplify Pro that
> tells that to speed up I've to "changing pad type from OBUF to
> OBUF_F_24 for pad clk_div_3_obuf to improve timing" and the same for
> "count_3_obuf" but how I could do this ??
> Following is the counter, by the way do you have in mind another way
> to speed it up (other than buy another device !!!). Ciao
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_unsigned.all;
>
> entity counter_divider_3 is
> port (
> clk : in STD_LOGIC;
> reset : in STD_LOGIC;
> count_3 : out STD_LOGIC_VECTOR (2 downto 0);
> clk_div_3 : out STD_LOGIC
> );
> end counter_divider_3;
>
> architecture counter_divider_3_arch of counter_divider_3 is
> signal int_count_3 : STD_LOGIC_VECTOR (1 downto 0) ;
> signal reset_clk_a_b : STD_LOGIC_VECTOR (3 downto 0) ;
> signal count_0_delayed : STD_LOGIC;
> begin
>
> process (clk, reset)
> begin
> if reset='1' then
> int_count_3 <= "01";
> elsif rising_edge(clk) then
> -- & funziona come aggregatore di bit non un and logico !!
> int_count_3 <= int_count_3(0) & not(int_count_3(0) or
> int_count_3(1));
> end if;
> end process;
>
> process(clk)
> begin
> if falling_edge(clk) then
> count_0_delayed <= int_count_3(0);
> end if;
> end process;
>
> clk_div_3 <= int_count_3(0) nor count_0_delayed;
>
> with int_count_3 select
> count_3 <= "010" when "00" ,
> "001" when "10" ,
> "000" when "01" ,
> "XXX" when others;
> end counter_divider_3_arch;
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36804
I am looking for a PCI development board to use with the Xilinx PCI32 core
and a Spartan 2 or XL FPGA. I would like to use the Virtual Computer Hot2
board since the PCI32 core comes with the board and it would allow me to
test the core before I buy it. Unfortunately these boards are out of stock
for awhile. Does anybody have one of these that they would like to sell?
Also, while I am at it, does anybody have good/bad experience with this
board relative to the Insight PCI development board? Thanks in advance
George Stein
Article: 36805Hi ! Could anyone give a quick guess for the price of a Altera EP20K200E in a PQ208 Package (mid speed grade) and for the Actel A500K270 in this package (if applicable). I need this for a very rough price comparison with Xilinx and dont want to wake up sleeping dogs at the distributors. (The freetradezone does only give me the approx. price for the Xilinx part, 100 quantity.) Regards, TobiasArticle: 36806
Thanks! That's the info I was looking for... I am in the middle of one project, that I have been using the 3.x tools for, and have NO desire to update the currently working perfectly tools just to find out that something doesn't work...I learned that from past experience...many times! I'll find out about the V2 device update, thanks again! <hamish@cloud.net.au> wrote in message news:3bfa2ffd$0$21656$afc38c87@news.optusnet.com.au... > Austin Franklin <austin@da22rkroom.com> wrote: > > I thought I had a full installation of the latest 3.x tools...and brought up > > the FPGA Editor...but it doesn't seem to allow me to select any of the > > Virtex 2 parts... Does anyone know if this is supposed to be available in > > FPGA Editor with the 3.x tools? If not, then is it available with the 4.x > > tools? > > You need 3.1i, plus the Virtex-II device update, plus service pack 8, > installed in that order. The device update includes service pack 6, but > if you install it after SP8, you need to reinstall SP8. > > I don't know if you can download the device update. I have it on CD-ROM. > I'd stick with 4.1i SP2 anyway -- much better for new designs IMHO. > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 36807
MAX3000 has more ground connections and is also cheaper but basically the same. You can interchange them as long as you keep track what the different ground pins are on a MAX7000A. "Utku Ozcan" <ozcan@netas.com.tr> wrote in message news:3BFA58D9.4354E738@netas.com.tr... > > Subject explains: What is the most obvious difference > between MAX3000A and MAX7000A (3.3 V) devices? > > Everything seems to be same: speed grade, I/O support, > JTAG. > > The only difference I can find so far is that MAX7000A > is a family of wider gate-count spectrum. > > UtkuArticle: 36808
Russell Shaw wrote: > > Andy Peters wrote: > > > > Russell Shaw wrote: > > > > > I traced from the clock input pin to the clock divider, and looked at > > > the fanout from the last flip-flop. I found there were a few counters > > > implemented as scattered logic, not being recognized as counter > > > templates. I found just one or two extra lines in a process can prevent > > > recognition by the compiler as a counter. > > > > I noticed that about Leonardo -- it's VERY picky about what it considers > > a counter. > > > > What's bizarre is that I ran Leonardo on two different machines (one a > > Sparc running Solaris 7, the other running Solaris 2.5) and I got > > different results (the 2.5 machine did the right thing for a counter; > > the S7 machine didn't!) for identical code with identical scripts. I > > haven't gotten to the bottom of that one yet. > > > > Moral: pay attention to the report and log files. > > Maybe there's an option for time-limiting the optimizations. > Did the faster machine optimize better? Nawww, the fact that it couldn't recognize this particular counter made the design blow up. Very odd. -aArticle: 36809
Or slv(9 downto 0) <= to_stdlogicvector(X"3AC"); I think this should work - with both vhdl'87 and '93. -sanjayArticle: 36810
In article <9sr4p0$idl$1@news.ua.es>, fede <fedeg@terra.es> wrote: >Hi > >Are there anybody who implemented elliptic curves cryptographic algorithms >in some fpga? >thanks I haven't implemented them in an FPGA, but I do have a minor notes-primer on the subject of Elliptic Curves in general (see http://www.cs.berkeley.edu/~nweaver/ellipticNotes.pdf ). The more interesting question is why do you want to do ECC instead of RSA? ECC still requires large number division to accomplish, there have been plenty of implementations of RSA on FPGAs, and RSA is no longer encumbered by patent restrictions. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 36811
Hi,
I am designing a system where I have multiple (16) clocks coming
from 4 DCM's in a Virtex2. These clocks are staggered by an equal phase
delay such that the clocks are phase delayed by 360/16 degrees from each
other. I am then latching these into a sixteen bit latch. I need to
know when in the cycle the latch pulse occurs. To determine this I am
looking for a series of '1's followed by a zero in the 16 bit data
word. In the simulation I may get an X (unknown) in the edge between
the 1's and 0's. For example, "1111 X000 0000 X111" or "00X1 1111 11X0
0000". As a result I am looking for at least 6 '1's in a row. I have
written code using if-then-else that is similar in function to a
priority encoder. The simulation returns an unknown due to the
potential X values in the data word. Is there a way to override these
to appear as either all '0's or all '1's?
Here is the if-then-else structure. Obviously I would rather use a case
statement. Can any one show me a simple way to do so without hand
encoding every value?
Can anyone tell me a way to get the system to ignore the X's or
something similar so that I can get my simulation to work? The one
sample uncertainty cased by the X is not a worry. No results is a pain
in the ___.
process(phase_temp, count)
begin
if falling_edge(count) then
phase(15 downto 0)<=phase_temp(15 downto 0);
end if;
end process;
process(phase)
begin
if (phase(8)='0' and phase(7 downto 2)="111111") then
data_out_temp(3 downto 0)<=int2vec(15, 4);
elsif (phase(9)='0' and phase(8 downto 3)="111111") then
data_out_temp(3 downto 0)<=int2vec(0, 4);
elsif (phase(10)='0' and phase(9 downto 4)="111111") then
data_out_temp(3 downto 0)<=int2vec(1, 4);
elsif (phase(11)='0' and phase(10 downto 5)="111111") then
data_out_temp(3 downto 0)<=int2vec(2, 4);
elsif (phase(12)='0' and phase(11 downto 6)="111111") then
data_out_temp(3 downto 0)<=int2vec(3, 4);
elsif (phase(13)='0' and phase(12 downto 7)="111111")then
data_out_temp(3 downto 0)<=int2vec(4, 4);
elsif (phase(14)='0' and phase(13 downto 8)="111111") then
data_out_temp(3 downto 0)<=int2vec(5, 4);
elsif (phase(15)='0' and phase(14 downto 9)="111111") then
data_out_temp(3 downto 0)<=int2vec(6, 4);
elsif (phase(0)='0' and phase(15 downto 10)="111111") then
data_out_temp(3 downto 0)<=int2vec(7, 4);
elsif (phase(1)='0' and phase(15 downto 11)="11111" and phase(0)='1')
then
data_out_temp(3 downto 0)<=int2vec(8, 4);
elsif (phase(2)='0' and phase(15 downto 12)="1111" and phase(1 downto
0)="11") then
data_out_temp(3 downto 0)<=int2vec(9, 4);
elsif (phase(3)='0' and phase(15 downto 13)="111" and phase(2 downto
0)="111") then
data_out_temp(3 downto 0)<=int2vec(10, 4);
elsif (phase(4)='0' and phase(15 downto 14)="11" and phase(3 downto
0)="1111") then
data_out_temp(3 downto 0)<=int2vec(11, 4);
elsif (phase(5)='0' and phase(15)='1' and phase(4 downto 0)="11111")
then
data_out_temp(3 downto 0)<=int2vec(12, 4);
elsif (phase(6)='0' and phase(5 downto 0)="111111") then
data_out_temp(3 downto 0)<=int2vec(13, 4);
elsif (phase(7)='0' and phase(6 downto 1)="111111") then
data_out_temp(3 downto 0)<=int2vec(14, 4);
end if;
end process;
By the way, the purpose of this code is give me a very precise
measurement of a pulse width. The main clock is 200MHz, thus, in
theory, the resolution is equivalent to using a 3.2GHz clock. I tried
to use multiple counters and sum the resultant count values, but I was
limited by the clock routing capacity of the virtex2. In theoy, there
are 16 clock muxes, but in practice you are lucky to use more than 8.
This greatly limits the required number of clock channels, as the 16
phases are not really clock channels. They do require low skew routing,
however.
Thanks,
Theron Hicks
Article: 36812Three comments: 1.The X is really "only" a simulation issue. In reality, the latch will either be 0 or 1. X only exists in the unreal world of simulation. :-( 2. A BlockRAM can make a nice encoder, especially when you can use both ports independently... 3. I still prefer your original counter approach, but I would use 16 binary ripple counters ( each composed of cascaded 2-bit Johnson counters in a slice). Thus the routing delays don't matter. Wait a little after closing the last gate, then perform the addition. Could be done in a serial adder, since you probably have plenty of time after the end of the capture. Just thinking... Peter Alfke ========================== Theron Hicks wrote: > Hi, > I am designing a system where I have multiple (16) clocks coming > from 4 DCM's in a Virtex2. These clocks are staggered by an equal phase > delay such that the clocks are phase delayed by 360/16 degrees from each > other. I am then latching these into a sixteen bit latch. I need to > know when in the cycle the latch pulse occurs. To determine this I am > looking for a series of '1's followed by a zero in the 16 bit data > word. In the simulation I may get an X (unknown) in the edge between > the 1's and 0's. For example, "1111 X000 0000 X111" or "00X1 1111 11X0 > 0000". As a result I am looking for at least 6 '1's in a row. <snip> > By the way, the purpose of this code is give me a very precise > measurement of a pulse width. The main clock is 200MHz, thus, in > theory, the resolution is equivalent to using a 3.2GHz clock. I tried > to use multiple counters and sum the resultant count values, but I was > limited by the clock routing capacity of the virtex2. In theoy, there > are 16 clock muxes, but in practice you are lucky to use more than 8. > This greatly limits the required number of clock channels, as the 16 > phases are not really clock channels. They do require low skew routing, > however. > > Thanks, > Theron HicksArticle: 36813
maybe you could try to search on http://www.usbid.com Rafael Tobias Stumber schrieb: > Hi ! > > Could anyone give a quick guess for the price of a > Altera EP20K200E in a PQ208 Package (mid speed grade) > and for the Actel A500K270 in this package (if applicable). > > I need this for a very rough price comparison with Xilinx > and dont want to wake up sleeping dogs at the distributors. > > (The freetradezone does only give me the approx. price for > the Xilinx part, 100 quantity.) > > Regards, TobiasArticle: 36814
Hi all, When doing things like bit-serial multiplers etc, do vhdl synthesizers/fitters make for an efficient fit, or do you get a mess that should be floor-planned first? Does Quartus have a low-level manual floor-planning/routing editor? Because xilinx fpgas have segmented interconnects, does that make manual routing easier than something without segments? Do any of the tools allow you to write macros to instantiate a pre-routed design of your own? Can they be scaleable in size if the fpga has suitable repetition of structure? Are FFTs suitable for bit-serial implementations?Article: 36815
Why don't you do the evaluation of the 18 bits at pulse start, and the 16 bits at pulse-end in hardware? You can use one BlockRAM to monitor, say 8 bits on one port, and 8 bits on the other port, then evaluate the two port outputs together. I all depends on whether you try to measure a wide or a narrow pulse. I am looking at using 3 Gbps Gigabit serial transceivers to do something similar. Have you looked at the Conexant SerDes devices? I bet that, within about a year, it will be very easy to measure pulse-widths with 100 picosecond resolution. Peter Alfke =======================================Article: 36816
Tom Dillon <tdillon@> wrote: > That is the exact code that Exemplar Leonardo will turn into a > "write_first" block RAM. Hrm, any reason why Synplicity chokes on this? Any way to not get it to choke? When have HDLs ever been easy to use? Ugh. Thanks, VR. >>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<< > On 11/20/01, 3:57:02 AM, VR <thisisntvalid@invaldireturn.co> wrote > regarding Synplicity and BlockRAM?: >> Hey all. >> For a project in VHDL, it was suggested by a colleague of mine for doing >> RAM intensive applications, that it is easier to instantiate a small RAM >> as opposed to creating an array of std_logic_vector. >> I was passed on this code, however when synthesizing for an XCV-800 >> (Virtex I) using Synplicity Synplify Pro 7.0, it for some odd reason uses >> 1024 tri-buffs! (BUFFT). >> The same code works fine in Spectrum (I checked) and I told works with > XSV >> synthesis. Neither use BUFFTs or an inordinate amount. >> I can't get this simple code to even P&R in Foundation (after being >> synthesized by Synplicity), I am told that I cannot have more than 86 >> BUFFTs on a net and that I actually have 4 sets of 256 BUFFTs. >> Any ideas on how to correct? Code is as follows: >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use IEEE.STD_LOGIC_ARITH.ALL; >> use IEEE.STD_LOGIC_UNSIGNED.ALL; >> entity ram is >> port (clk : in std_logic; >> we : in std_logic; >> a : in std_logic_vector(11 downto 0); >> di : in std_logic_vector(3 downto 0); >> do : out std_logic_vector(3 downto 0)); >> end ram; >> architecture syn of ram is >> type ram_type is array (4095 downto 0) of std_logic_vector (3 downto 0); >> signal RAM : ram_type; >> signal read_a : std_logic_vector(11 downto 0); >> begin >> process (clk) >> begin >> if (clk'event and clk = '1') then >> if (we = '1') then >> RAM(conv_integer(a)) <= di; >> end if; >> read_a <= a; >> end if; >> end process; >> do <= RAM(conv_integer(read_a)); >> end syn; >> Thanks! >> VR.Article: 36817
The synthesizers generally do a pretty good job with bit serial
stuff...it usually has very little logic between flip-flops so the
mapping is easy. You can often get away without floorplanning bit
serial, although if you are pushing the clock limits of the FPGA you'll
probably have to do it to eke out the last few tenths of a nanosecond.
Quartus has a floorplanner, but I thought it was close to useless last
time I used it (some time ago). Xilinx's floorplanner is better, but
has its fair share of unwanted "features" to work around too.
Placement in the form of floorplanning gets you most of the way there,
and really is sufficient for most bit serial circuits (these tend not to
congest routing). The tools don't give an easy repeatable, supported
means to do manual routing. The thing is, if the placement is good, and
assuming that you are not overly congesting the routing, the router does
a pretty good job. Placement can be done in the normal design flow
easily, so it is the preferred method for macros.
FFTs can be done bit serially in FPGAs. I did one a number of years ago
for an XC4020 design, and as I recall, it only took a fraction of the
chip for everything except the storage. Reordering in the chip is a
bear if you don't have bit wide addressable memory.
Russell Shaw wrote:
> Hi all,
>
> When doing things like bit-serial multiplers etc, do vhdl
> synthesizers/fitters make for an efficient fit, or do you
> get a mess that should be floor-planned first?
>
> Does Quartus have a low-level manual floor-planning/routing
> editor?
>
> Because xilinx fpgas have segmented interconnects, does that
> make manual routing easier than something without segments?
>
> Do any of the tools allow you to write macros to instantiate
> a pre-routed design of your own? Can they be scaleable in
> size if the fpga has suitable repetition of structure?
>
> Are FFTs suitable for bit-serial implementations?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 36818I don't know how much the HOT2 board with Spartan (XCS40) costs, but assuming that it costs something like $200, I think Insight Electronics Spartan-II Development Kit is a better deal since Spartan-II is a faster and larger device, and the kit with only the card (without the LogiCORE PCI32 license) costs only $145. http://208.129.228.206/solutions/kits/xilinx/spartan-iipci.html I used this kit to develop my own PCI IP core, and although the PCI IP core doesn't meet 33MHz PCI's timings (Tsu < 7ns and Tval < 11ns), the card somehow (barely) worked in two computers I tested it. It would have been nice if the Insight Electronics Spartan-II Development Kit used a 200K system gate part (XC2S200) instead of a 150K system gate part (XC2S150) even if the kit cost another $50 more, but overall I am very happy with the Insight Electronics Spartan-II Development Kit. I am told that the Insight Electronics Spartan-II Development Kit with Xilinx LogiCORE PCI32 license costs $2000. You may want to try out Xilinx LogiCORE PCI32 evaluation program before licensing the IP core. Kevin Brace (don't respond to me directly, respond within the newsgroup) postings@tundratech.com (George) wrote in message news:<915F6F22DGeorgeS@news.jacksonville.net>... > I am looking for a PCI development board to use with the Xilinx PCI32 core > and a Spartan 2 or XL FPGA. I would like to use the Virtual Computer Hot2 > board since the PCI32 core comes with the board and it would allow me to > test the core before I buy it. Unfortunately these boards are out of stock > for awhile. Does anybody have one of these that they would like to sell? > Also, while I am at it, does anybody have good/bad experience with this > board relative to the Insight PCI development board? Thanks in advance > George SteinArticle: 36819
C.Hermine wrote: > > On the LATTICE web site I found ispDesignEXPERT Starter > software but I couldn't download the 4 files (54Mbytes). I suggest contacting the Lattice Webmaster - I've found the Lattice Webfolk helpful in the past. > So I am looking for the sofware for ispLSI 1016 that was > include in the Starter kit describes by ELEKTOR > (french version n° 197 november 1994) : > pDS 1016 (pLSI / ispLSI development system ) > ispCODE Find out the Lattice distributors for your country, and ask them for a starter pack. The current ones will be charged for (although the charge always used to be much less than the combined cost of the hardware included in the kits), but they might have some old versions sitting on the shelf. -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 36820
Gunther May wrote: > > could anybody say me where to find a simple free GAL (especially 16V8) > compiler for MS-DOS? Go to <http://www.ecs.soton.ac.uk/~tmf/pld.htm> and download PLPL along with its documentation. Supports just about all the small PLDs including the full 20 and 24 pin PAL families, 16V8/20V8 (you can chose to target these GALs as a fully-definable macrocell PLD or as emulating the PAL16R8/20R8 ranges), 22V10, 18CV8, 26V10, EP900, etc. PLPL has various quirks (and a couple of bugs), and you need to understand the silicon you're designing for, but it does include the extremely useful CASE construct and a full Quine-McCluskey product term minimiser. PLPL is a DOS application, runs VERY fast on a modern PC, but (because it is native DOS software) it CAN run out of memory when trying to minimise very large CASE statements. -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 36821
There is a university group who have developed an Elliptic-Curve CryptoProcessor. See http://www.vlsi.informatik.tu-darmstadt.de/research/research_index.html for more information. --------------------------------------------------------------------------- Acconovis GmbH Harald Simmler - CEO mailto: simmler@acconovis.com WWW: http://www.acconovis.comArticle: 36822
I just had a related problem which may give you some insight. I tried
to infer a dual port Block RAM in registered output mode. This worked
fine for VirtexII, but didn't work for ordinary Virtex. I'd installed
Synplify 7.0.1. However, my FAE had no apparent problem synthesising
my code, but he had 7.0 installed. Lo and behold, when I changed back
to 7.0, Synplify appeared to instantiate the Block RAM correctly. A
few emails back and forth have implied that, possibly, Synplify 7.0
has some 'issues' when inferring Virtex Block RAM and ver.7.0.1 symply
(ho ho) removed this feature. Maybe these 'issues' are related to the
problem you're seeing? Needless to say, I'm now suspicious of the
results I'm getting for Virtex. Anyway, my FAE has sent this to
Synplicity in a bug report. I'll try to post any further stuff I get.
Cheers, Syms.
Article: 36823In article <9t1vrr$6s4$1@eol.dd.chalmers.se>, e9danneREMOVE_THIS@etek.chalmers.se says... > Hi. > I need info on the various op-codes used in jtag accessing xc95xx cpld: ... Look at the BSDL files for these devices. They are included in the free progamming sw from Xilinx but can probabely be downloaded separately from the support web pages. Best regards -- Klaus Falser Durst Phototechnik AG kfalser@IHATESPAMEdurst.itArticle: 36824
I did a similar thing recently and solved it in this fashion. As has
been said your problem is the code "count_0_delayed <= int_count_3(0)"
because of your falling edge. What I did was to set two processes
going, each implementing a divide by three like your first process.
One was clocked on the rising edge, one on the falling edge. This
gives you two signals, rising_int_count_3(0) and
falling_int_count_3(0). Then use a flip flop (henceforth known as the
'evil' flip flop) to sample falling_int_count_3(0) with the falling
edge of rising_int_count_3(0) as a clock. (Still with it?) If your
flip flop doesn't have a '1' in it, you need to slip one of the
counters, until it does. Then you can stop slipping and 'or' the two
signals to get your divide by three clock.
This is, of course, horrible! You need to RLOC the signals and the
'evil' flip flop. It works(ish) because you equalise the delay on the
two signals to the 'evil' flip flop. You need to believe that the
clock-to-out time is the same for both int_count signals! This saves
you 1.4ns in your timing budget, according to my datasheet, if you
accept that clock-to-out times track each other. Worked for me. Make
sure your clock is 50-50 mark space too!
cheers, Syms
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z