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Messages from 36825

Article: 36825
Subject: XC4000EX Logiblox Clock Distribution
From: John <john.maher@nuigalway.ie>
Date: Wed, 21 Nov 2001 04:09:26 -0800
Links: << >>  << T >>  << A >>
I am seeing a problem where the clock being distributed to a Logiblox RAM within a bigger design, uses a non dedicated clock line. 

The design being targeted is a 4028EX using 2.1i sp6 PAR. Has anyone seen a problem like this? 

Regards John

Article: 36826
Subject: Re: don't cares and X's in a case statement?
From: hamish@cloud.net.au
Date: 21 Nov 2001 12:14:23 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga Theron Hicks <hicksthe@egr.msu.edu> wrote:
> limited by the clock routing capacity of the virtex2.  In theoy, there
> are 16 clock muxes, but in practice you are lucky to use more than 8.

That's not quite true; depending your design, you can use all 16.
The rule is that for any quadrant, you can access either the primary
or secondary buffer in a pair, but not both. I'm using 11 or so in
a design I'm working on at the moment.

I'd like more dedicated clock pins. 16 is good, but that's only 8
clocks when you use them as differential pins. Ideally, there would
always be 16 clock pins, ie 16 differential pairs.



Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 36827
Subject: XC4000EX Logiblox Clock Distribution
From: John <john.maher@nuigalway.ie>
Date: Wed, 21 Nov 2001 04:21:32 -0800
Links: << >>  << T >>  << A >>
I am seeing a problem where the clock being distributed to a Logiblox RAM within a bigger design, uses a non dedicated clock line. 

The design being targeted is a 4028EX using 2.1i sp6 PAR. Has anyone seen a problem like this? 

Regards John

Article: 36828
Subject: Viewing generated VHDL
From: Adrian <g9731642@campus.ru.ac.za>
Date: Wed, 21 Nov 2001 04:23:22 -0800
Links: << >>  << T >>  << A >>
Hi,

I'm using Xilinx Foundation F3.1
I am using schematic design entry, however wish to view generated VHDL for my entire design. How do I do this?

thanks
adrian

Article: 36829
Subject: Re: Foundation ISE 4.1
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Wed, 21 Nov 2001 08:15:43 -0700
Links: << >>  << T >>  << A >>
Hello Eric,

FPGA Express 3.6, which comes with ISE 4.1i can be installed on
a machine that already has another version of Express on it.  Unlike
previous versions, Synopsys has given Xilinx their own registry entry
for FPGA Express 3.6.  Therefore, you should have no problem with
the Viewlogic Express and Foundation Express conflicting.

As to your other question, this version of FPGA Express is restricted to
Xilinx devices.  I hope this helps.

Regards,
Kamal

Erik Lins wrote:

> Hello,
> Foundation ISE4.1 comes with FPGA Express, when I'm right. Is this FPGA
> Express restricted to Xilinx devices? Or can one use it for Altera,
> provided the libraries are available? I have installed an older version
> of Viewlogic with FPGA Express used for Altera's and now I'm wandering
> what happens if I install Foundation beside it. What happens to
> enviroment variables, which libraries will be found by which program.
> Best would be to use only the new version of FPGA Express and tell it to
> use both Xilinx and Altera libs. Is that possible?
>
> Cheers,
> ER!K
>
> -- Dr. Erik Lins, Projektleiter
> HighTronix GmbH, 35578 Wetzlar
> Telefon 06441-952010, Telefax -952012
> e.lins@hightronix.de, www.hightronix.de


Article: 36830
Subject: Re: jtag programming xilinx cpld
From: Alan Nishioka <alann@accom.com>
Date: Wed, 21 Nov 2001 08:20:28 -0800
Links: << >>  << T >>  << A >>
You can also generate an SVF file using the jtag programmer.  This will 
give you the opcodes and an example of how they are used.

Alan Nishioka
alann@accom.com


Daniel Nilsson wrote:

>Hi.
>I need info on the various op-codes used in jtag accessing xc95xx cpld:s to
>test my homedeveloped jtag access software, the opcodes I am particularly
>interrested in are:
>
>idcode
>bypass
>extest
>highz
>sample/preload
>
>I am also interrested in the lengths of the opcodes (how many bits)
>
>/Daniel Nilsson, M.Sc.EE student
>


Article: 36831
Subject: Re: don't cares and X's in a case statement?
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 21 Nov 2001 11:56:00 -0500
Links: << >>  << T >>  << A >>
Theron Hicks wrote:
> 
> Hi,
>     I am designing a system where I have multiple (16) clocks coming
> from 4 DCM's in a Virtex2.  These clocks are staggered by an equal phase
> delay such that the clocks are phase delayed by 360/16 degrees from each
> other.  I am then latching these into a sixteen bit latch.  I need to
> know when in the cycle the latch pulse occurs.  To determine this I am
> looking for a series of '1's followed by a zero in the 16 bit data
> word.  In the simulation I may get an X (unknown) in the edge between
> the 1's and 0's.  For example, "1111 X000 0000 X111" or "00X1 1111 11X0
> 0000".  As a result I am looking for at least 6 '1's in a row.  I have
> written code using if-then-else that is similar in function to a
> priority encoder.  The simulation returns an unknown due to the
> potential X values in the data word.  Is there a way to override these
> to appear as either all '0's or all '1's?
> 
> Here is the if-then-else structure.  Obviously I would rather use a case
> statement.  Can any one show me a simple way to do so without hand
> encoding every value?
> Can anyone tell me a way to get the system to ignore the X's or
> something similar so that I can get my simulation to work?  The one
> sample uncertainty cased by the X is not a worry.  No results is a pain
> in the ___.
> 
> process(phase_temp, count)
> begin
>  if falling_edge(count) then
>   phase(15 downto 0)<=phase_temp(15 downto 0);
>  end if;
> end process;

snip... 
 
> By the way, the purpose of this code is give me a very precise
> measurement of a pulse width.  The main clock is 200MHz, thus, in
> theory, the resolution is equivalent to using a 3.2GHz clock.  I tried
> to use multiple counters and sum the resultant count values, but I was
> limited by the clock routing capacity of the virtex2.  In theoy, there
> are 16 clock muxes, but in practice you are lucky to use more than 8.
> This greatly limits the required number of clock channels, as the 16
> phases are not really clock channels.  They do require low skew routing,
> however.
> 
> Thanks,
> Theron Hicks

If I can offer my two cents worth. I would not expect this to work very
well. Your accuracy in measurement will be limited by the skew in
routing the 16 phase shifted clocks to the register inputs. Since they
will not (all) be on the clock routing nets, you can expect significant
skew in the routes. 

How do you expect to adequately control the routing skew?

BTW, I think you are getting X's in your simulation because you are
simulating post routing. You can do a functional simulation before
routing which should not introduce an X's from metastability since there
is no delay data available. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 36832
Subject: Re: ISA interface
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 21 Nov 2001 11:59:30 -0500
Links: << >>  << T >>  << A >>
Jason Berringer wrote:
> 
> Hello all,
> 
> I'm new to the newsgroup and am curious if anyone has VHDL code for a 16 bit
> full ISA interface. Everything seems to PCI from what I can see, and I don't
> require that level of complexity. If you could help me out or point me to a
> source I would be most appreciative.
> 
> Thanks

The ISA bus is very simple and only requires the decode of an address
along with the qualifying timing strobe to enable the data transfer. So
it is not normally provided as IP. It would take longer to learn how to
use the IP than to write your own. 

Just pick up a book on the ISA bus and read a little. You will see what
I mean. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 36833
Subject: Re: Elliptic Curves
From: klonsky@hotmail.com (Noel Klonsky)
Date: 21 Nov 2001 10:51:50 -0800
Links: << >>  << T >>  << A >>
Try a guy called Liam Marnane at the University College Cork, EEE Dept.
www.ucc.ie

Noel



"fede" <fedeg@terra.es> wrote in message news:<9sr4p0$idl$1@news.ua.es>...
> Hi
> 
> Are there anybody who implemented elliptic curves cryptographic algorithms
> in some fpga?
> thanks

Article: 36834
Subject: Re: Synplicity and BlockRAM?
From: VR <nospam@vrvrvrvrvrvrv.com>
Date: Wed, 21 Nov 2001 18:52:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
Symon <symon_brewer@hotmail> wrote:

> I just had a related problem which may give you some insight. I tried
> to infer a dual port Block RAM in registered output mode. This worked
> fine for VirtexII, but didn't work for ordinary Virtex. I'd installed
> Synplify 7.0.1. However, my FAE had no apparent problem synthesising
> my code, but he had 7.0 installed. Lo and behold, when I changed back

I had 7.0 and it didn't go. I tried 7.02 and it still didn't go, it still
created a lot of tri-buffs.

Spectrum had no problems, and FPGA Xpres 3.51 just got stuck in the
"linking design" stage.

VR.

Article: 36835
Subject: slew rate of virtex output buffers figures
From: "jfh" <jfhasson@club-internet.fr>
Date: Wed, 21 Nov 2001 19:55:59 +0100
Links: << >>  << T >>  << A >>
Hi,

I work with both virtex and virtex E and I am about to place and route my
board but I wish I had the figures of the slew rate of the output buffers of
a Virtex and virtex E in LVTTL for the different current grades and with the
slow or fast slew rate option. Does anyone have that type of information
because I could not find it ?
Thank you.

J.F. Hasson




Article: 36836
Subject: Re: slew rate of virtex output buffers figures
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 21 Nov 2001 12:15:32 -0800
Links: << >>  << T >>  << A >>
JF,

That is what the IBIS models are good for.

If you do not have an IBIS simulator, it is like trying to build a house without
a hammer.

Austin

jfh wrote:

> Hi,
>
> I work with both virtex and virtex E and I am about to place and route my
> board but I wish I had the figures of the slew rate of the output buffers of
> a Virtex and virtex E in LVTTL for the different current grades and with the
> slow or fast slew rate option. Does anyone have that type of information
> because I could not find it ?
> Thank you.
>
> J.F. Hasson


Article: 36837
Subject: Re: slew rate of virtex output buffers figures
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 21 Nov 2001 21:59:14 +0100
Links: << >>  << T >>  << A >>
Austin Lesea <austin.lesea@xilinx.com> writes:

> JF,
> 

> That is what the IBIS models are good for.
> 
> If you do not have an IBIS simulator, it is like trying to build a house without
> a hammer.
> 

More like trying to build a house without the blueprint. It can be
done if you are experienced, know a few rules of thumb, and not too
concerned about the quality of the result.

Or whatever. ;-)

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 36838
Subject: Re: Viewing generated VHDL
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 21 Nov 2001 21:16:20 GMT
Links: << >>  << T >>  << A >>
Adrian wrote:
> 
> Hi,
> 
> I'm using Xilinx Foundation F3.1
> I am using schematic design entry, however wish to view generated VHDL for my entire design. How do I do this?

Is the VHDL already generated?  If so, most any text editor will work.

-a

Article: 36839
Subject: Re: Prototyping Board
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 21 Nov 2001 21:25:11 GMT
Links: << >>  << T >>  << A >>
John Jakson wrote:

> Datacube looks like an interesting solution to video, never heard of
> them before. 

They do programmable video-processor boards.

They are frighteningly expensive.

-a

Article: 36840
Subject: Re: slew rate of virtex output buffers figures
From: "Speedy Zero Two" <david@manorsway.freeserve.co.uk>
Date: Wed, 21 Nov 2001 21:29:39 -0000
Links: << >>  << T >>  << A >>
That's a poor response from Xilinx,
I always thought customer support was one of their good points.......


Dave



"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3BFC0B64.AB4353C4@xilinx.com...
> JF,
>
> That is what the IBIS models are good for.
>
> If you do not have an IBIS simulator, it is like trying to build a house
without
> a hammer.
>
> Austin
>
> jfh wrote:
>
> > Hi,
> >
> > I work with both virtex and virtex E and I am about to place and route
my
> > board but I wish I had the figures of the slew rate of the output
buffers of
> > a Virtex and virtex E in LVTTL for the different current grades and with
the
> > slow or fast slew rate option. Does anyone have that type of information
> > because I could not find it ?
> > Thank you.
> >
> > J.F. Hasson
>



Article: 36841
Subject: Re: Low cost Spartan2 FPGA board
From: "kryten_droid" <kryten_droid@ntlworld.com>
Date: Wed, 21 Nov 2001 21:30:28 -0000
Links: << >>  << T >>  << A >>

> Introductory price:  US$149,  available now
> http://www.burched.com.au/bedspartan2.html
>
And some technical revue here:
http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm




Article: 36842
Subject: read only version register usinga generic
From: "Dave Brown" <dbrown@novatel.ca>
Date: Wed, 21 Nov 2001 16:20:28 -0700
Links: << >>  << T >>  << A >>
Hi everyone,
    I have a SpartanXL XCS-05 design that is a memory mapped device. One of
the memory addresses is supposed to be an 8 bit version register that
reflects the version of VHDL code that was used to synthesize the design. I
implemented this as generic integer in my top level module that gets passed
down to the address decoder. This way, I can just change the generic in the
top level. When the version address shows up on the address bus, I return
this generic using conv_unsigned(version, 8). This has worked fine. Until
today, when I got to version 54. Now my design won't fit onto the chip. I
was at about 95% of 4-LUTs used up with version 53. With 54 as the version,
I get 103% of 4 input LUT's used. I thought maybe this was because of the
changes, so I went back to the code for version 53 and just changed the
generic to 54. Presto, it doesn't fit into the design. I'm stumped. What's
special about 54 vs 53? Nothing in my mind. Every number up to 54 worked
fine. Hmm, any ideas?
Thanks,
Dave




Article: 36843
Subject: Re: slew rate of virtex output buffers figures
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 21 Nov 2001 15:45:32 -0800
Links: << >>  << T >>  << A >>
And what about my answer was poor?

That we strongly recommend that you get the right tools to do the job?


Tell you what, open up our web page, and do a search on signal integrity.

Do the same for any other LOGIC supplier.

Hands down, we win  More content.  More real useful stuff.  More articles,
answers, tech topics, Xclusives, etc etc etc.

If I give you a fish, I have fed you.  If I teach you how to fish, you feed
yourself.

Austin



Speedy Zero Two wrote:

> That's a poor response from Xilinx,
> I always thought customer support was one of their good points.......
>
> Dave
>
> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3BFC0B64.AB4353C4@xilinx.com...
> > JF,
> >
> > That is what the IBIS models are good for.
> >
> > If you do not have an IBIS simulator, it is like trying to build a house
> without
> > a hammer.
> >
> > Austin
> >
> > jfh wrote:
> >
> > > Hi,
> > >
> > > I work with both virtex and virtex E and I am about to place and route
> my
> > > board but I wish I had the figures of the slew rate of the output
> buffers of
> > > a Virtex and virtex E in LVTTL for the different current grades and with
> the
> > > slow or fast slew rate option. Does anyone have that type of information
> > > because I could not find it ?
> > > Thank you.
> > >
> > > J.F. Hasson
> >


Article: 36844
Subject: Re: Decoupling capacitors on Virtex II
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 22 Nov 2001 00:35:22 +0000
Links: << >>  << T >>  << A >>


rickman wrote:

> Ian,
>
> You are a man after my own heart. You seem to actually understand what
> is going on rather than just having learned a few "rules of thumb". So
> many people who design power distibution never actually read the
> capacitor data sheets and have no true understanding of how they work at
> high frequencies.
>
> I agree 100% with everything you said, expecially the part about using a
> single large value, low ESR device on the board. I have read several
> people here say that you need multiple tantalums per chip which is
> nonsense. The only reason (that I know) of placing caps near the load is
> to minimize the effects of inductance in the power distibution. But
> since the large, bulk caps have very high inductance relative to the
> power distribution, there is no need to keep them close to the load. So
> you can use one large device anywhere on the board.
>
> Another point that often escapes designers is that it does not matter if
> your noise frequecies are above the self resonant point of the cap. At
> those frequencies the cap is actually an inductor. But as long as the
> impedance is low, it still acts to decouple the noise. So for high
> freqs, the only relevant factor is the total impedance to ground. By
> keeping this impedance low at the frequencies of the noise, you will get
> good decoupling and a quiet power plane. So lots of MLCC caps are good
> and more are better. As you say, the value is not so important, moreso
> the physical size. Ceramic 100 nF, 0603 caps work great and don't
> clutter up the board with bulk.
>
>

If the the rule that high speed decouplers should be placed as close as
possible to the chip's power pins [I've heard ~1cm]  isn't just more voodoo
then its rationale must be inductance again ?

One other query I've got is that it seems that what's called decoupling
really covers 2 things:

o Stopping high frequency noise generated externally from getting into the
chip via the power pins.

o Dealing with self-injected noise from the chip driving very fast edges
into capacitive loads.

In the second case, with edges in the 1-2 nsec range or faster it would
appear to me that the frequencies we are dealing with have 500MHz+
components. In other words even 0402 caps will appear inductive ?




Article: 36845
Subject: Re: slew rate of virtex output buffers figures
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 22 Nov 2001 00:57:31 +0000
Links: << >>  << T >>  << A >>


Austin Lesea wrote:

> And what about my answer was poor?
>
> That we strongly recommend that you get the right tools to do the job?
>
> Tell you what, open up our web page, and do a search on signal integrity.
>
> Do the same for any other LOGIC supplier.
>
> Hands down, we win  More content.  More real useful stuff.  More articles,
> answers, tech topics, Xclusives, etc etc etc.
>
> If I give you a fish, I have fed you.  If I teach you how to fish, you feed
> yourself.
>
> Austin
>

The site is great with one exception:

The WebPACK download section. It used to be o.k. but its become an overcomplicated
mess that seems to have suffered from a s/w engineer doing some resume padding
with tons of slow & broken JavaScript [I hate sites that require me to enable
Javascript. One of our guys here considers it to be a security hole and I
sometimes forget to disable it after visiting a JS-required site].

This is important to us since our field upgrade instructions begin:

``Go & get the free WebPACK JTAG programmer from the Xilinx site'', then get hold
of a standard Centronics extension cable, ...

Finally: If fish = IBIS simulator I'll just take the fish, with thanks.



Article: 36846
Subject: Re: read only version register usinga generic
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Thu, 22 Nov 2001 01:04:58 GMT
Links: << >>  << T >>  << A >>
Fortunately I am an expert on numerology.  53 is prime, and has a good aura,
whereas 54 is not prime and has both 2's and 3's in its prime factorization,
which gives it bad karma.

"Dave Brown" <dbrown@novatel.ca> wrote in message
news:9thcq5$34m$1@pallas.novatel.ca...
> Hi everyone,
>     I have a SpartanXL XCS-05 design that is a memory mapped device. One
of
> the memory addresses is supposed to be an 8 bit version register that
> reflects the version of VHDL code that was used to synthesize the design.
I
> implemented this as generic integer in my top level module that gets
passed
> down to the address decoder. This way, I can just change the generic in
the
> top level. When the version address shows up on the address bus, I return
> this generic using conv_unsigned(version, 8). This has worked fine. Until
> today, when I got to version 54. Now my design won't fit onto the chip. I
> was at about 95% of 4-LUTs used up with version 53. With 54 as the
version,
> I get 103% of 4 input LUT's used. I thought maybe this was because of the
> changes, so I went back to the code for version 53 and just changed the
> generic to 54. Presto, it doesn't fit into the design. I'm stumped. What's
> special about 54 vs 53? Nothing in my mind. Every number up to 54 worked
> fine. Hmm, any ideas?
> Thanks,
> Dave
>
>
>



Article: 36847
Subject: Re: Decoupling capacitors on Virtex II
From: William L Hunter Jr <wlhunterjr@home.com>
Date: Thu, 22 Nov 2001 01:58:46 GMT
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> Some other common mistakes are running traces to the caps (makes them useless),
> having a single via from the plane to the end of the pad (not as good as two vias,
> or via in pad), and locating the caps too far from the chip, and having a good
> bypass solution for the fpga, and forgetting all of the other really new high
> speed chips on the board that no one told you also need even better bypass
> solutions.

Austin please elaborate on the common mistakes!!

Not knowing any better I have always heard the following   What is the recommended way
to connect decoupling caps???

"To provide proper decoupling, connection
should be made from the device Vcc or GND pin to the decoupling cap, then from the cap
to
the Vcc or GND plane. and placing SMT caps on the opposite side of the
board from the SMT devices, two vias are required per connection,
one to get from the SMT device to the cap and another to get from
the cap to the plane. A better solution is to move the caps to the
top side of the board where possible."

Thanks
Bill


Article: 36848
Subject: too large a 32 entry 3 read 2 write register file
From: shengyu_shen@hotmail.com (ssy)
Date: 21 Nov 2001 18:27:43 -0800
Links: << >>  << T >>  << A >>
in my  design, I have a 32 entry 3 read and 2 write register file,
each entry hold 32 bits.

so each read port have 31 mux to select out the desire register,3 read
port nead nearly 100 mux, each mux is 32 bit width, so total 3000 mux
needed|||, it is a large number for my APEX20K400E,

so I want to use tristate signal output for every entry,and tie them
together to replace the large mux tree,but if it is a problem 32
tristate signal drive a port?

or any other suggestion to deal with this too large register file?

Article: 36849
Subject: PCMCIA interface and CPLD
From: c_oflynn@yahoo.com (Colin O'Flynn)
Date: 21 Nov 2001 19:03:15 -0800
Links: << >>  << T >>  << A >>
Hi,

   I'm fairly new to CPLD, but have been a micro user for a long time.
I'm interested in trying a PCMCIA interface. Anyone know of some good
sites or books on it? I checked online, and there are a few books, but
none get good reviews. I figure i'll use a Ziolog chip as the master
interface, and then the CPLD to do some other data proccessing. I'm
basically looking for info on the hardware AND software. I've seen the
development kits, but they are way to much for right now ($300 US).

  Thanks so much,

        -Colin



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