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Messages from 36850

Article: 36850
Subject: Re: slew rate of virtex output buffers figures
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 22 Nov 2001 03:28:32 GMT
Links: << >>  << T >>  << A >>

--------------4F507A82799B5ECEC7954F21
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

Let me make a constructive suggestion:

We will publish a step-by-step cookbook how you can use the free version of
HypeLynx to analyze output behavior with astounding accuracy and surprising ease.

Here are just a few success stories, documenetd by Innoveda, the owners of
HyperLynx.

http://www.innoveda.com/products/datasheets_HTML/hyperlynx_success.asp

Over the past years, progress in FPGAs has vastly simplified the logic design.
Bigger chips, better technology, more advanced architectures, abundant routing,
lots of cores, and more user-friendly software all have made your life so much
more productive ( to avoid the dangerous word "easier").
But the electrical and the high-frequency analog aspects on the pc-board have
gotten much more complex, and they affect every user, even the few remaining
10-MHz-clock-driven designs. These problems are not caused by the clock
frequency, but only by the edge rates, the UHF components in the pc-board
signals.
And no VHDL or Verilog can help you there.
That's what Austin meant when he mentioned the need to learn how to fish.
Signal integrity is no longer a subject only for the speed-demons, it affects
every design.
We all have got lo learn this "new" discipline, whether we want to or not.
And the available tools actually make it fun, once you master them.

Peter Alfke
=================================================
Austin Lesea wrote:

> And what about my answer was poor?
>
> That we strongly recommend that you get the right tools to do the job?
>
> Tell you what, open up our web page, and do a search on signal integrity.
>
> Do the same for any other LOGIC supplier.
>
> Hands down, we win  More content.  More real useful stuff.  More articles,
> answers, tech topics, Xclusives, etc etc etc.
>
> If I give you a fish, I have fed you.  If I teach you how to fish, you feed
> yourself.
>
> Austin
>
> Speedy Zero Two wrote:
>
> > That's a poor response from Xilinx,
> > I always thought customer support was one of their good points.......
> >
> > Dave
> >
> > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> > news:3BFC0B64.AB4353C4@xilinx.com...
> > > JF,
> > >
> > > That is what the IBIS models are good for.
> > >
> > > If you do not have an IBIS simulator, it is like trying to build a house
> > without
> > > a hammer.
> > >
> > > Austin
> > >
> > > jfh wrote:
> > >
> > > > Hi,
> > > >
> > > > I work with both virtex and virtex E and I am about to place and route
> > my
> > > > board but I wish I had the figures of the slew rate of the output
> > buffers of
> > > > a Virtex and virtex E in LVTTL for the different current grades and with
> > the
> > > > slow or fast slew rate option. Does anyone have that type of information
> > > > because I could not find it ?
> > > > Thank you.
> > > >
> > > > J.F. Hasson
> > >

--------------4F507A82799B5ECEC7954F21
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Let me make a constructive suggestion:
<p>We will publish a step-by-step cookbook how you can use the free version
of HypeLynx to analyze output behavior with astounding accuracy and surprising
ease.
<br>Here are just a few success stories, documenetd by Innoveda, the owners
of HyperLynx.
<p><u><A HREF="http://www.innoveda.com/products/datasheets_HTML/hyperlynx_success.asp">http://www.innoveda.com/products/datasheets_HTML/hyperlynx_success.asp</A></u><u></u>
<p>Over the past years, progress in FPGAs has vastly simplified the logic
design. Bigger chips, better technology, more advanced architectures, abundant
routing, lots of cores, and more user-friendly software all have made your
life so much more productive ( to avoid the dangerous word "easier").
<br>But the electrical and the high-frequency analog aspects on the pc-board
have gotten much more complex, and they affect every user, even the few
remaining 10-MHz-clock-driven designs. These problems are not caused by
the clock frequency, but only by the edge rates, the UHF components in
the pc-board signals.
<br>And no VHDL or Verilog can help you there.
<br>That's what Austin meant when he mentioned the need to learn how to
fish.
<br>Signal integrity is no longer a subject only for the speed-demons,
it affects every design.
<br>We all have got lo learn this "new" discipline, whether we want to
or not.
<br>And the available tools actually make it fun, once you master them.
<p>Peter Alfke
<br>=================================================
<br>Austin Lesea wrote:
<blockquote TYPE=CITE>And what about my answer was poor?
<p>That we strongly recommend that you get the right tools to do the job?
<p>Tell you what, open up our web page, and do a search on signal integrity.
<p>Do the same for any other LOGIC supplier.
<p>Hands down, we win&nbsp; More content.&nbsp; More real useful stuff.&nbsp;
More articles,
<br>answers, tech topics, Xclusives, etc etc etc.
<p>If I give you a fish, I have fed you.&nbsp; If I teach you how to fish,
you feed
<br>yourself.
<p>Austin
<p>Speedy Zero Two wrote:
<p>> That's a poor response from Xilinx,
<br>> I always thought customer support was one of their good points.......
<br>>
<br>> Dave
<br>>
<br>> "Austin Lesea" &lt;austin.lesea@xilinx.com> wrote in message
<br>> <a href="news:3BFC0B64.AB4353C4@xilinx.com">news:3BFC0B64.AB4353C4@xilinx.com</a>...
<br>> > JF,
<br>> >
<br>> > That is what the IBIS models are good for.
<br>> >
<br>> > If you do not have an IBIS simulator, it is like trying to build
a house
<br>> without
<br>> > a hammer.
<br>> >
<br>> > Austin
<br>> >
<br>> > jfh wrote:
<br>> >
<br>> > > Hi,
<br>> > >
<br>> > > I work with both virtex and virtex E and I am about to place
and route
<br>> my
<br>> > > board but I wish I had the figures of the slew rate of the output
<br>> buffers of
<br>> > > a Virtex and virtex E in LVTTL for the different current grades
and with
<br>> the
<br>> > > slow or fast slew rate option. Does anyone have that type of
information
<br>> > > because I could not find it ?
<br>> > > Thank you.
<br>> > >
<br>> > > J.F. Hasson
<br>> ></blockquote>
</html>

--------------4F507A82799B5ECEC7954F21--


Article: 36851
(removed)


Article: 36852
Subject: Re: Decoupling capacitors on Virtex II
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 21 Nov 2001 23:21:24 -0500
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> 
> If the the rule that high speed decouplers should be placed as close as
> possible to the chip's power pins [I've heard ~1cm]  isn't just more voodoo
> then its rationale must be inductance again ?

I am not clear what you are saying here. I was not saying that it is
good to be inductive. I am saying that it does not matter if the cap is
inductive, as long as the total impedance (including any trace
impedance) is low. The impedance finds a sharp minimum at the self
resonant frequency and then starts increasing again as frequency
increases. Above this self resonant frequency the cap is net inductive.
But the cap is still an effective decoupling component until the
impedance rises enough to interfere with its operation. This can easily
be 10X the freq of self inductance. 

 
> One other query I've got is that it seems that what's called decoupling
> really covers 2 things:
> 
> o Stopping high frequency noise generated externally from getting into the
> chip via the power pins.
> 
> o Dealing with self-injected noise from the chip driving very fast edges
> into capacitive loads.
> 
> In the second case, with edges in the 1-2 nsec range or faster it would
> appear to me that the frequencies we are dealing with have 500MHz+
> components. In other words even 0402 caps will appear inductive ?

When you say "driving very fast edges into capacitive loads" I assume
you are talking about the current spike required from the power bus to
change the voltage on an output. Yes this has very fast frequency
components. But the impedance of a cap is still effective in reducing
the amplitude of the voltage spike on the power bus even when the cap is
above the self resonant freq. The AVX chart shows an 0805 MLCC cap as
having about 3 or 4 ohms impedance at 500 Mhz. With some 20 mA switching
on that power pin, you will see less than 0.1 volt of noise. The fact
that it is inductive reactance does not matter!

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 36853
Subject: The Xilinx Practical Designer Lab Book
From: djley@msn.com (Douglas)
Date: 21 Nov 2001 21:40:23 -0800
Links: << >>  << T >>  << A >>
I'm using Xilinx Foundation Student Edition Ver.2.1i and "The Xilinx
Practical Designer Lab Book 1.5". The exercise is a 4x4 Asynchronous
Memory, the source code in the book and also the source code on the CD
return the error messages below.
These error messages occur when I check for syntax errors. Since, I am
not a student I'm assuming that form my past experience I can not ask
for help on "The Xilinx University" ( MSU ) student website.





Error: C:/xcproj-v/mem1_40/mem1.vhd  line -3   Library logical name
XSE is not mapped to a host directory. (VSS-1071) 
(FPGA-dm-hdlc-unknown)
 Error   L5/C0 : #0 Error: C:/xcproj-v/mem1_40/mem1.vhd  line 5   No
selected element named LED is defined for this prefix.  (VSS-573)
 Error   L21/C0 : #0 Error: C:/xcproj-v/mem1_40/mem1.vhd  line 21  
The intermediate file for entity MEM1 is not in the library bound to
WORK.  (VSS-1084)
 3 error(s) 0 warning(s) found


Line and Text:

3 LIBRARY IEEE,xse;

5 Use xse.led.ALL;

21 ARCHITECTURE  mem1_arch OF mem1 IS

Article: 36854
Subject: Re: Viewing generated VHDL
From: Adrian <g9731642@campus.ru.ac.za>
Date: Wed, 21 Nov 2001 23:24:59 -0800
Links: << >>  << T >>  << A >>
Don't know if is generated. I'm trying to see if Foundation automatically generates VHDL for schematic designs I have made, and if so where can I find these files!

adrian

Article: 36855
Subject: Creating a jitter free clock
From: Adrian <g9731642@campus.ru.ac.za>
Date: Wed, 21 Nov 2001 23:36:54 -0800
Links: << >>  << T >>  << A >>
Hi,

I'm using a programmable clock which has an accuracy of 1 part per million. i.e. I can set f = 1.000000 MHz. However, I need a clock with a resolution of 1 part per billion ie. f can be set to 1.000000000 MHz and does not vary over a period of at least 5 minutes.

Is there anything I can add to my FPGA design to achieve this? Clock will be running at approximately 32MHz.

thanks
adrian

Article: 36856
Subject: how can define function in terms of equation rather than gates in XC4000 series
From: skoc@gantep.edu.tr (skoc)
Date: 22 Nov 2001 01:24:44 -0800
Links: << >>  << T >>  << A >>
I'm a Phd student and I'm working on Xilinx XC4000 project. I've used
schematic editor of ORCAD.I want to learn that is XC4000 series allows
functionality to specified in terms of equationrather than gates, like
CLB primitive in XC3000 series. if it is possible how can I do. I
haven't successed this using FMAP. Is possible help me about this
problem? thanks.
Regards,
sema KOÇ

Article: 36857
Subject: fix LOC on LUT1
From: khtsoi@cse.cuhk.edu.hk
Date: 22 Nov 2001 09:37:36 GMT
Links: << >>  << T >>  << A >>
Hi,

I must fix a NOT gate to a cretain location and the
gate is in form of LUT1 in Xilinx XCV1000E. I can
use the RLOC/LOC to give a location like R12C3.S0
under Synopsys DC. But I want to give more constrain
to the location (i.e. in F-function or G-function LUT
inside a slide). What can I do? Thanks in advance!

---- Brittle

Article: 36858
Subject: Re: Decoupling capacitors on Virtex II
From: "Philippe Robert" <PhilippeR@sundance.com>
Date: Thu, 22 Nov 2001 09:38:02 -0000
Links: << >>  << T >>  << A >>
Hi,

I am more like in the VHDL engineer...and let me tell you that you guys give
me hard work to follow all that you say !!!
But it is very interesting. I have ordered the book that HW Johnson wrote. I
think I will need to spend a bit of time reading it.

    > Hmm, try redestributiing the capacitance into less caps, but dont
forget to
    > use small ones (10nF or lower) for the "really" high frequencys. In
    > microwave engineering they use sometimes even 100pF instead of 1nF
because
    > of the lower inductance.
    > And dont forget a good ground-VCC planes. In your layer stacking, the
    > GND-VCC planes should be close together, forming a superb high
frequncy
    > capacitor.

Is it a question of impedance between the two planes ?


Thanks again to all of you for your help.
Philippe.




Article: 36859
Subject: how to imply tristate buffer in APEX20K
From: shengyu_shen@hotmail.com (ssy)
Date: 22 Nov 2001 02:42:03 -0800
Links: << >>  << T >>  << A >>
Hi

I am using APEX20K, and I know that there is no build in tristate
buffer in PAEX, but xilinx device have build in tri state buffer, so a
tri state buffer in APEX will occupy a LE, right?

I have a register file with 32 entry, and 3 read port, so if I use 3
mux tree to select desire register, then this register file will
consume about 4000 LE, so  want to use tri state signal to replace mux
tree, but after that, the register file's size do not change too much,

how to deal with this?

Article: 36860
Subject: How do I.......
From: "Harjo Otten" <h.otten@rohill.geen.spam.nl>
Date: Thu, 22 Nov 2001 12:29:03 +0100
Links: << >>  << T >>  << A >>
Hi,

Can anybody help me with this:

I've got a process with 2 inout busses  (8 bits wide) named PDi and PDo.
When my "Normal_IO" signal is deasserted I want to put some data from
another prcoess on the PDo bus, and do nothing with the PDi bus. But (and
this is my problem) when "Normal_IO" is asserted I want to simply tie PDi
and PDo together, so it's 'transparent' both ways. Is this possible ?? And
what should the VHDL code for such a construction look like ??

Thanx,

H.




Article: 36861
Subject: Synplicity & BlockRAMs
From: Maire <maire.mcloone@ee.qub.ac.uk>
Date: Thu, 22 Nov 2001 11:56:40 +0000
Links: << >>  << T >>  << A >>
I am currently using Synplify Pro v7.0. I am designing in VHDL and the 
target device is Xilinx - Virtex. The design utilises the Block RAM 
available on the Virtex. With the aid of the VHDL generate statement the 
BRAMs are multiply instantiated. However, when the design is synthesised 
the BRAMs are renamed with numbers appended to the end????  This is also 
the case when I use Synplify version back to v6.1.3.

Does anyone know any way to prevent this as it causes problems in Xilinx 
Design Manager?


Article: 36862
Subject: Re: How do I.......
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Thu, 22 Nov 2001 12:05:25 +0000
Links: << >>  << T >>  << A >>
In article <ninit9.nl2.ln@svr004.rohill.nl>, Harjo Otten
<h.otten@rohill.geen.spam.nl> writes
>Hi,
>
>Can anybody help me with this:
>
>I've got a process with 2 inout busses  (8 bits wide) named PDi and PDo.
>When my "Normal_IO" signal is deasserted I want to put some data from
>another prcoess on the PDo bus, and do nothing with the PDi bus. But (and
>this is my problem) when "Normal_IO" is asserted I want to simply tie PDi
>and PDo together, so it's 'transparent' both ways. Is this possible ?? And
>what should the VHDL code for such a construction look like ??

See the recent thread "How to write a 'relay'" in comp.lang.vhdl
for lots of information on why this is almost impossible in VHDL.

It's easy in Verilog;  just instantiate a "tran" primitive:

  tranif1( PDi[0], PDo[0], Normal_IO );

and so on, eight times for the eight bits (because Verilog doesn't
have a generate statement, at least until Verilog-2001 is fully
implemented by tool vendors, grrrr!).

No synthesis tool I know of will cope with this, though.
It would need to synthesise to pass transistors.

You can easily implement it in hardware with "QuickSwitch"
components, but not on an FPGA as far as I know.
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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Article: 36863
Subject: Re: Synplicity & BlockRAMs
From: hamish@cloud.net.au
Date: 22 Nov 2001 12:45:45 GMT
Links: << >>  << T >>  << A >>
Maire <maire.mcloone@ee.qub.ac.uk> wrote:
> I am currently using Synplify Pro v7.0. I am designing in VHDL and the 
> target device is Xilinx - Virtex. The design utilises the Block RAM 
> available on the Virtex. With the aid of the VHDL generate statement the 
> BRAMs are multiply instantiated. However, when the design is synthesised 
> the BRAMs are renamed with numbers appended to the end????  This is also 
> the case when I use Synplify version back to v6.1.3.

> Does anyone know any way to prevent this as it causes problems in Xilinx 
> Design Manager?

It's caused by the generics. You will need to put
-- synthesis translate_off/on around the generic map on your
instantiation, and possibly around the generic section on
your component declaration too if relevant.

If you are initializing the contents using a generic, you have
to put that information in an attribute instead.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 36864
Subject: Re: Decoupling capacitors on Virtex II
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 22 Nov 2001 13:39:48 +0000
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes:

> When you say "driving very fast edges into capacitive loads" I assume
> you are talking about the current spike required from the power bus to
> change the voltage on an output. Yes this has very fast frequency
> components. But the impedance of a cap is still effective in reducing
> the amplitude of the voltage spike on the power bus even when the cap is
> above the self resonant freq. The AVX chart shows an 0805 MLCC cap as
> having about 3 or 4 ohms impedance at 500 Mhz. With some 20 mA switching
> on that power pin, you will see less than 0.1 volt of noise. The fact
> that it is inductive reactance does not matter!
> 

Just be careful that the way you mount the capacitors doesn't add too
muc more inductance to the capacitor's inherent inductance.  Vias on
the end of traces from the cap pads can be 4nH.  My last design I had
caps mounted on a large plane pad with several (3-4) vias through each
end.  This should add 1nH ish.

Then you are relying on the planes having a low spreading inductance
to deliver the power to the chip, which must also be mounted on
*really* short traces.

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 36865
Subject: Wanted - source for discontinued Coolrunner parts
From: Dave Watkins <david.c.watkins@baesystems.com>
Date: Thu, 22 Nov 2001 14:00:33 +0000
Links: << >>  << T >>  << A >>
Hi,

We are currently preparing an urgent bid for a customer in which our
product incorporates one of the discontinued Phillips/Xilinx 5V
coolrunner parts (XCR5128C-10TQ128I) - a package type for which we know
of no direct equivalent.

Unfortunately we have managed to pick a time when the whole of the US is
shut down and cannot contact Xilinx directly - so I wondered whether
anyone here  has any idea whether there is any possibility that Xilinx
may have uncommitted stock for approximately 500 to 1000 parts?
Alternatively, does anyone know of any specialist supplier that is
likely to carry stock of this obsolete part?

Thanks in advance,

Dave Watkins

BAE SYSTEMS
Rochester
England




Article: 36866
Subject: Re: read only version register usinga generic
From: "Dave Brown" <dbrown@novatel.ca>
Date: Thu, 22 Nov 2001 09:22:57 -0700
Links: << >>  << T >>  << A >>
Nice try. 52 isn't prime and it worked. So did 48, and it has 2 and 3 in
it's prime factorization.
Thanks for the chuckle though,
D.
"Kevin Neilson" <kevin_neilson@removethis-yahoo.com> wrote in message
news:_aYK7.158834$IR4.55129103@news1.denver1.co.home.com...
> Fortunately I am an expert on numerology.  53 is prime, and has a good
aura,
> whereas 54 is not prime and has both 2's and 3's in its prime
factorization,
> which gives it bad karma.
>
> "Dave Brown" <dbrown@novatel.ca> wrote in message
> news:9thcq5$34m$1@pallas.novatel.ca...
> > Hi everyone,
> >     I have a SpartanXL XCS-05 design that is a memory mapped device. One
> of
> > the memory addresses is supposed to be an 8 bit version register that
> > reflects the version of VHDL code that was used to synthesize the
design.
> I
> > implemented this as generic integer in my top level module that gets
> passed
> > down to the address decoder. This way, I can just change the generic in
> the
> > top level. When the version address shows up on the address bus, I
return
> > this generic using conv_unsigned(version, 8). This has worked fine.
Until
> > today, when I got to version 54. Now my design won't fit onto the chip.
I
> > was at about 95% of 4-LUTs used up with version 53. With 54 as the
> version,
> > I get 103% of 4 input LUT's used. I thought maybe this was because of
the
> > changes, so I went back to the code for version 53 and just changed the
> > generic to 54. Presto, it doesn't fit into the design. I'm stumped.
What's
> > special about 54 vs 53? Nothing in my mind. Every number up to 54 worked
> > fine. Hmm, any ideas?
> > Thanks,
> > Dave
> >
> >
> >
>
>



Article: 36867
Subject: Re: Viewing generated VHDL
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 22 Nov 2001 12:31:37 -0500
Links: << >>  << T >>  << A >>
Adrian wrote:

> Don't know if is generated. I'm trying to see if Foundation automatically generates VHDL for schematic designs I have made, and if so where can I find these files!
>
> adrian

You might try opening your top-level schematic in the schematic editor and then exporting the netlist as VHDL using Options->Export Netlist... and then select VHDL as
the file type.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 36868
Subject: Re: Viewing generated VHDL
From: ramnathgoenka@yahoo.com (Ramnath)
Date: 22 Nov 2001 09:53:58 -0800
Links: << >>  << T >>  << A >>
hi,

   I am also new to this area.

   I think Schematic is in lower level than the vhdl code as you are
directly use the components available in the library, I mean there is
no necessity to create the VHDL .

  If you have a FSM design ( using the FSM editor) then it is in some
upper layer and so VHDL code is created for that one.

   Gurus please explain more

Ramnath




Adrian <g9731642@campus.ru.ac.za> wrote in message news:<ee73477.1@WebX.sUN8CHnE>...
> Don't know if is generated. I'm trying to see if Foundation automatically generates VHDL for schematic designs I have made, and if so where can I find these files!
> 
> adrian

Article: 36869
Subject: Re: read only version register usinga generic
From: "Johnsonw10" <johnsonw10_NOSPAM@hotmail.com>
Date: Thu, 22 Nov 2001 17:54:21 GMT
Links: << >>  << T >>  << A >>
Have you tried any number that is bigger than 54? I was wondering if there
is a pattern in the version numbers which makes your design not fit. Or
maybe it is just the randomness that causes the optimization/synthesis
algorithms not to work.

Jim

"Dave Brown" <dbrown@novatel.ca> wrote in message
news:9tj8na$k4j$1@pallas.novatel.ca...
> Nice try. 52 isn't prime and it worked. So did 48, and it has 2 and 3 in
> it's prime factorization.
> Thanks for the chuckle though,
> D.
> "Kevin Neilson" <kevin_neilson@removethis-yahoo.com> wrote in message
> news:_aYK7.158834$IR4.55129103@news1.denver1.co.home.com...
> > Fortunately I am an expert on numerology.  53 is prime, and has a good
> aura,
> > whereas 54 is not prime and has both 2's and 3's in its prime
> factorization,
> > which gives it bad karma.
> >
> > "Dave Brown" <dbrown@novatel.ca> wrote in message
> > news:9thcq5$34m$1@pallas.novatel.ca...
> > > Hi everyone,
> > >     I have a SpartanXL XCS-05 design that is a memory mapped device.
One
> > of
> > > the memory addresses is supposed to be an 8 bit version register that
> > > reflects the version of VHDL code that was used to synthesize the
> design.
> > I
> > > implemented this as generic integer in my top level module that gets
> > passed
> > > down to the address decoder. This way, I can just change the generic
in
> > the
> > > top level. When the version address shows up on the address bus, I
> return
> > > this generic using conv_unsigned(version, 8). This has worked fine.
> Until
> > > today, when I got to version 54. Now my design won't fit onto the
chip.
> I
> > > was at about 95% of 4-LUTs used up with version 53. With 54 as the
> > version,
> > > I get 103% of 4 input LUT's used. I thought maybe this was because of
> the
> > > changes, so I went back to the code for version 53 and just changed
the
> > > generic to 54. Presto, it doesn't fit into the design. I'm stumped.
> What's
> > > special about 54 vs 53? Nothing in my mind. Every number up to 54
worked
> > > fine. Hmm, any ideas?
> > > Thanks,
> > > Dave
> > >
> > >
> > >
> >
> >
>
>



Article: 36870
Subject: Altera Quartus fork bus on block diagram
From: cgorac@yahoo.com (Crni Gorac)
Date: 22 Nov 2001 09:55:54 -0800
Links: << >>  << T >>  << A >>
Am using Altera Quartus II Web edition for some simple designs for my
students. My question is: how to fork bus in BDF file using this tool?
For example, I'm trying to use 2 4-bit adders to create 8-bit adder
and I would like to separate op0[7..0] input to op0[3..0] input of
low-nibbles 4-bit adder and op0[3..0] input of high-nibbles 4-bit
adder.

Thanks.

Article: 36871
Subject: Re: Altera & Actel prices
From: Ben Popoola <o.m.popoola@sussex.ac.uk>
Date: Thu, 22 Nov 2001 18:31:29 +0000
Links: << >>  << T >>  << A >>
Try also
www.arrow.com as they have online prices for most devices. In general
however it depends on how many of a particular device you want to buy.

Tobias Stumber wrote:

> Hi !
>
> Could anyone give a quick guess for  the price of a
> Altera EP20K200E in a PQ208 Package (mid speed grade)
> and for the Actel A500K270 in this package (if applicable).
>
> I need this for a very rough price comparison with Xilinx
> and dont want to wake up sleeping dogs at the distributors.
>
> (The freetradezone does only give me the approx. price for
> the Xilinx part, 100 quantity.)
>
> Regards, Tobias


Article: 36872
Subject: Re: How do I.......
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Thu, 22 Nov 2001 18:40:42 GMT
Links: << >>  << T >>  << A >>
On Thu, 22 Nov 2001 12:29:03 +0100, "Harjo Otten"
<h.otten@rohill.geen.spam.nl> wrote:

>Hi,
>
>Can anybody help me with this:
>
>I've got a process with 2 inout busses  (8 bits wide) named PDi and PDo.
>When my "Normal_IO" signal is deasserted I want to put some data from
>another prcoess on the PDo bus, and do nothing with the PDi bus. But (and
>this is my problem) when "Normal_IO" is asserted I want to simply tie PDi
>and PDo together, so it's 'transparent' both ways. Is this possible ?? And
>what should the VHDL code for such a construction look like ??

Let me try to steer you to a different direction where you don't need
this construct at all. How do you really use a truly transparent bus ?
You obviously need some arbitration because two sides can't be driving
the bus to arbitraty values at the same time. Maybe you're using one
pin on the bus as a control signal to see who can talk ? Isolate the
arbitration logic and use it to change the transparent bus to a
bi-directional bus.

Muzaffer Kal

http://www.dspia.com
DSP algorithm implementations for FPGA systems

Article: 36873
Subject: Re: Altera Quartus fork bus on block diagram
From: "Johnsonw10" <johnsonw10_NOSPAM@hotmail.com>
Date: Thu, 22 Nov 2001 18:44:14 GMT
Links: << >>  << T >>  << A >>
http://www.pldworld.com/_altera/html/toolman/quartus_tutorial.pdf has an
example.

Jim

"Crni Gorac" <cgorac@yahoo.com> wrote in message
news:cb2002fc.0111220955.1033a5cb@posting.google.com...
> Am using Altera Quartus II Web edition for some simple designs for my
> students. My question is: how to fork bus in BDF file using this tool?
> For example, I'm trying to use 2 4-bit adders to create 8-bit adder
> and I would like to separate op0[7..0] input to op0[3..0] input of
> low-nibbles 4-bit adder and op0[3..0] input of high-nibbles 4-bit
> adder.
>
> Thanks.



Article: 36874
Subject: Re: too large a 32 entry 3 read 2 write register file
From: kayrock66@yahoo.com (Jay)
Date: 22 Nov 2001 11:55:52 -0800
Links: << >>  << T >>  << A >>
As I understand it, unlike Xilinx, Altera does not put a tri-state
buffer anywhere in their chip except for in the I/O cell.  So you have
to use the cleaner mux strategy.  But not to worry.  The 4 input look
up table structure that makes up most sram FPGA's can implement wide
muxes fairly efficiently if not slowly.  For example a 32 input mux
could be build using 11 look up tables.  So you've got no problem
fitting in that Altera part you mentioned.

shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0111211827.4c31d734@posting.google.com>...
> in my  design, I have a 32 entry 3 read and 2 write register file,
> each entry hold 32 bits.
> 
> so each read port have 31 mux to select out the desire register,3 read
> port nead nearly 100 mux, each mux is 32 bit width, so total 3000 mux
> needed|||, it is a large number for my APEX20K400E,
> 
> so I want to use tristate signal output for every entry,and tie them
> together to replace the large mux tree,but if it is a problem 32
> tristate signal drive a port?
> 
> or any other suggestion to deal with this too large register file?



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