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Messages from 36875

Article: 36875
Subject: Re: slew rate of virtex output buffers figures
From: kayrock66@yahoo.com (Jay)
Date: 22 Nov 2001 12:08:51 -0800
Links: << >>  << T >>  << A >>
Unless you are doing something really fast (my Vertex E design tops
out at only 21MHz) you can probably just use the same settings (output
impedance and slew rate option) and (IMHO) you'll be okay.

"jfh" <jfhasson@club-internet.fr> wrote in message news:<3bfbf990$0$26361$7a628cd7@news.club-internet.fr>...
> Hi,
> 
> I work with both virtex and virtex E and I am about to place and route my
> board but I wish I had the figures of the slew rate of the output buffers of
> a Virtex and virtex E in LVTTL for the different current grades and with the
> slow or fast slew rate option. Does anyone have that type of information
> because I could not find it ?
> Thank you.
> 
> J.F. Hasson

Article: 36876
Subject: Re: Fast Fourier Transformation - camera data
From: kayrock66@yahoo.com (Jay)
Date: 22 Nov 2001 12:52:28 -0800
Links: << >>  << T >>  << A >>
Could it be implimented in an FPGA?  Sure, it could.  You'd probably
have to add an external memory device (even using the block syle rams
available "now-a days".  Should you?  We that depends on other factors
you haven't listed, namely speed of operation.  But on the other had,
well written assembler running in cache on a 2GHz P4 may beat an FPGA.

Fixed versus floating- same deal,  you haven't given enough data to
make that decision, but in general, if the precision of your input
sequence is limited, there is little value to using floating point in
the calculation.  A time you might use float would be if you had a
recursive filter, like a low pass for your image squence.

In general, if you can do it in software, do it that way.  Your life
will be easier.


Thomas Wambera <thomas@wambera.de> wrote in message news:<1103_1005637743@asic15>...
> Hello ng!
> 
> I am looking for an open Core which contains functions as Fast Fourier Transformation (possibly the Butterfly algorithm).
> Does anybody know about?
> 
> My other problem is that I have to implement a 2 dimensional analysis of Camera data. Every row can be calculated 
> during measurement, but the y-direction (the coloums) have to be stored and calculated later. Does anybody have an 
> idea what would be the best possibility to do so? The main problem is the mass of data, with an greyscale camera (8 
> bit/pixel) and a picture of 512x512 an immense memory is needed. The other problem is the data format, it should be 
> float, but is that precise enough to calculate with?
> 
> One possibility to save memory would be in-place calculating, but is it anyhow possible to realize with an fpga or should 
> it be done in a pc ?
> 
> If you would use an fpga, could the block ram be the "candidate" for storing the data or is it to less memory, also in the 
> "E" series of Virtex?
> 
> Thanks for your interest!

Article: 36877
Subject: Re: How can I solve the "clock" warning of synplify.
From: kayrock66@yahoo.com (Jay)
Date: 22 Nov 2001 13:02:05 -0800
Links: << >>  << T >>  << A >>
Basically restating what Phil said, recode your design to use an
enable instead of driving the clock from logic.  Better to do it clean
than patching a warning message.

"duola" <deerlux@hotmail.com> wrote in message news:<9sve8c$k9t$1@mail.cn99.com>...
> When I synthesized my design using Synplify I got the following warning:"Net
> G_3 appears to
> be a clock source which was not identified. Assuming default frequency" Does
> it mater? How can I solve the problem?

Article: 36878
Subject: Re: slew rate of virtex output buffers figures
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 22 Nov 2001 21:32:22 +0000
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> Let me make a constructive suggestion:
>
> We will publish a step-by-step cookbook how you can use the free
> version of HypeLynx to analyze output behavior with astounding
> accuracy and surprising ease.

Do you mean the "demo" version or is there something else I can't see on
the site? I had a look there some while ago but the word "demo" to me
tends to mean next-to-useless. Maybe my cynisism is misplaced in this
case ...

<snip>

>
> That's what Austin meant when he mentioned the need to learn how to
> fish.
> Signal integrity is no longer a subject only for the speed-demons, it
> affects every design.
> We all have got lo learn this "new" discipline, whether we want to or
> not.
> And the available tools actually make it fun, once you master them.

I agree & I want to, finally, start getting to grips with this stuff. In
the past, though, what's tended to put me off is the quantity of $$$s
required to get into it, a bit like simulation & synthesis tools until
ModelSIM-PE & Synplicity came along.






Article: 36879
Subject: Re: Decoupling capacitors on Virtex II
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Thu, 22 Nov 2001 14:29:16 -0800
Links: << >>  << T >>  << A >>
On 22 Nov 2001 13:39:48 +0000, Martin Thompson
<martin.j.thompson@trw.com> wrote:
>
>Just be careful that the way you mount the capacitors doesn't add too
>muc more inductance to the capacitor's inherent inductance.  Vias on
>the end of traces from the cap pads can be 4nH.  My last design I had
>caps mounted on a large plane pad with several (3-4) vias through each
>end.  This should add 1nH ish.
>
>Then you are relying on the planes having a low spreading inductance
>to deliver the power to the chip, which must also be mounted on
>*really* short traces.
>
>Cheers,
>Martin


Martin,

I did a couple of VME boards that used 3.3 volt Xilinx fpga's. The 3.3
volt island was part of a split plane (3.3 under fpga's, 5 volt plane
elsewhere) with a 0.005 inch dielectric between power plane and ground
plane. Just for fun, I designed a few SMA connector footprints into
the board so I could access the power planes.

On bare boards, using a Tek 11801 (20 GHz) TDR, the 3.3 and 5 volt
pours looked, as near as I could measure, like ideal capacitors of the
expected values, with just a tad of inductance at the SMA connector
transition. Otherwise, no sign of ringing or edge effects.

I then started adding the bypass caps, here and there. As close as I
could measure, the effective capacitance increased by the added C
value, no matter where I put them. Again, no sign of ringing or
distance effects.

So I conclude that the planes themselves are the ultimate high-speed
bypass, and the caps provide the longer-term energy storage. After
all, a 10" wide, 0.005" spaced, Er=5 transmission line is a pretty
low-impedance thing.

So we put maybe four 0805, 0.1 uf ceramics per FPGA, one per every few
smaller chips, and a couple of 10 volt tantalums per board, and don't
worry much about exactly where they go. Manufacturing hates vias in
pads, so we extend a short 20 mil trace before we hit the via. On a
running board, measuring the signals at the SMA connectors verifies
that things are quiet.

Given this, the often cited Sun papers are pretty much nonsense; they
fixate on simulating caps but ignore the planes.


John


Article: 36880
Subject: Re: Synplicity and BlockRAM?
From: barnish@hotmail.com (Andrew Barnish)
Date: 22 Nov 2001 15:15:43 -0800
Links: << >>  << T >>  << A >>
Hi,

It sounds like Synplicity is inferring LUTs instead of a blockram.
The BUFTs are used the mux the outputs of the LUTs, since each LUT is only 16x1 bit.
A simple one line in your contraint file (.sdc) will fix this:

define_attribute    {ram[3:0]} syn_ramstyle {block_ram}

or you can put it as an attribute in the VHDL.
See the docs for further info. There are plenty of examples there too.

Regards,

Andy Barnish
Roke Manor Research, UK


VR <thisisntvalid@invaldireturn.co> wrote in message news:<9td9de$hk3$2@news.utdallas.edu>...
> Hey all.
> 
> For a project in VHDL, it was suggested by a colleague of mine for doing
> RAM intensive applications, that it is easier to instantiate a small RAM
> as opposed to creating an array of std_logic_vector.
> 
> I was passed on this code, however when synthesizing for an XCV-800
> (Virtex I) using Synplicity Synplify Pro 7.0, it for some odd reason uses
> 1024 tri-buffs! (BUFFT).
> 
> The same code works fine in Spectrum (I checked) and I told works with XSV
> synthesis. Neither use BUFFTs or an inordinate amount.
> 
> I can't get this simple code to even P&R in Foundation (after being
> synthesized by Synplicity), I am told that I cannot have more than 86
> BUFFTs on a net and that I actually have 4 sets of 256 BUFFTs.
> 
> Any ideas on how to correct? Code is as follows:
> 
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> 
> entity ram is 
>  port (clk : in std_logic; 
>  	we  : in std_logic; 
>  	a   : in std_logic_vector(11 downto 0); 
>  	di  : in std_logic_vector(3 downto 0); 
>  	do  : out std_logic_vector(3 downto 0)); 
>  end ram; 
>  
>  architecture syn of ram is 
>  
>  type ram_type is array (4095 downto 0) of std_logic_vector (3 downto 0); 
>  signal RAM : ram_type; 
>  signal read_a : std_logic_vector(11 downto 0); 
>  
>  begin 
>  process (clk) 
>  begin 
>  	if (clk'event and clk = '1') then  
>  		if (we = '1') then 
>  			RAM(conv_integer(a)) <= di; 
>  		end if; 
>  		read_a <= a; 
>  	end if; 
>  end process; 
>  
>  do <= RAM(conv_integer(read_a));
>  
>  end syn;
>  
> Thanks!
> VR.

Article: 36881
Subject: 3 Input LUTs in SpartanXL
From: "Dave Brown" <dbrown@novatel.ca>
Date: Thu, 22 Nov 2001 17:26:39 -0700
Links: << >>  << T >>  << A >>
What design changes do I need to make in VHDL to increase my utilization of
3 input LUT's in a SpartanXL device? I'm just about out of 4-input LUTs, but
I have lots of 3 input ones available. Is there any quick tips anyone has to
make synthesis use the 3 input ones?
Thanks,
Dave




Article: 36882
Subject: Re: how can define function in terms of equation rather than gates in XC4000 series
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 23 Nov 2001 01:43:55 GMT
Links: << >>  << T >>  << A >>
Hi Sema,

Before I get into an answer, are you aware that XC4000 is now quite old,
and maybe you should consider Xilinx Spartan, Spartan-II, Virtex, or
Virtex-II products. The current sw from xilinx does not support the
original XC4000 family. Current support starts at XC4000E family.

You may want to download the free current sw from Xilinx called
WebPack that handles current products, and includes its own schematic
package (not as good as Orcad, but free), and also has Verilog and VHDL
synthesis and simulation.

On to your question: The XC3000 CLB primative has no equivalent in any
other architecture.

FMAP which can be used with all architectures starting with XC4000
works differently. It is well documented here:

http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/chap05/lib05046.htm

you can see all the documentation here:

http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm

You can get PDF copies if you wish here:

http://toolbox.xilinx.com/docsan/xilinx4/index.htm


For text based descriptions of logic, most people use Verilog or VHDL,
but the abstraction level is very much higher than the CLB primitives
of the XC3000. The CLB primitives are like a very low level assembler,
and Verilog/VHDL are like C in comparison. You can get a lot more done
quickly, but with less detailed control.

Recommendation: change to a newer product family, and start learning
Verilog or VHDL.

All the best

Philip Freidin

On 22 Nov 2001 01:24:44 -0800, skoc@gantep.edu.tr (skoc) wrote:
>I'm a Phd student and I'm working on Xilinx XC4000 project. I've used
>schematic editor of ORCAD.I want to learn that is XC4000 series allows
>functionality to specified in terms of equationrather than gates, like
>CLB primitive in XC3000 series. if it is possible how can I do. I
>haven't successed this using FMAP. Is possible help me about this
>problem? thanks.
>Regards,
>sema KOÇ

Philip Freidin
Fliptronics

Article: 36883
Subject: Re: fix LOC on LUT1
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 23 Nov 2001 01:48:46 GMT
Links: << >>  << T >>  << A >>
The RLOC/LOC gets you to a specific slice, the BEL attribute controls mapping
within a slice.

syntax is:   BEL={F | G |FFX | FFY | XORF | XORG}

example from a UCF file is:

    INST xyzzy BEL=FFX;

This info is from the Xilinx Libraries guide, page 775

Philip Freidin



On 22 Nov 2001 09:37:36 GMT, khtsoi@cse.cuhk.edu.hk wrote:
>Hi,
>
>I must fix a NOT gate to a cretain location and the
>gate is in form of LUT1 in Xilinx XCV1000E. I can
>use the RLOC/LOC to give a location like R12C3.S0
>under Synopsys DC. But I want to give more constrain
>to the location (i.e. in F-function or G-function LUT
>inside a slide). What can I do? Thanks in advance!
>
>---- Brittle

Philip Freidin
Fliptronics

Article: 36884
Subject: Re: Xilinx and Multirate clock ??
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Fri, 23 Nov 2001 01:50:22 GMT
Links: << >>  << T >>  << A >>
Andy Peters wrote:
> 
> Lasse Langwadt Christensen wrote:
> 
> > -Lasse
> > -- Lasse Langwadt Christensen,
> > -- A Dane in Phoenix, Arizona
> 
> Wow...summer must've been, um, "interesting" for ya!
> 
> -andy
> -- A Jersey boy in Tucson, Arizona

nahh, it wasn't too bad I'm from a place that has seasons :)
And too hot or too cold and wet to be outside doesn't make 
a big difference.

Now that I've spend the summer in Arizona, I get to 
go home and spend winter in Denmark, perfect planning :)  

-Lasse
-- Lasse Langwadt Christensen, 
-- A Dane in Phoenix, Arizona

Article: 36885
Subject: Urgent need - PCI Bus Analyzer
From: john@aja.com (John Abt)
Date: 22 Nov 2001 21:44:27 -0800
Links: << >>  << T >>  << A >>
Urgently need (like yesterday) a 64/33 or 64/66 PCI bus
analyzer. Agilent E2926b, E2928A, or Vmetro PBT-515
would do. Will buy, rent, lease, borrow, do yardwork,
anything. 

John Abt
800-251-4224

Article: 36886
(removed)


Article: 36887
Subject: Re: Altera Quartus fork bus on block diagram
From: cgorac@yahoo.com (Crni Gorac)
Date: 22 Nov 2001 23:57:30 -0800
Links: << >>  << T >>  << A >>
Thank you for your reply but - could you be more specific? I've read
the tutorial already and am unable to find example you are referring
to. I've tried various combinations (naming of busses, explicit
mappers), but without success. Maybe my problem is in names - e.g.
4-bit adder inputs are named in0[3..0] and in1[3..0] and I'm trying to
name 8-bit adder inputs as in0[7..0] and in1[7..0]?

Thanks.


"Johnsonw10" <johnsonw10_NOSPAM@hotmail.com> wrote in message news:<2IbL7.988$oV2.567091@typhoon.ne.mediaone.net>...
> http://www.pldworld.com/_altera/html/toolman/quartus_tutorial.pdf has an
> example.
> 
> Jim
> 
> "Crni Gorac" <cgorac@yahoo.com> wrote in message
> news:cb2002fc.0111220955.1033a5cb@posting.google.com...
> > Am using Altera Quartus II Web edition for some simple designs for my
> > students. My question is: how to fork bus in BDF file using this tool?
> > For example, I'm trying to use 2 4-bit adders to create 8-bit adder
> > and I would like to separate op0[7..0] input to op0[3..0] input of
> > low-nibbles 4-bit adder and op0[3..0] input of high-nibbles 4-bit
> > adder.
> >
> > Thanks.

Article: 36888
Subject: Re: Fpga Synthesis Process
From: ramnathgoenka@yahoo.com (Ramnath)
Date: 23 Nov 2001 01:06:51 -0800
Links: << >>  << T >>  << A >>
Hi,

    Sorry krishna i have missed a long time.

    Anyway i could get from your message, 

    Another message, what is the exact use of the simulation tool
provided in xilinx. i hope we can do the Functional and Timing
simulation in Model sim itself. AM i correct.  ofcourse we need some
file (*.SDF if i am  correct) to do timing simulation. could you
please tell me which process gives you that file.

  I use Xilinx v1.5   

   Ramnath


pvkrishna@indiatimes.com (krishna P V) wrote in message news:<e84cd65e.0110250413.1569aa25@posting.google.com>...
> "Johan Van Dyck" <Johan.Van.Dyck@philips.com> wrote in message news:<3bd6a983$0$7113$4d4efb8e@news.be.uu.net>...
> > Hi
> > 
> > * The synth process reads your code and transforms it to known blocks like
> > mux, adder,... It also unrolls the loops.
> > * The mapper (implementation) maps the generic blocks from the synth to the
> > real lay-out from your FPGA. As a generic block could be  a '200 to 5 mux',
> > in the FPGA only '4 to 2 mux' (this is an expample) could exist. Lot's of
> > 4t02 mux must be cascaded to form the original block.
> > * After mapping you can simulate a kind of gatelist generated out of the
> > tool. (We never use that).
> > *Of course, you need to verify the FPGA after the mapping is programmed
> > insite.
> > 
> > Hope this helps you a littel bit
> > 
> > Johan.
> > 
> > "Ramnath" <ramnathgoenka@yahoo.com> wrote in message
> > news:62cc2cff.0110201050.7d89b335@posting.google.com...
> > > hi,
> > >
> > >     I am a newbie to this area and slowly picking up things. I am
> > > using Xilinx foundation series v 1.5 and Model sim.
> > >
> > >     Alothough i have all these and even using these things, i do not
> > > fully understand the concept of all.
> > >
> > >    Could any one tell me what are the various stages in the synthesis
> > > of FPGA.
> > >
> > > To be exact what is done in the synthesis process, implementation
> > > process, simulation and verification.
> > >
> > >    What is the difference between simulation done in ModelSim and the
> > > simulation done in Xilinx itself.
> > >
> > >   Some one told me Modelsim is for simulation the testbeches ( still
> > > not clear, please through some light)
> > >
> > >        Thanks a lot in advance and expecting the reply.
> > >
> > > Ramnath
> 
> Ramanath,
> As you write, modelsim is effictively suitable for testbenches,of
> course even for models. I have smatttering of knowledge about xillinx
> software.So i will leave it to others. The advantages you get with the
> modelsim are great. For example transport delays,file operation ,and
> also some other advanced features will not work in . You can even talk
> with your VHDL designs with C programs.
>   
>    If your design is very big, you can't apply signals through force
> commands and see output signals. Your testbench should be very
> exhaustive one. In Some cases, it will be better to have the testbench
> that applies the signal upon our need and finally tells that your
> model is correctly functioning or not.Using VHDL advanced features and
> the modelsim features, the job of getting a good testbench will be
> easy one.
> 
> questions welcome,
> regards,
> krishna

Article: 36889
Subject: Re: Decoupling capacitors on Virtex II
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 23 Nov 2001 09:46:18 +0000
Links: << >>  << T >>  << A >>
John  Larkin <jjlarkin@highlandSNIPTHIStechnology.com> writes:

<snip>
> I did a couple of VME boards that used 3.3 volt Xilinx fpga's. The 3.3
> volt island was part of a split plane (3.3 under fpga's, 5 volt plane
> elsewhere) with a 0.005 inch dielectric between power plane and ground
> plane. Just for fun, I designed a few SMA connector footprints into
> the board so I could access the power planes.
> 

That was something I had pondered doing recently also, glad someone
else did the hard work though :-)

> On bare boards, using a Tek 11801 (20 GHz) TDR, the 3.3 and 5 volt
> pours looked, as near as I could measure, like ideal capacitors of the
> expected values, with just a tad of inductance at the SMA connector
> transition. Otherwise, no sign of ringing or edge effects.
> 

As expected with a 5thou spacing.  Things get a bit more tricky is you
are doing 4 layer 1.6mm boards, as the spreading inductance gets more
significant then.

> I then started adding the bypass caps, here and there. As close as I
> could measure, the effective capacitance increased by the added C
> value, no matter where I put them. Again, no sign of ringing or
> distance effects.
> 
> So I conclude that the planes themselves are the ultimate high-speed
> bypass, and the caps provide the longer-term energy storage. After
> all, a 10" wide, 0.005" spaced, Er=5 transmission line is a pretty
> low-impedance thing.
> 

And so long as the caps are closer (in time) than the edge you are
trying to support, things are fine!  For example if we take speed of
propogation equal to 1/2 speed of light in free space (which is
conservative), a 1ns edge is 15 cm "long", so if your caps are within
7.5cm the edge will "see" them fine.  Or is my physics flawed?

> So we put maybe four 0805, 0.1 uf ceramics per FPGA, one per every few
> smaller chips, and a couple of 10 volt tantalums per board, and don't
> worry much about exactly where they go. Manufacturing hates vias in
> pads, so we extend a short 20 mil trace before we hit the via. On a
> running board, measuring the signals at the SMA connectors verifies
> that things are quiet.
> 

I didn;t end up putting the vias in the pads, just extended a plane
fill out from the pad and stuck the vias in there.  This may have been
no better than a trace, but it made it easier to get multiple vias
in.  You results imply that that might be overkill anyway though.

> Given this, the often cited Sun papers are pretty much nonsense; they
> fixate on simulating caps but ignore the planes.
> 

I wouldn't go as far as nonsense (but then I'm not a PDS guru),
but I agree that the planes are neglected in the one I have next to
me.

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 36890
Subject: wget of WebPack
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 23 Nov 2001 12:01:17 +0100
Links: << >>  << T >>  << A >>

In case somebody is struggling with a not-internet-exporer-for-windows
web browser (like myself, using Opera under Linux) to download WebPack
- Here is how you can download it using wget:

wget --http-user USER --http-passwd PASS http://www.xilinx.com/webpack/41wp2/WebPACK_41wp20_full_installer.exe

Where USER is your Xilinx registered username and PASS is your
selected password.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 36891
Subject: Using XC18Vxx ISP config proms with Spartan XL
From: "Lionel DORIS" <lionel.doris@lab-leas.fr>
Date: Fri, 23 Nov 2001 12:39:41 +0100
Links: << >>  << T >>  << A >>
Hi.

I am using XC17S10XL configuration proms ( OTP prom ) with SPARTAN XL.
It's possible to use XC18Vxx In system programming config proms ( FLASH )
with SPARTAN XL FPGA ?
What is the best mode : Master serial mode or parallel Express mode ?

Lionel




Article: 36892
(removed)


Article: 36893
Subject: Re: Altera Quartus fork bus on block diagram
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Fri, 23 Nov 2001 16:43:05 +0100
Links: << >>  << T >>  << A >>
Naming the busses should work.
You can download a simple example from:

http://www.elca.de/downloads/bus_test.zip

- Wolfgang
http://www.elca.de

"Crni Gorac" <cgorac@yahoo.com> schrieb im Newsbeitrag
news:cb2002fc.0111220955.1033a5cb@posting.google.com...
> Am using Altera Quartus II Web edition for some simple designs for my
> students. My question is: how to fork bus in BDF file using this tool?
> For example, I'm trying to use 2 4-bit adders to create 8-bit adder
> and I would like to separate op0[7..0] input to op0[3..0] input of
> low-nibbles 4-bit adder and op0[3..0] input of high-nibbles 4-bit
> adder.
>
> Thanks.



Article: 36894
Subject: Re: how to imply tristate buffer in APEX20K
From: "Jan Gray" <jsgray@acm.org>
Date: Fri, 23 Nov 2001 08:09:17 -0800
Links: << >>  << T >>  << A >>

"ssy" <shengyu_shen@hotmail.com> wrote in message
news:f4a5f64f.0111220242.8f7e5f@posting.google.com...
> Hi
>
> I am using APEX20K, and I know that there is no build in tristate
> buffer in PAEX, but xilinx device have build in tri state buffer, so a
> tri state buffer in APEX will occupy a LE, right?
>
> I have a register file with 32 entry, and 3 read port, so if I use 3
> mux tree to select desire register, then this register file will
> consume about 4000 LE, so  want to use tri state signal to replace mux
> tree, but after that, the register file's size do not change too much,
>
> how to deal with this?

Put the register file in proper RAM (EABs/ESBs), e.g. as first described in
http://www.fpgacpu.org/usenet/altera_cpus_dual_port_EABs.html.  Each SRAM
is, after all, conceptually just a big cheap array of flip-flops, write
enable decoders, and output multiplexers.

Also, you might value visiting http://fpga-faq.com/archives/index.html
and/or google.com and searching for "Altera register file".

Jan Gray, Gray Research LLC




Article: 36895
Subject: Re: fix LOC on LUT1
From: Ray Andraka <ray@andraka.com>
Date: Fri, 23 Nov 2001 16:12:43 GMT
Links: << >>  << T >>  << A >>
For Virtex/VIrtexE, you can use a BEL constraint to place an element
within the F or G LUTs, the X or Y flip-flops or the F or G xorcy gate.

attribute BEL:string;
attribute BEL of U1: label is "F";
attribute BEL of U2: label is "G";
attribute BEL of U3: label is "FFX";
attribute BEL of U4: label is "FFY";
attribute BEL of U5: label is "XORF";
attribute BEL of U6: label is "XORG";




khtsoi@cse.cuhk.edu.hk wrote:

> Hi,
>
> I must fix a NOT gate to a cretain location and the
> gate is in form of LUT1 in Xilinx XCV1000E. I can
> use the RLOC/LOC to give a location like R12C3.S0
> under Synopsys DC. But I want to give more constrain
> to the location (i.e. in F-function or G-function LUT
> inside a slide). What can I do? Thanks in advance!
>
> ---- Brittle

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36896
Subject: Re: Fast Fourier Transformation - camera data
From: Ray Andraka <ray@andraka.com>
Date: Fri, 23 Nov 2001 16:28:21 GMT
Links: << >>  << T >>  << A >>
Open core might be a bit tough, if you want it with any kind of performance or density.  Both Altera and Xilinx have FFT cores
in their free libraries, however you don't get the source.  We sell  highly optimized 8 and 16 point cores that can be clocked
at the limit of the FPGA (clock rate is limited by the SRL16 pulse width).  Our cores are also considerably more compact than
the free cores (the 16 point core fits in an XC2S100).

A well executed FFT design in an FPGA will significantly outperform a microprocessor, and it has the advantage of being able to
be accelerated by paralleling kernels.  Or 16 point core, in a virtexE-8 does pipelined 16 point FFTs in 70ns.  We've done
custom 4K point designs with it that do better than 70 us in space grade military FPGAs (-4 speed grade).

Floating point can become advantageous with larger FFTs because of the gains, even if your input is limited to a small number of
bits.  For a 4K FFT, you may find it preferable to have a block floatinog point over fixed point to keep precision reasonable
without severely limiting dynamic range.

Jay wrote:

> Could it be implimented in an FPGA?  Sure, it could.  You'd probably
> have to add an external memory device (even using the block syle rams
> available "now-a days".  Should you?  We that depends on other factors
> you haven't listed, namely speed of operation.  But on the other had,
> well written assembler running in cache on a 2GHz P4 may beat an FPGA.
>
> Fixed versus floating- same deal,  you haven't given enough data to
> make that decision, but in general, if the precision of your input
> sequence is limited, there is little value to using floating point in
> the calculation.  A time you might use float would be if you had a
> recursive filter, like a low pass for your image squence.
>
> In general, if you can do it in software, do it that way.  Your life
> will be easier.
>
> Thomas Wambera <thomas@wambera.de> wrote in message news:<1103_1005637743@asic15>...
> > Hello ng!
> >
> > I am looking for an open Core which contains functions as Fast Fourier Transformation (possibly the Butterfly algorithm).
> > Does anybody know about?
> >
> > My other problem is that I have to implement a 2 dimensional analysis of Camera data. Every row can be calculated
> > during measurement, but the y-direction (the coloums) have to be stored and calculated later. Does anybody have an
> > idea what would be the best possibility to do so? The main problem is the mass of data, with an greyscale camera (8
> > bit/pixel) and a picture of 512x512 an immense memory is needed. The other problem is the data format, it should be
> > float, but is that precise enough to calculate with?
> >
> > One possibility to save memory would be in-place calculating, but is it anyhow possible to realize with an fpga or should
> > it be done in a pc ?
> >
> > If you would use an fpga, could the block ram be the "candidate" for storing the data or is it to less memory, also in the
> > "E" series of Virtex?
> >
> > Thanks for your interest!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 36897
Subject: Re: Viewing generated VHDL
From: Nick Macias <nmacias@cellmatrix.com>
Date: Fri, 23 Nov 2001 10:22:56 -0700
Links: << >>  << T >>  << A >>
WebPack's schematic entry system/design flow creates a .VHF file
somewhere along the way, which seems to contains the (flat?) VHDL for
the circuit you create. Not sure about Foundation (I just started
working with Webpack yesterday).

	Nick

> Adrian <g9731642@campus.ru.ac.za> wrote in message news:<ee73477.1@WebX.sUN8CHnE>...
> > Don't know if is generated. I'm trying to see if Foundation automatically generates VHDL for schematic designs I have made, and if so where can I find these files!
> >
> > adrian

Article: 36898
Subject: Re: Decoupling capacitors on Virtex II
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Fri, 23 Nov 2001 10:36:53 -0800
Links: << >>  << T >>  << A >>
On 23 Nov 2001 09:46:18 +0000, Martin Thompson
<martin.j.thompson@trw.com> wrote:

>John  Larkin <jjlarkin@highlandSNIPTHIStechnology.com> writes:
>
><snip>
>> I did a couple of VME boards that used 3.3 volt Xilinx fpga's. The 3.3
>> volt island was part of a split plane (3.3 under fpga's, 5 volt plane
>> elsewhere) with a 0.005 inch dielectric between power plane and ground
>> plane. Just for fun, I designed a few SMA connector footprints into
>> the board so I could access the power planes.
>> 
>
>That was something I had pondered doing recently also, glad someone
>else did the hard work though :-)
>
>> On bare boards, using a Tek 11801 (20 GHz) TDR, the 3.3 and 5 volt
>> pours looked, as near as I could measure, like ideal capacitors of the
>> expected values, with just a tad of inductance at the SMA connector
>> transition. Otherwise, no sign of ringing or edge effects.
>> 
>
>As expected with a 5thou spacing.  Things get a bit more tricky is you
>are doing 4 layer 1.6mm boards, as the spreading inductance gets more
>significant then.
>

Even on 4-layer boards, we specify a very thin dielectric layer
between the power and ground planes to get the best plane effects. The
PCB fab houses don't seem to mind.

>> I then started adding the bypass caps, here and there. As close as I
>> could measure, the effective capacitance increased by the added C
>> value, no matter where I put them. Again, no sign of ringing or
>> distance effects.
>> 
>> So I conclude that the planes themselves are the ultimate high-speed
>> bypass, and the caps provide the longer-term energy storage. After
>> all, a 10" wide, 0.005" spaced, Er=5 transmission line is a pretty
>> low-impedance thing.
>> 
>
>And so long as the caps are closer (in time) than the edge you are
>trying to support, things are fine!  For example if we take speed of
>propogation equal to 1/2 speed of light in free space (which is
>conservative), a 1ns edge is 15 cm "long", so if your caps are within
>7.5cm the edge will "see" them fine.  Or is my physics flawed?

The TDR we used has a net risetime of about 30 ps, or about 0.1"
resolution inside FR4. Yes, it surprised me that the bypass cap
location made no discernable difference to the impedance seen at the
SMA test point. I think the FR4 material is lossy enough to smear out
any reflections (or, in the frequency domain, kill the Q of any
resonances, which would be well into the GHz range here). 

I embarked on this because (besides it being fun) I had just finished
a board that, using the usual ROTs, had something like 200 bypass
caps, and it occurred to me that a) this was silly and b) I had never
designed a multilayer board that actually failed because of
insufficient logic bypasses.

Hey, I'm an engineer; I don't have to understand it, I only have to
make it work!


John



Article: 36899
Subject: Re: Using XC18Vxx ISP config proms with Spartan XL
From: shane@metronsys.com (Shane Rowell)
Date: 23 Nov 2001 12:04:42 -0800
Links: << >>  << T >>  << A >>
"Lionel DORIS" <lionel.doris@lab-leas.fr> wrote in message news:<9tlci5$6b0$1@s1.read.news.oleane.net>...
> Hi.
> 
> I am using XC17S10XL configuration proms ( OTP prom ) with SPARTAN XL.
> It's possible to use XC18Vxx In system programming config proms ( FLASH )
> with SPARTAN XL FPGA ?
> What is the best mode : Master serial mode or parallel Express mode ?
> 
> Lionel

Lionel,

I have just looked into this for a new project. I use a XCS30XL and
plan to use a XC18V512. I will socket the prom and bring out the JTAG
pins out for in-circuit programming

Master serial is easiest configuration. The data sheet provides all of
the info that you should need.  You could also use a micro attached to
the JTAG pins for even more fun.

-Shane



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