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Messages from 36975

Article: 36975
Subject: Re: Device Support in Webpack
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Tue, 27 Nov 2001 14:52:31 -0700
Links: << >>  << T >>  << A >>
Hello Rick,

Devices supported in WebPACK besides all Xilinx CPLDs include
Virtex-E and Virtex-II devices up to 300K and all Spartan-II and
Spartan-IIE devices.

The main features that WebPACK is missing when compared to the
Foundation version of ISE are Core Generator, FPGA Editor, and
FPGA Express synthesis.

As far as OS support, Windows XP is not officially supported but
many cases have been seen where the software has worked fine.
I know that the Xilinx support team has a machine with a fresh
install of XP up and running with no changes to the OS. You may
want to get in contact with an FAE about this as they've probably
seen cases for both sides of the story.

I hope this helps.

Regards,
Kamal

> I checked out the info on which devices are supported by the ISE Webpack
> software and it looks like Virtex II 40, 80 and 250 are supported in
> addition to all of the Spartan II and IIE(?).
>
> http://www.xilinx.com/ise/products/webpack_config.htm
>
> Can anyone verify that these devices are actually supported and working
> in the current release of Webpack?
>
> Also, it is clear that only a trial version of ModelSim is included and
> you need to buy the XE version if you want to do real work with the
> simulator. Are there any other pieces included that are not fully
> functional?
>
> Finally, the only supported OS listed are 98, 2000 and NT 4.0. Anyone
> know if they plan to update this list with something more current like
> XP? I expect to be buying a new machine soon and hate to have to use an
> old OS just for Xilinx.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 36976
Subject: Re: Device Support in Webpack
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 27 Nov 2001 15:49:48 -0700
Links: << >>  << T >>  << A >>
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Theron Hicks wrote:

> I have used the webpack for the virtex2-40 series device.  Web pack does not
> support logiblox, coregen, and FPGA editor.  With those exceptions I found
> it to be quite usable.  The so-called modelsim limitation is not entirely
> true.  Modelsim is crippled in that as the simulations get more and more
> lines of code the simulator gets bogged down.  It does not stop entirely.  I
> have used it to simulate a virtex2-40 with 95% of the chip utilized.



> The worst thing I can say about the modelsim is that the models for DCM's and
> other similar virtex2 specific devices are not simulatable at the behavioral
> or post-translate levels.  Thus to simulate a DCM one has to at least map
> the device to get a simulation result

Could you elaborate on the statement above concerning not being able to simulate
the DCM's at a behavioral level?  There are simulation models for the DCMs (and
virtually all other Virtex-II primitives) availible in the UNISIM library for
behavioral simulation that are true functional models with a few limitations
that are documented in Answer Record #10861.  They work fine for most however I
am not exactly sure what you are refering to as "not simulatable" so I can not
be too much more specific as to your issues.  Perhaps I can help you out with
that with a little more information.


--  Brian



> .  If you are just using standard VHDL
> then model-sim webpack works great.
>
> rickman wrote:
>
> > I checked out the info on which devices are supported by the ISE Webpack
> > software and it looks like Virtex II 40, 80 and 250 are supported in
>
> Correct
> also, the virtexE series up to 300K gates, spartan2, and spartan2E to
> similar sizes.
> also Coolrunner, coolrunner2, and XC9500, xc9500xl and xc9500xv series
> devices.  These all show up in my options for devices.  I have gone to the
> ISE4.1 package but only because I really wanted the coregen devices.  It was
> $695 with the same modelsim as webpack.
>
> By the way, if anyone knows a workaround for any of my complaints, please
> let me know.
>
> Thanks,
> Theron Hicks
>
> >
> > addition to all of the Spartan II and IIE(?).
> >
> > http://www.xilinx.com/ise/products/webpack_config.htm
> >
> > Can anyone verify that these devices are actually supported and working
> > in the current release of Webpack?
> >
> > Also, it is clear that only a trial version of ModelSim is included and
> > you need to buy the XE version if you want to do real work with the
> > simulator. Are there any other pieces included that are not fully
> > functional?
> >
> > Finally, the only supported OS listed are 98, 2000 and NT 4.0. Anyone
> > know if they plan to update this list with something more current like
> > XP? I expect to be buying a new machine soon and hate to have to use an
> > old OS just for Xilinx.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;
<p>Theron Hicks wrote:
<blockquote TYPE=CITE>I have used the webpack for the virtex2-40 series
device.&nbsp; Web pack does not
<br>support logiblox, coregen, and FPGA editor.&nbsp; With those exceptions
I found
<br>it to be quite usable.&nbsp; The so-called modelsim limitation is not
entirely
<br>true.&nbsp; Modelsim is crippled in that as the simulations get more
and more
<br>lines of code the simulator gets bogged down.&nbsp; It does not stop
entirely.&nbsp; I
<br>have used it to simulate a virtex2-40 with 95% of the chip utilized.</blockquote>

<br>&nbsp;
<blockquote TYPE=CITE>The worst thing I can say about the modelsim is that
the models for DCM's and
<br>other similar virtex2 specific devices are not simulatable at the behavioral
<br>or post-translate levels.&nbsp; Thus to simulate a DCM one has to at
least map
<br>the device to get a simulation result</blockquote>

<p><br>Could you elaborate on the statement above concerning not being
able to simulate the DCM's at a behavioral level?&nbsp; There are simulation
models for the DCMs (and virtually all other Virtex-II primitives) availible
in the UNISIM library for behavioral simulation that are true functional
models with a few limitations that are documented in <a href="http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10861">Answer
Record #10861</a>.&nbsp; They work fine for most however I am not exactly
sure what you are refering to as "not simulatable" so I can not be too
much more specific as to your issues.&nbsp; Perhaps I can help you out
with that with a little more information.
<br>&nbsp;
<p>--&nbsp; Brian
<br>&nbsp;
<br>&nbsp;
<blockquote TYPE=CITE>.&nbsp; If you are just using standard VHDL
<br>then model-sim webpack works great.
<p>rickman wrote:
<p>> I checked out the info on which devices are supported by the ISE Webpack
<br>> software and it looks like Virtex II 40, 80 and 250 are supported
in
<p>Correct
<br>also, the virtexE series up to 300K gates, spartan2, and spartan2E
to
<br>similar sizes.
<br>also Coolrunner, coolrunner2, and XC9500, xc9500xl and xc9500xv series
<br>devices.&nbsp; These all show up in my options for devices.&nbsp; I
have gone to the
<br>ISE4.1 package but only because I really wanted the coregen devices.&nbsp;
It was
<br>$695 with the same modelsim as webpack.
<p>By the way, if anyone knows a workaround for any of my complaints, please
<br>let me know.
<p>Thanks,
<br>Theron Hicks
<p>>
<br>> addition to all of the Spartan II and IIE(?).
<br>>
<br>> <a href="http://www.xilinx.com/ise/products/webpack_config.htm">http://www.xilinx.com/ise/products/webpack_config.htm</a>
<br>>
<br>> Can anyone verify that these devices are actually supported and working
<br>> in the current release of Webpack?
<br>>
<br>> Also, it is clear that only a trial version of ModelSim is included
and
<br>> you need to buy the XE version if you want to do real work with the
<br>> simulator. Are there any other pieces included that are not fully
<br>> functional?
<br>>
<br>> Finally, the only supported OS listed are 98, 2000 and NT 4.0. Anyone
<br>> know if they plan to update this list with something more current
like
<br>> XP? I expect to be buying a new machine soon and hate to have to
use an
<br>> old OS just for Xilinx.
<br>>
<br>> --
<br>>
<br>> Rick "rickman" Collins
<br>>
<br>> rick.collins@XYarius.com
<br>> Ignore the reply address. To email me use the above address with
the XY
<br>> removed.
<br>>
<br>> Arius - A Signal Processing Solutions Company
<br>> Specializing in DSP and FPGA design&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
URL <a href="http://www.arius.com">http://www.arius.com</a>
<br>> 4 King Ave&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
301-682-7772 Voice
<br>> Frederick, MD 21701-3110&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
301-682-7666 FAX</blockquote>
</html>

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Article: 36977
Subject: Re: Got enough mebibytes of RAM ?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 27 Nov 2001 23:49:46 +0000
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> We all need a laugh now and then.
> This one is good for a serious smile, whatever that is.
>
> http://physics.nist.gov/cuu/Units/binary.html
>
> Peter Alfke

Priceless!

Do you happen to know if they're hiring ? Sounds like a nice relaxing
place to hunker down for the recession.




Article: 36978
Subject: Re: 'Timing' simulation in ModelSIM
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 27 Nov 2001 16:54:44 -0700
Links: << >>  << T >>  << A >>
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<Resending due to newsgroup server problems>


I agree with Rick on verifying functionality as your design has gone
through a
large transformation from your RTL to code to physical design however I
think
there are merits in debugging timing issues as well.  I can not tell you
how many
times I have seen designs in which timing problems were spotted in the
timing
simulation stage even when full timespecs were entered and fairly
thorough static
analysis was performed.  One fairly recent example of this is where a
designer
fully timespec'ed the design.  This included putting PERIOD constraints
on the
clocks, OFFSETs for the input and output paths and MAXDELAYs for
"special" paths.
The constraints looked good, covered most all of the relevant portions
of the
design and static timing analysis checked out however during a timing
simulation,
timing errors were seen.  How could this happen?  It turns out after a
little
investigation, that some of the timing paths that were supposed to be
covered by
the PERIOD constraint were over-ridden by a MAXDELAY.  Normally, this
would not be
a problem as the PERIOD constraint had the same value as the MAXDELAY
however in
this case, that path was going from a negative clocked register to a
positive
edged register and thus is half the period.  The constraint allowed too
much time
for that path.  This would certainly be overlooked by almost anyone
doing static
timing analysis however the simulation easily picked this up and
identified the
problem to the engineer.  To make matters worse, in situations like
this, the
design could work perfect in the lab even with timing violations however
once the
design heats up, you get a slightly slower part (but still in
specifications), or
some other slight variation, you could have some non-working boards. 
Many times
the part or possibly the board will be blamed but the reality is it is
missing
timing but since proper verification was not performed, this was never
identified.

Timing simulation is just another verification method and obviously is
not
required to get a design to work but certainly is a very good idea
none-the-less.
It is by no means a substitute for timespecs or static timing analysis
however
when used in conjunction with it, can better ensure a working, stable
design in
the end.  In my opinion, timing simulation is not too much added effort
if planned
for in the functional simulation stages of the design and well worth the
time
spent.  Timing simulation can sometimes easily identify things
overlooked in
static analysis (unconstrained paths, improperly constrained paths,
unforseen
occurances, etc.) or in the lab as my story attempts to illustrate.

I have heard people say timing simulation is not necessary and generally
a waste
of time however I certainly disagree with that and have seen several
cases to
contradict that. 

<stepping off soap-box now>


--  Brian



Rick Filipkiewicz wrote:

> Austin Franklin wrote:
>
> > > Hey there,
> > >     It seems I have another challange to overcome in attempting 'timing'
> > > simulations in ModelSIM.
> >
> > Kris,
> >
> > Why are you doing timing simulations in the first place?
> >
> > Austin
>
> Post P&R simulation is the only way to find NGDBUILD/MAP/PAR bugs [BITGEN bugs
> = you are basically stuffed]. Particularly in the early days of MX.Y there
> were a lot of issues with timing contraints. Even as recently as 2.1i you
> couldn't separate the 2 parts of a BlockRAM if they were on different clocks -
> lead to some interesting problems.
>
> Found a new 2.1iSP6 MAP bug just the other day when re-building an old release
> with the same toolset as the original build. Needed post PAR simulation to
> find it.
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Article: 36979
Subject: Re: Which vendor to choose
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Wed, 28 Nov 2001 11:26:51 +1100
Links: << >>  << T >>  << A >>
What is a CLB? configurable logic block? Is that the basic logic
cell with ram/flip-flop kind of thing?

Ray Andraka wrote:
> 
> It really depends on what your major applications are.  Altera has CAM built in,
> which is very nice to nice in those network and sorter applications, whilc
> xilinx's ability to use CLBs as small RAMs or shift registers is extremely
> valuable in DSP applications.  You need to carefully look at the features and
> architecture while thinking about how they will help or hurt your typical
> designs.
> 
> Jason Berringer wrote:
> 
> > Hello everyone,
> >
> > Since everyone here has more experience with FPGAs than I, I will ask for
> > some advice. Since I'm just starting with FPGAs it seems to me a good idea
> > to pick a vendor and stick to it (and this seems to be cheaper since you
> > don't have to purchase everyone's tools). I would like some comments on
> > which vendor is the "preferred" vendor these days. In other words why should
> > I choose Altera over Xilinx over Atmel, etc. I'm looking for honest answers
> > and no sales calls. My applications will vary in size and speed so
> > flexibility is very important, along with relative costs of software and
> > ICs/demonstration boards.
> >
> > I'm interested to know so I can save myself some head aches and make an
> > informed decision on which company to align myself with.

Article: 36980
Subject: Re: Creating a jitter free clock
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 28 Nov 2001 00:44:07 GMT
Links: << >>  << T >>  << A >>
On Tue, 27 Nov 2001 11:14:22 -0800, Austin Lesea
<austin.lesea@xilinx.com> wrote:

>Peter,
>
>The Color Burst frequency is supposed to be synchronized to a national standard, but it never was in the US.  It is synchronized in Europe.
>
>Thus, here in the US, we have a "free" good reference, that isn't traceable to anything.
>
>It has been replaced world - wide with GPS receivers that correct and update other oscillators.
>
>Most CMDA cellular basestations use GPS for their timebase.
>
>GPS with slective availability off (its present state) is +/- 10 nS at any given moment, but averaged over time is better than ~1E-13, or never worse than 100 nS from UTC, ever.

Is there a good reason for measuring time in nano siemens (nS - a
measure of conductance) instead of nano seconds (ns)?

I notice that all the Xilinx timing reports meaure time using units of
conductance as well.  I've never been quite sure of the conversion
factor...

;)

Allan.

Article: 36981
Subject: Re: Creating a jitter free clock
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 27 Nov 2001 17:02:01 -0800
Links: << >>  << T >>  << A >>
Allan,

After reading Peter's post on gibibytes (instead of gigabytes), I really have to be much more careful with my fingers, and with the shift key ......

Is the inverse of farads the daraf?  What about the inverse of henries?  is it uF and uH?  or uf and uh ....

Anyone out there have a convenient URL for a website to solve these distressing issues?

It was a far simpler time when 'hertz' were cycles per second....

Austin

Allan Herriman wrote:

> On Tue, 27 Nov 2001 11:14:22 -0800, Austin Lesea
> <austin.lesea@xilinx.com> wrote:
>
> >Peter,
> >
> >The Color Burst frequency is supposed to be synchronized to a national standard, but it never was in the US.  It is synchronized in Europe.
> >
> >Thus, here in the US, we have a "free" good reference, that isn't traceable to anything.
> >
> >It has been replaced world - wide with GPS receivers that correct and update other oscillators.
> >
> >Most CMDA cellular basestations use GPS for their timebase.
> >
> >GPS with slective availability off (its present state) is +/- 10 nS at any given moment, but averaged over time is better than ~1E-13, or never worse than 100 nS from UTC, ever.
>
> Is there a good reason for measuring time in nano siemens (nS - a
> measure of conductance) instead of nano seconds (ns)?
>
> I notice that all the Xilinx timing reports meaure time using units of
> conductance as well.  I've never been quite sure of the conversion
> factor...
>
> ;)
>
> Allan.


Article: 36982
Subject: Re: Device Support in Webpack
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 28 Nov 2001 01:07:28 GMT
Links: << >>  << T >>  << A >>
rickman wrote:

> I am aware of the ModelSim behavior. I did a project with it a little
> over a year ago and it got to be a real pain at 500 lines of code. It
> was not a gradual change in simulation time, but was about a 5x to 10x
> reduction in speed once you reached the 500 line limitation. This made
> it MUCH harder to get any real work done. Since it is not clearly
> indicated in the documentation, it snuck up behind me in the middle of
> this small project. Now I know better than to try to use any of the demo
> tools for a project, even when they look useful.

Rick:

The free ModelSim is a toy.  How can you expect otherwise when the
non-free version costs in four figures?  
 
> IIRC, logiblox lets you instantiate complex elements like counters,
> adders, bus muxes and the like, right? I am not familiar with coregen. I
> will read up on it at the Xilinx web site. FPGA editor is important. I
> take it there are no replacement modules for Logiblox and FPGA editor in
> WebPack? It would be a pain to work without these functions.

CoreGen and LogiBlox, methinks, are meta-libraries that are more useful
if your design-entry method is schematics.  LogiBlox is the "old stuff,"
CoreGen is the "new stuff."  It's neat in principle to be able to custom
configure a FIFO or a RAM with CoreGen.  However, I've found that I've
been able to get better results writing my own code.  Synplify and
Leonardo both handle RAM inference quite well, so there's no reason to
instantiate a library component.

And I'm of the opinion that some of the simulation models Xilinx provide
-- the CoreGen FIFO, for one -- are broken.  Search the archives of this
newsgroup, and of comp.lang.vhdl, for more of my bitching and moaning in
that regard.

--andy

PS: Why XP?

Article: 36983
Subject: Re: Simple Logic State Analyser
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Wed, 28 Nov 2001 01:14:30 GMT
Links: << >>  << T >>  << A >>
Gunther May wrote:
> 
> Hello,
> 
> I meant exactly what you call a timing logic analyser (I was not sure about
> the English word, sorry).
> It does not need to have an own display (this would probably get quickly
> very expensive); the possibility to load it up to a PC would be sufficient.
> Dos somebody have such a circuit/PLD software? You would make me a great
> favour!

A timing logic analyzer is fairly simple.  First, you need a sample
clock.  For this to be of any value, your sample rate oughta be as high
as you can stand -- otherwise, you may miss events that you're trying to
analyze.  On every rising edge of your sample clock, all of your inputs
are clocked into some sort of storage.  Of course, there has to be some
sort of mechanism to read the sample storage and display it, or transmit
it to a PC or some such for further display/analysis.

Of course, you also want some sort of intelligent triggering mechanism;
otherwise, you fill up your sample buffer with useless stuff. 
Triggering can be as simple as "look for an occurrence of pattern XYZ on
these data pins, and start storing until the buffer's full" to all sorts
of complex setups.  The more complex triggers can be VERY useful indeed.

Face it, it's an interesting lab project if you're doing a senior design
project for school, but give me an HP/Agilent logic analyzer, and I'll
get some work done!

-a

Article: 36984
Subject: Re: Creating a jitter free clock
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Wed, 28 Nov 2001 01:31:28 -0000
Links: << >>  << T >>  << A >>

"Austin Lesea" <austin.lesea@...inx.com> wrote
> Is the inverse of farads the daraf?  What about the inverse of henries?  is it
uF and uH?  or uf and uh ....

Indeed.  The Siemen replaced the mho, the inverse of you-know-what.






Article: 36985
Subject: Re: Creating a jitter free clock
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 28 Nov 2001 01:49:49 GMT
Links: << >>  << T >>  << A >>
On Tue, 27 Nov 2001 17:02:01 -0800, Austin Lesea
<austin.lesea@xilinx.com> wrote:

>Allan,
>
>After reading Peter's post on gibibytes (instead of gigabytes), I really have to be much more careful with my fingers, and with the shift key ......
>
>Is the inverse of farads the daraf?  What about the inverse of henries?  is it uF and uH?  or uf and uh ....
>
>Anyone out there have a convenient URL for a website to solve these distressing issues?

Here is the English translation of a document from Bureau
International des Poids et Mesures:
http://www.bipm.fr/pdf/si-brochure.pdf

Any chance of getting the Xilinx software to comply?

Regards,
Allan.

>It was a far simpler time when 'hertz' were cycles per second....
>
>Austin
>
>Allan Herriman wrote:
>
>> On Tue, 27 Nov 2001 11:14:22 -0800, Austin Lesea
>> <austin.lesea@xilinx.com> wrote:
>>
>> >Peter,
>> >
>> >The Color Burst frequency is supposed to be synchronized to a national standard, but it never was in the US.  It is synchronized in Europe.
>> >
>> >Thus, here in the US, we have a "free" good reference, that isn't traceable to anything.
>> >
>> >It has been replaced world - wide with GPS receivers that correct and update other oscillators.
>> >
>> >Most CMDA cellular basestations use GPS for their timebase.
>> >
>> >GPS with slective availability off (its present state) is +/- 10 nS at any given moment, but averaged over time is better than ~1E-13, or never worse than 100 nS from UTC, ever.
>>
>> Is there a good reason for measuring time in nano siemens (nS - a
>> measure of conductance) instead of nano seconds (ns)?
>>
>> I notice that all the Xilinx timing reports meaure time using units of
>> conductance as well.  I've never been quite sure of the conversion
>> factor...
>>
>> ;)
>>
>> Allan.
>


Article: 36986
Subject: Re: Which vendor to choose
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 27 Nov 2001 18:00:54 -0800
Links: << >>  << T >>  << A >>
CLB ( configurable Logic Block ) os a Xilinx-specific name for the basic block in the
FPGA fabric or matrix.
Depending on the device family this "molecule" has different numbers of
"atoms"=Look-Up-Tables and flip-flops.
In XC4000 and Spartan devices there are 2 LUTs and flip-flops per CLB.
In Spartan-II and Virtex there are four,
in Virtex-II there are eight.

That's why we also use ( and I prefer ) the name Logic Cell for a LUT+flip-flop.

A LUT is always a 4-input table = a 16-bit ROM, implementing any function of four
variables.
Only XILINX LUTs can also be used as 16-bit RAMs.

Modern FPGAs have additional goodies, like BlockRAMs, sophisticated clock management
( eliminating clock delays, multiplying, dividing, and phase-shifting the clock) and
many different I/O standards, including built-in termination.

Peter Alfke, Xilinx Applications
=======================================
Russell Shaw wrote:

> What is a CLB? configurable logic block? Is that the basic logic
> cell with ram/flip-flop kind of thing?
>
> Ray Andraka wrote:
> >
> > It really depends on what your major applications are.  Altera has CAM built in,
> > which is very nice to nice in those network and sorter applications, whilc
> > xilinx's ability to use CLBs as small RAMs or shift registers is extremely
> > valuable in DSP applications.  You need to carefully look at the features and
> > architecture while thinking about how they will help or hurt your typical
> > designs.
> >
> > Jason Berringer wrote:
> >
> > > Hello everyone,
> > >
> > > Since everyone here has more experience with FPGAs than I, I will ask for
> > > some advice. Since I'm just starting with FPGAs it seems to me a good idea
> > > to pick a vendor and stick to it (and this seems to be cheaper since you
> > > don't have to purchase everyone's tools). I would like some comments on
> > > which vendor is the "preferred" vendor these days. In other words why should
> > > I choose Altera over Xilinx over Atmel, etc. I'm looking for honest answers
> > > and no sales calls. My applications will vary in size and speed so
> > > flexibility is very important, along with relative costs of software and
> > > ICs/demonstration boards.
> > >
> > > I'm interested to know so I can save myself some head aches and make an
> > > informed decision on which company to align myself with.


Article: 36987
Subject: Re: Creating a jitter free clock
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 27 Nov 2001 18:49:29 -0800
Links: << >>  << T >>  << A >>
We must have come a long way, when the chief complaint about our software now boils down to our use of capital S for designating "second".  :-)
Obviously, we must have made great strides since the olden days when such complaints often used language not appropriate for delicate ears.

I call that progress with a capital P.

peter alfke




Article: 36988
Subject: What does a 'Slice' refer to in a Xilinx MAP report?
From: Kris Nichols <knichols@uoguelph.ca>
Date: Wed, 28 Nov 2001 02:52:34 GMT
Links: << >>  << T >>  << A >>
A Xilinx MAP report gives statistics regarding an implemented FPGA 
design, including the following:

-Number of Slices
-Number of Slice Flip Flops
-Number of 4 input LUTs
-Number of bonded IOBs
-Equivalent Gate count
-Additional JTAG gate count for IOBs

I understand most of these concepts, but what does a 'Slice' refer to? 
I've skimmed through most of the Xilinx literature on their website, but 
find no reference as to what a 'Slice' refers to.  Thanks in advance.

Kris Nichols


Article: 36989
Subject: Re: What does a 'Slice' refer to in a Xilinx MAP report?
From: "S. Ramirez" <sramirez@cfl.rr.com>
Date: Wed, 28 Nov 2001 03:32:29 GMT
Links: << >>  << T >>  << A >>
Kris,
     Skim this:
          http://www.xilinx.com/partinfo/ds031-2.pdf

     Go to page 12, Configurable Logic Blocks, where Slice Description along
with Figures 13, 14 will show you what a slice is.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA


"Kris Nichols" <knichols@uoguelph.ca> wrote in message
news:3C044F4D.5040805@uoguelph.ca...
> A Xilinx MAP report gives statistics regarding an implemented FPGA
> design, including the following:
>
> -Number of Slices
> -Number of Slice Flip Flops
> -Number of 4 input LUTs
> -Number of bonded IOBs
> -Equivalent Gate count
> -Additional JTAG gate count for IOBs
>
> I understand most of these concepts, but what does a 'Slice' refer to?
> I've skimmed through most of the Xilinx literature on their website, but
> find no reference as to what a 'Slice' refers to.  Thanks in advance.
>
> Kris Nichols
>
>



Article: 36990
Subject: reducing PAR time
From: khtsoi@cse.cuhk.edu.hk
Date: 28 Nov 2001 04:53:13 GMT
Links: << >>  << T >>  << A >>
Hi,

I have a design including many instances (say 100) of a regular
cell. The design is in form of VHDL codes. The cell use only
LUTs and FDs and all have RLOC attribute on them.

Can I find a way to reduce the place and route (par tools from
Xilinx) time by telling the par tools not to re-consider the
placement and routing in the identical cells? How?

Env: Synopsys Design Compiler & Xilinx Alliance 3.1i on SunOS

Thanks in advance!

---- Brittle

Article: 36991
Subject: Re: Alliance
From: "Srinivasan Venkataramanan" <srinivasan@siliconsystems.co.in>
Date: Wed, 28 Nov 2001 10:36:27 +0530
Links: << >>  << T >>  << A >>
Hi,
   Try at:

ftp://asim.lip6.fr/pub/alliance/distribution/4.0

Not sure if you can use it with Xilinx - as I haven't done that, but
why not try Webpack from Xilinx itself?

Good Luck,
Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"


"Fabio Bertone" <fabiobeta@libero.it> wrote in message
news:363d514c42eb46192e0000bbb36706e5.42588@mygate.mailgate.org...
> I'm searching information about this software. I suppose I can use
it to
> simulate Xilinx FPGA.
> How can I get it?(download?)
>
> Thanks
> Fabio
>
>
> --
> Posted from didlinux.polito.it [130.192.39.231]
> via Mailgate.ORG Server - http://www.Mailgate.ORG



Article: 36992
Subject: Re: What does a 'Slice' refer to in a Xilinx MAP report?
From: Peter Alfke <palfke@earthlink.net>
Date: Wed, 28 Nov 2001 05:08:59 GMT
Links: << >>  << T >>  << A >>
A slice is two LUTs + flip-flops. So it is, kind of, the equivalent of an
XC4000CLB.
The Virtex carry and clocking structure makes it meaningful to group about
two LUTs ( or two Logic Cells ) together, hence the slice.
But for bulk measurements of utilization, a slice is just two LUTs + 2
flip-flops.
"Slice flip-flops" would be a distinction from IOB flip-flops.

Peter Alfke
===============================
Kris Nichols wrote:

> A Xilinx MAP report gives statistics regarding an implemented FPGA
> design, including the following:
>
> -Number of Slices
> -Number of Slice Flip Flops
> -Number of 4 input LUTs
> -Number of bonded IOBs
> -Equivalent Gate count
> -Additional JTAG gate count for IOBs
>
> I understand most of these concepts, but what does a 'Slice' refer to?
> I've skimmed through most of the Xilinx literature on their website, but
> find no reference as to what a 'Slice' refers to.  Thanks in advance.
>
> Kris Nichols


Article: 36993
Subject: maximum output current on Spartan2
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 28 Nov 2001 05:12:22 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm looking for the maximum current I can draw from a Spartan2 output
(LVTTL mode) without impairing reliability.  I'm only interested in
sourcing current (i.e. from the P channel strong pullup).

I found Xilinx Answer 4453:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=4453
that says that the figure is 20mA for 4000E/XL devices, based on metal
migration.

I couldn't find any figures for Spartan2 though.

My next question: how does this scale with the selected I/O standard?
E.g. if an LVTTL24 output has an absolute maximum current of 'X' mA,
will an LVTTL12 output have an absolute maximum current of 'X' mA, or
'X'/2 mA?
I guess it depends on which bits of metalization are the 'critial
path'.

Thanks,
Allan.

Article: 36994
Subject: Re: an unespected clock
From: Fabian <Fabian.Meister@colorsystems.de>
Date: Wed, 28 Nov 2001 00:43:37 -0800
Links: << >>  << T >>  << A >>
You have applied a clock constraint (global clock constraint) to the unregistered logic. Therefore, a system clock was added to your log file. If you need more specific information contact your local Synplicity Sales representative.  They have a nice Quick Start Guide released for their SynplifyPro software which explains the most important stuff on how to use the tool on a few pages.

Article: 36995
Subject: What is a difference?
From: "Tomasz Brychcy" <T.Brychcy@ime.pz.zgora.pl>
Date: Wed, 28 Nov 2001 09:48:39 +0100
Links: << >>  << T >>  << A >>
Hello,

What is a difference between: digital IC design and digital logic design?

Tomek



Article: 36996
Subject: Re: What is a difference?
From: muzaffer@kal.st
Date: Wed, 28 Nov 2001 09:25:43 GMT
Links: << >>  << T >>  << A >>
On Wed, 28 Nov 2001 09:48:39 +0100, "Tomasz Brychcy"
<T.Brychcy@ime.pz.zgora.pl> wrote:

>Hello,
>
>What is a difference between: digital IC design and digital logic design?
>
>Tomek
>

digital logic design is part of what goes into a digital IC. To do a
digital IC you first design the logic, then you synthesize, do static
timing analysis, redo the logic if you don't meet timing, P&R,
backannotate, do some more logic, add scan etc etc till you get a GDS
II at which point you can claim to have a digital IC.
hope this helps.


Muzaffer Kal

http://www.dspia.com
DSP algorithm implementations for FPGA systems

Article: 36997
Subject: Re: Creating a jitter free clock
From: adrian <>
Date: Wed, 28 Nov 2001 03:50:48 -0800
Links: << >>  << T >>  << A >>
I'll tell you exactly what I need it for. I have designed an FPGA based Pulsar timer for a radio astronomy observatory. What the instrument essentially does is coherent averaging on pulses coming from neutron stars (pulsars)to build up a pulse profile. Averaging, right now, will take place over a maximum of 5 minutes, although this will probably be much less in the future. 

I need to be able to set a user defined sampling frequency to this resolution, and not have at move at all. If it does, it means that the pulse will being to drift across the averaged profile, and move around with jitter.

adrian

Article: 36998
Subject: Re: Creating a jitter free clock
From: adrian <>
Date: Wed, 28 Nov 2001 03:52:58 -0800
Links: << >>  << T >>  << A >>
Hi,

Forgot to mention, the system does have access to a 1pps hydrogen MASER. 

adrian

Article: 36999
Subject: Is there a full open-source synthesis path for any FPGA?
From: Kees van Reeuwijk <C.vanReeuwijk@twi.tudelft.nl>
Date: Wed, 28 Nov 2001 13:18:10 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm looking for an open-source implementation of the entire synthesis
path for an FPGA, in particular placement, routing, and generation of a
configuration file for the FPGA. Any pointers to such software would be
greatly appreciated.

Alternatively:

I understand that the scarcity of such software is partly because
vendors do not release enough information. Are there any modern devices
for which this information *is* available? IOW, if I wanted to implement
an open-source synthesis tool, which devices should I target? Again,
recommendations would be greatly appreciated.



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