Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 37325

Article: 37325
Subject: Re: Webpack Version 3: Exit with error code 0002
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 6 Dec 2001 23:02:45 -0800
Links: << >>  << T >>  << A >>
Although I do realize that I am not directly answering your question,
why not upgrade to the latest ISE WebPack 4.1?
I find it better than the older ISE WebPack 3.x.
If you don't want to download 130MB of files, you can go to this
website to order a free CD (actually CD-R) that contains ISE WebPack
4.1.

http://208.129.228.206/solutions/kits/xilinx/webpack/


I received the CD through USPS First-Class mail, but because I already
downloaded files totaling 130MB with a 56K modem (I did it while I was
sleeping), I haven't made sure the CD really has ISE WebPack 4.1.
Although the invoice I got said ISE WebPack 4.1, so I guess it has ISE
WebPack 4.1.
Again, it was totally free.




Kevin Brace (don't respond to me directly, respond within the
newsgroup)



Brinda <brinda@glue.umd.edu> wrote in message news:<ee73873.-1@WebX.sUN8CHnE>...
> Hi
> 
> I am trying to synthesise a simple receiver module. But I always get the error as above done: failed with exit code 0002.
> It says that the module is correct for synthesis - extracts several signals before failing.
> Can someone tell me what this means
> please
> Brinda

Article: 37326
Subject: Re: where is designed FPGA for apple II computer...?
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Fri, 7 Dec 2001 07:03:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3C105206.7DC3C9A5@andraka.com>,
Ray Andraka  <ray@andraka.com> wrote:
>Oops, that should have read "...and _microprocessor_ designs that are
>specifically...".  We routinely do other designs well beyond 100 MHz.
>Microprocessors can be a challenge at the high rates because there is
>limited opportunity for deep pipelining.

Until you decide "screw it" and go multithreaded.  2 or 4 threads is a
nice number.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 37327
Subject: Re: URL for ordering Xilinx ise webpack 4.1i cdrom
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 6 Dec 2001 23:08:28 -0800
Links: << >>  << T >>  << A >>
Try this website.

http://208.129.228.206/solutions/kits/xilinx/webpack/


I got one from Insight Electronics, but I already downloaded it from
Xilinx (downloaded files totaling 130MB with a 56K modem), so I
haven't made sure the CD (actually CD-R) really has ISE WebPack 4.1.
The invoice says I got ISE WebPack 4.1 CD, so I guess it has ISE
WebPack 4.1.
The thing was totally free.
They will send it through USPS First-Class Mail.



Kevin Brace (don't respond to me directly, respond within the
newsgroup)




"David Feustel" <dfeustel@mindspring.com> wrote in message news:<i9QM7.184582$My2.108866220@news1.mntp1.il.home.com>...
> Is there a URL or phone number for ordering the
> Xilinx ISE 4.1i webpack on cdrom?
> 
> Thanks.

Article: 37328
Subject: Re: How to increase clock skew for Spartan-II
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 6 Dec 2001 23:33:41 -0800
Links: << >>  << T >>  << A >>
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<9uj083$8mq25$1@ID-84877.news.dfncis.de>...
> "Kevin Brace" <kevinbraceusenet@hotmail.com> schrieb im Newsbeitrag
> news:cc7b0b5f.0112032335.34c890b5@posting.google.com...
> > I will like to know if there is a way to increase clock skew by about
> > 1.0 ns through a .UCF file (User Constraint File).
> > I am having problems meeting Tsu (setup time), and adding 1.0ns of
> > clock skew won't totally solve my problem, but it will help.
> > I will like to add the clock skew through a .UCF file because the HDL
> > code has to be portable across different FPGA vendors (mainly Xilinx
> > and Altera).
> > The device I am using is Xilinx Spartan-II 150K system gate part
> > (XC2S150-5), and the software I am using is Xilinx ISE WebPack 4.1.
> 
> Iam curious about INCREASING clock skew. Usually you use a DLL to REMOVE
> clock skew, dont you ?. Do you use the IOB FFs ?? Without DELAY active? What
> frequency are you running? Can you switch to a higher speed grade?


I know it sounds strange because most people don't want clock skew at
all.
However, in my case, I already constrained the output and tri-state
control FFs inside IOBs, so Tco (Tval in PCI) is no longer an issue.
I am working on a PCI IP core, and because I finally figured out the
way to constrain output and tri-state control FFs into IOBs, I now
have more margin to increase clock skew, and still meet Tco (Tval).
Currently, the worst Tval I got is about 9.9 ns (actually 9.831ns),
and 33MHz PCI's Tval is 11ns, so I can still increase the clock skew
by 1.1ns, and still be safe to meet Tval.
The problem I am having is that it is very hard to meet 33MHz PCI's
Tsu < 7ns, and even if I count the normal clock skew (about 2.3ns to
2.5ns for Spartan-II 150K gate speed grade -5) as part of Tsu, the Tsu
is 9.3ns, but the worst Tsu I got is about 10.9ns (8.6ns + 2.3ns).
Of course, adding 1.1ns of clock skew will still not solve the problem
completely (will still violate the timings by 0.5ns), but will help.
        IOB delay is active for all IOB input FFs, but I will like to
know if I can do so for the clock pin from a .UCF file.
I have a requirement where I cannot do any kind of vendor specific
stuff in the HDL files.
However, I don't mind what is inside a .UCD file.
The maximum clock of the design is about 50MHz, but I don't believe
that is an issue now.
        Using a faster speed grade (XC2S150-6C) will likely solve my
problem without adding more clock skew (in my case, if I floorplanned
the LUTs), but I already own a PCI card that has Xilinx Spartan-II
150K system gate part speed grade -5 (XC2S150-5CPQ208), so I really
want to meet timings with speed grade -5.
By the way, with speed grade -5, I already floorplanned it, and
floorplanning helped a lot, but I still fall short by 1.5ns.
I know that the card will still run okay without meeting timings (that
is how I tested my PCI IP core, and worked fine without lockups), but
I don't want to violate the PCI specification.
A lot of companies violates the PCI specification, but I don't want to
do so.




Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 37329
Subject: Re: How to increase clock skew for Spartan-II
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 6 Dec 2001 23:36:43 -0800
Links: << >>  << T >>  << A >>
hamish@cloud.net.au wrote in message news:<3c0cb4ce$0$21612$afc38c87@news.optusnet.com.au>...
> Kevin Brace <kevinbraceusenet@hotmail.com> wrote:
> > I will like to know if there is a way to increase clock skew by about
> > 1.0 ns through a .UCF file (User Constraint File).
> > I am having problems meeting Tsu (setup time), and adding 1.0ns of
> > clock skew won't totally solve my problem, but it will help.
> > I will like to add the clock skew through a .UCF file because the HDL
> > code has to be portable across different FPGA vendors (mainly Xilinx
> > and Altera).
> > The device I am using is Xilinx Spartan-II 150K system gate part
> > (XC2S150-5), and the software I am using is Xilinx ISE WebPack 4.1.
> 
> Clock skew figures quoted by TRCE/Timing Analyzer are only maximum
> values anyway -- the actual skew in the real silicon could be
> anything from that value down to zero (perhaps even negative).
> So even if you could add that skew, it would only add to the
> maximum, not necessarily the actual.
> 
> You could daisy chain the global buffers or something like that.
> You could use the phase shift if you had a Virtex-II.
> 
> Hamish


        Would there always be clock skew no matter what?
How would I daisy chain the global buffers outside of HDL files (like .UCF file)?
I know that from a .UCF file, I can add IOBDELAY for IOB input FFs.
Can I do so for clock pins?



Kevin Brace (don't respond to me directly, respond within the newsgroup)

Article: 37330
Subject: Re: quartus post simulation setup problem
From: asherm@asherm.com (Asher C. Martin)
Date: 6 Dec 2001 23:49:53 -0800
Links: << >>  << T >>  << A >>
nchrysos@ics.forth.gr (Nick) wrote in message news:<d0131214.0112060913.27c9410e@posting.google.com>...
> Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3C0EB1F6.160D02BC@flukenetworks.com>...
> 
> 
> Well thanks...the Quartus II could be a solution but i cannot get it
> this software...
> 
> anyway I did not have a clear answer about the problem ,since it
> appears
> regardless of the clock frequency that i use. 
> 
> What kind of setup violation is this?
> 
> Is there anything that i can do?
> I only use the positive edge(changed it),  the problem is on internal
> register ( no pins involved), it involves clock enable signals, it
> involves two clock domains that are synchronized 2x ( no phase
> difference).
> The simulation problem appears also on the APEX, as far as i can see
> from the logical  analyzer.
> thanks for your interest..
> Nick

Hi Nick,

Your best bet is to use Quartus II 1.1 timing.  If you run your design
in quartus you can get an FMAX for your critical path and the delay
times for each of the other paths.  If you have a timing violation it
will highlight the path in red and then you can optomize your design
for this path.

Typically Quartus timing should be the most accurate... 

You can also create a netlist or .vo file and .sdo file and then
simulate your design using this with Verilog-xl or modelsim.  The
timing violations will also show up there if you have any.

Take care,
>Asher<

Article: 37331
Subject: Re: Has anyone successfully used opencores PCI?
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 07 Dec 2001 09:39:33 +0100
Links: << >>  << T >>  << A >>
"Sul Weh" <sweather1999@yahoo.com> writes:

> Also, why would one choose to use opencores instead of the Xilinx logicore
> PCI?

Maybe you're prototyping using an FPGA, but might implement it using
an ASIC in which it might be very difficult to use the Xilinx core.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 37332
Subject: Re: where is designed FPGA for apple II computer...?
From: seilebost@aol.com (olivier JEAN)
Date: 7 Dec 2001 00:49:57 -0800
Links: << >>  << T >>  << A >>
Hi everybody.

 It exists two FPGA design about 6502.
 + FREE-IP :  http://www.free-ip.com/6502/index.html
 + BIRD COMPUTER : http://www.birdcomputer.ca/bc6502_page.html ( to
see previous message).
 But the BCD operation is not implemented.

 I'm interesting by an 6502 build-in FPGA. Because I design a 80's
retro-computer, ORIC ATMOS. It has used an 6502.
 My site about the retro computer is : passionoric.ifrance.com


     Best Regard.

            OlivieR.





Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3C0FE654.3DDD7829@xilinx.com>...
> Caution,
> 
> We once programmed an Apple II on an FPGA perhaps seven years ago.
> 
> It ran far, far, too fast.
> 
> The disk interface is done in software, so all of the timing was off.
> Everything worked fine, but it couldn't talk to the disk drives.
> 
> Austin
> 
> 
> Kiyoung SON wrote:
> 
> > designed FPGA for Apple II computer...
> > I want it...

Article: 37333
Subject: Parameters deciding Max. Clock Frequency supported in a Sequential Ckt
From: anand_rectian@yahoo.co.in (Anand Kumar V)
Date: 7 Dec 2001 02:56:20 -0800
Links: << >>  << T >>  << A >>
What are all the factors that determine the maximum fequency(clock) of
operation in a Sequential Ckt that has many flipflops connected in
cascade ?...

      f (max) = 1 /  ( ? + ? + ?....)    (I need the expression)

  I know that set up time, hold time and clock to output delay affect
the max. frequency of operation. what r all the other parameters ??
  Iam not sure about the relationship between them. Given the
parameters , how will u calculate the max. frequency ???.
  Does the HOLD Time play any role in calculating the max. Clock
frequency ?

    These are few qns residing in my mind for a long time. Suggest me
some books which deal with Digital design techniques for sequential
Circuits along with clock timing analysis. Forward the links for any
good article available.
 
 Regards,
 Anand.

Article: 37334
Subject: Re: XC6200
From: Reinoud <dus@wanabe.nl>
Date: Fri, 07 Dec 2001 11:35:38 GMT
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> The unique aspect of the XC6200 was that it tolerated any "garbage" bitstream,
> since there was no possibility of contention.
> No other FPGA has that feature.

The MPGA has that.  It's cheap and readily available, too :-).

    http://ce.et.tudelft.nl/~reinoud/mpga/README.html

Also, for the next version a fast FF state save and restore feature
is planned, which is especially useful for reconfigurable computing.

- Reinoud

(Spam goes to wanabe, mail to wanadoo.)

Article: 37335
Subject: IP Updates and Modelsim
From: "Simon Deeley" <deeleys@cf.ac.uk>
Date: Fri, 7 Dec 2001 12:37:45 -0000
Links: << >>  << T >>  << A >>
Hi all,
I just installed the IP update and got a new synchronous fifo thingy v3 (v2
before) but when I try to simulate it using model sim, the compiler can't
find the files it needs:

# -- Loading entity fifo
# ERROR: Could not find
c:/Modeltech_xe/win32xoem/../xilinx/vhdl/xilinxcorelib.sync_fifo_v3_0
# ERROR: fifo.vhd(56): cannot find expanded name:
xilinxcorelib.sync_fifo_v3_0
# ERROR: fifo.vhd(57): xilinxcorelib is not an entity.
# ERROR: fifo.vhd(74): Error in configuration specification.  Expected
entity aspect.
# ERROR: fifo.vhd(87): VHDL Compiler exiting
# ERROR: c:/Modeltech_xe/win32xoem/vcom failed.
# Error in macro ./fifo_tb.fdo line 6
# c:/Modeltech_xe/win32xoem/vcom failed.
#     while executing
# "vcom -skip e -93 -explicit   fifo.vhd"

I go to the directory its looking in - there is stuff for previous versions
but not for the IP I have updated - does anyone know where I can find
updates for the modelsim libraries?

Thanks



Article: 37336
Subject: Translating....
From: "Giggio" <giggio@ciacca.com>
Date: Fri, 7 Dec 2001 14:25:56 +0100
Links: << >>  << T >>  << A >>
Hello!
Im a student of electronic engineering and im working with Xilinx ISE 4
for the first time...
..I need to translate from C to VHDL a program that I did...
but i have some problems.
I have a Matrix  A:4X4 (for example) I stored its values in a Dual Port
Memory Block (16 bit integer with 2-complement).
Now i have to take this values to make the following cycles:

for(i=0;i<=n-1;i++)
{
    for(j=i;j<=n-1;j++)
    {
          for (sum=a[i][j] , k=i-1 ; k>=0;k--) sum -= a[i][k]*a[j][k];
           if (i==j) {a[i][i]=sqrt(sum) ; } else a[j][i]=sum/a[i][i];
    }
}

but Im not able to create a VHDL (or a schematic) that does it.
Someone can help me?
Remeber that values are read form the DPMB with just one index!
I think that a multiplier and an accumulator will be used, but thats all!..
(the BIG problem is the line with     "for (sum.......)"
Thanks for your attention...
Luigi.




Article: 37337
Subject: RE: IP Updates and Modelsim
From: #BASUKI ENDAH PRIYANTO# <PH892987@ntu.edu.sg>
Date: Fri, 7 Dec 2001 21:32:36 +0800
Links: << >>  << T >>  << A >>
Hi Simon,

Download xilinx_lib.tcl from xilinx webpage.
then, run the tcl script in your modelsim s/w.

Basically, it will updates the new ip to your modelsim library.

You can email me directly, if you can not find the script at xilinx
webpage.

Regards,

Basuki

:-----Original Message-----
:From: Simon Deeley [mailto:deeleys@cf.ac.uk]
:Posted At: Friday, 07 December, 2001 8:38 PM
:Posted To: fpga
:Conversation: IP Updates and Modelsim
:Subject: IP Updates and Modelsim
:
:
:Hi all,
:I just installed the IP update and got a new synchronous fifo 
:thingy v3 (v2
:before) but when I try to simulate it using model sim, the 
:compiler can't
:find the files it needs:
:
:# -- Loading entity fifo
:# ERROR: Could not find
:c:/Modeltech_xe/win32xoem/../xilinx/vhdl/xilinxcorelib.sync_fifo_v3_0
:# ERROR: fifo.vhd(56): cannot find expanded name:
:xilinxcorelib.sync_fifo_v3_0
:# ERROR: fifo.vhd(57): xilinxcorelib is not an entity.
:# ERROR: fifo.vhd(74): Error in configuration specification.  Expected
:entity aspect.
:# ERROR: fifo.vhd(87): VHDL Compiler exiting
:# ERROR: c:/Modeltech_xe/win32xoem/vcom failed.
:# Error in macro ./fifo_tb.fdo line 6
:# c:/Modeltech_xe/win32xoem/vcom failed.
:#     while executing
:# "vcom -skip e -93 -explicit   fifo.vhd"
:
:I go to the directory its looking in - there is stuff for 
:previous versions
:but not for the IP I have updated - does anyone know where I can find
:updates for the modelsim libraries?
:
:Thanks
:
:


Article: 37338
Subject: Re: xilinx ise 4.1i
From: jacky Renaux <renaux.jacky@wanadoo.fr>
Date: 07 Dec 2001 13:38:09 GMT
Links: << >>  << T >>  << A >>

HI 

Just click on edif , you will get more to select including vhdl ...

hope it will help 
jacky

-- 
Use our news server 'news.foorum.com' from anywhere.
More details at: http://nnrpinfo.go.foorum.com/

Article: 37339
Subject: Re: What do you like/dislike about place and route tools?
From: "Pallek, Andrew [CAR:CN34:EXCH]" <apallek@americasm01.nt.com>
Date: Fri, 07 Dec 2001 09:17:29 -0500
Links: << >>  << T >>  << A >>
     Another Beef about Lattice tools is that sometimes they output
truncated .jed files when fitting on UNIX platforms.  You think everything
fit fine, but your programming file is only about 1/8 of the size it needs
to be to be valid, and downloadable.   Spitting out useless junk is not a
desireable feature unless you need a quasi-random number generator, which
was not what I was hoping for.  I haven't seen this problem on the PC
platform.  And you think that the place and route would be doing the same
thing on both platforms.  Apparently not.



Article: 37340
Subject: Re: quartus post simulation setup problem
From: nchrysos@ics.forth.gr (Nick)
Date: 7 Dec 2001 07:40:06 -0800
Links: << >>  << T >>  << A >>
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3C0FCA81.A9C22B37@flukenetworks.com>...
> Nick wrote:
> 
> > I am using 2 clocks. Both are global, and this path actual uses both
> > clocks.
> > The second clock is derived from the first ( twice period)
> > always @(posedge clk) s_clk = ~s_clk;
> > 
> > > > Are you (Nick) clocking on both edges of the clock?
> > >
> > > I hope not.
> > >
> > 
> > Yes i do in one circumstance, is this so bad...? What i wanted to do
> > is to provide a state like the following
> > clk  101
> > s_clk
> 
> Your choices are:
> 1. Redo your design and timing analysis
> along the lines of Brian's suggestions
> to correct the correct the clock skew
> you introduce by using two clocks.
> 
> 2. Redo your design with a single clock
> on a global line so you can use a simple
> register to register static timing analysis.
> 
> 
>             --Mike Treseler


I followed the single clock suggestion of Brian  and it works fine,
Well thanks to both,
Anyway i have to say that besides this problem -- which needed some
expertise that i lack,  Quartus is a very strange software, for
instance in the beginning of this project, i had to replace all the
dff x(output,input,clk) instances in my project with the completly
equavelant
always @(posedge clk) output = input;
to stop getting clock stuck at ground messages...
I hope QII is better (and faster!)

Article: 37341
Subject: Altera pin drivers
From: "Andrea Sabatini" <sabatini@nergal.it>
Date: Fri, 7 Dec 2001 16:48:41 +0100
Links: << >>  << T >>  << A >>
hi all,

i'm designing an fpga usign altera max-plus and/or quartusII (we still
haven't decided which one) and i have a question about it. does anybody
knows if these softwares automatically place IO buffers? or do i have to
insert them manually at my top level? it's obvious that i have to put manage
the bidir pin direction, but what about those ones whose direction is fixed?

thanks

andrea



Article: 37342
Subject: Re: Synplify to Actel clkbuf problems
From: Gerald Weile <Gerald.Weile@web.de>
Date: Fri, 07 Dec 2001 16:53:41 +0100
Links: << >>  << T >>  << A >>
Tony Nelson wrote:
> 
> Hi,
> 
> I'm synthesizing a design in Synplify with no pin constraints, then
> importing that edif into the Actel tools for PAR.  When I import a pin
> constraint file into the Actel tools, it gives an error, because it
> assigned a clock to an Actel HCLKBUF instead of a CLKBUF, which is
> what that pin provides.  Are there any Synplify constraints that force
> a specific signal to be a CLKBUF?  In Leonardo Spectrum this is quite
> easy:
> 
> set_attribute .work.controller.struct.clk_15MHZ -name PAD -value
> CLKBUF -port
> 
> Are there any comparable Synplify attributes to do the same thing?
> 
> Thanks,
> Tony Nelson


I think you will have to instanciate the CLKBUF manually:
------
library a54sxa;
    use a54sxa.all;
...
  component clkbuf
    port ( pad  : in std_logic; y : out std_logic );
  end component;
...
    hc : clkbuf port map ( pad => clk_pad, y => clk_intern );
------

Maybe you can avoid that if you try the "syn_noclockbuf" and 
"alspin" attributes. (I have not used those myself so far.)
Look at the Synplify reference manual for details...
------
  attribute syn_noclockbuf of wrong_clk : signal is true;
  attribute alspin         of CLK       : signal is "82"
------

MfG,
Gerald
-- 
    ---------------------------------------------------
    Gerald Weile     mailto:GWE@msc-ge.com 
MSC Vertriebs GmbH    Phone:+49-7249-910-186  Fax: -268
    ASIC Design        http://www.msc-ge.com

Article: 37343
Subject: Re: How to increase clock skew for Spartan-II
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 7 Dec 2001 17:37:13 +0100
Links: << >>  << T >>  << A >>
"Kevin Brace" <kevinbraceusenet@hotmail.com> schrieb im Newsbeitrag
news:cc7b0b5f.0112062333.5f67d298@posting.google.com...

[  PCI-Core inst meeting spec yet ]

Again, I wouldnt fool around with additional skew in the clock tree. I would
rather go an look if there are optimizations possible within the logic. You
already mentioned (and did) flooplannig. Try to register your internal
signals as much as possible, try to use priority encoded logic. Set the
output buffers to FAST slew rate and 12mA.
At least, you are not the first one who develops an PCI core for Spartan-II,
other did this before successful, so it can be done.

--
MfG
Falk





Article: 37344
Subject: Re: Parameters deciding Max. Clock Frequency supported in a Sequential Ckt
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 7 Dec 2001 17:40:48 +0100
Links: << >>  << T >>  << A >>
"Anand Kumar V" <anand_rectian@yahoo.co.in> schrieb im Newsbeitrag
news:8525036.0112070256.69272c6a@posting.google.com...
> What are all the factors that determine the maximum fequency(clock) of
> operation in a Sequential Ckt that has many flipflops connected in
> cascade ?...
>
>       f (max) = 1 /  ( ? + ? + ?....)    (I need the expression)

Within one clock period, 4 main things take their time

clock_2_output
logic delay
routing delay
setup time

the sum of these 4 basic timing parameters give you the minimum clock
period. But when there is clock skew involved, thing change.
--
MfG
Falk





Article: 37345
Subject: Re: Translating....
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 7 Dec 2001 17:57:31 +0100
Links: << >>  << T >>  << A >>
"Giggio" <giggio@ciacca.com> schrieb im Newsbeitrag
news:9uqg2v$otd$1@nets3.rz.RWTH-Aachen.DE...
> Hello!
> Im a student of electronic engineering and im working with Xilinx ISE 4
> for the first time...
> ..I need to translate from C to VHDL a program that I did...
> but i have some problems.
> I have a Matrix  A:4X4 (for example) I stored its values in a Dual Port
> Memory Block (16 bit integer with 2-complement).
> Now i have to take this values to make the following cycles:
>
> for(i=0;i<=n-1;i++)
> {
>     for(j=i;j<=n-1;j++)
>     {
>           for (sum=a[i][j] , k=i-1 ; k>=0;k--) sum -= a[i][k]*a[j][k];
>            if (i==j) {a[i][i]=sqrt(sum) ; } else a[j][i]=sum/a[i][i];
>     }
> }

Looks like you need 3 counters to do the looping. To address the values
inside the DP-RAM, you dont need a "real" multiplier" since the array is
4x4, which is a power of 2. simple bitshifting will do the stuff.
Furthermore you need a small FSM to control the calculation, loading of the
counters etc.
inside the 3 loop (k is the index) you need 2 cycles to read a[i][k] and
a[j][k]
To get rid of the summing problem, try to write down the single steps that
the cpu will do when executing the C-code (I know, it will be assembler, but
you know what I mean)

read a[i][j]
store it into sum
load k with i-1

loop starts
  load a[i][k]
  load a[j][k]
  muliply both
  add result to summ
loop end, decrease k, check if greater or equal zero

now you see, you need the RAM, a multiplier, registers for a[i][k], a[j][k],
an accumulator etc.
for all these components, you need control signals, generated by the FSM.
now try to convert this into a state machine

--
MfG
Falk




Article: 37346
Subject: Re: Altera pin drivers
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 7 Dec 2001 17:59:56 +0100
Links: << >>  << T >>  << A >>
"Andrea Sabatini" <sabatini@nergal.it> schrieb im Newsbeitrag
news:9uqo7c$2jko$1@newsreader1.mclink.it...
> hi all,
>
> i'm designing an fpga usign altera max-plus and/or quartusII (we still
> haven't decided which one) and i have a question about it. does anybody

I suggest to drop MAx-plus as fast as possible, because it is a real pain to
work with.

> knows if these softwares automatically place IO buffers? or do i have to

For Max-plus, Yes. For Quartus, I dont know, but guess it does.

--
MfG
Falk







Article: 37347
Subject: Re: How to increase clock skew for Spartan-II
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Fri, 07 Dec 2001 09:37:16 -0800
Links: << >>  << T >>  << A >>

Hello,

> Currently, the worst Tval I got is about 9.9 ns (actually 9.831ns),
> and 33MHz PCI's Tval is 11ns, so I can still increase the clock skew
> by 1.1ns, and still be safe to meet Tval.
> 
> The problem I am having is that it is very hard to meet 33MHz PCI's
> Tsu < 7ns, and even if I count the normal clock skew (about 2.3ns to
> 2.5ns for Spartan-II 150K gate speed grade -5) as part of Tsu, the Tsu
> is 9.3ns, but the worst Tsu I got is about 10.9ns (8.6ns + 2.3ns).
> Of course, adding 1.1ns of clock skew will still not solve the problem
> completely (will still violate the timings by 0.5ns), but will help.

I understand exactly what you are trying to do.  However, there are
some dangers in it.  If you were to increase the clock distribution
delay, you would be able to rob the clock to out to pay setup.  There
are ways to do this -- but for the most part, you will be using vendor
specific constructs in your HDL.

What you have not considered is the effect on the IOB input flip flops
that you are using with the DELAY enabled.  These DELAY elements are
designed to guarantee zero hold time in the IOB input flip flops.  In
essence, these delay buffers are matched to the global clock
distribution
delay.  There is a way around this, too -- build your own delay buffers
out of LUTs (generally frowned upon) -- but again, you will be using
vendor specific constructs in your HDL.

If you were to increase the global clock distribution delay without
increasing the delay through the input buffers (which you cannot do)
you will "void" your warranty of zero hold at these inputs, which is
also a requirement of the PCI specification.

Eric

Article: 37348
Subject: Re: For Sale: Huge Xilinx FPGA lots
From: "Keith" <keith@sc-solutions.co.uk>
Date: Fri, 7 Dec 2001 19:16:07 -0000
Links: << >>  << T >>  << A >>
Robert Posey wrote in message <3C1003CA.B092E573@raytheon.com>...
>Ditto, without the part numbers there isn't a way to tell if they would be
>usable.


The part numbers (and qty of each) are on the e-bay page.

They are various 3000 and 4000 series chips.

Probably not suited for new commercial designs
but okay for hobbyists if they are PLCC (which I cannot see from the pics).

Hobbyists probably won't want that many (I don't),
I'd consider buying the batch and selling them individually to individual
hobbyists
as they found a need for some.

I have not seen them on sale widely, though my 1999 Farnell catalogue
shows a few Atmel clones of some Xilinx 4000 series chips.

Is it hard to get these parts in small qty?

I think the auction time expires in the next few hours or so.




Article: 37349
Subject: Re: For Sale: Huge Xilinx FPGA lots
From: Arthur <>
Date: Fri, 7 Dec 2001 11:27:17 -0800
Links: << >>  << T >>  << A >>
I'd be wary of this -
1.  who knows what precautions were taken when the parts were removed from the board
2. current Xilinx software doesn't support these devices



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search