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Messages from 37400

Article: 37400
Subject: Re: ISA syncronization?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 10 Dec 2001 00:46:11 -0500
Links: << >>  << T >>  << A >>
Jason,

I recommend , like the others, that you use an async interface. But you
may need to sync the control input signals to your FSM. If there is a
chance that a FF can go metastable and interfere with the FSM operation,
you will need to add some circuitry to deal with this. 


Jason Berringer wrote:
> 
> Hello all,
> 
> Another novice question here that I would appreciate some help with. I'm
> writing the code for a simple ISA interface, simple being that this card is
> only going to interrupt the processor (at 1kHz) and place 16 bit data blocks
> on the bus when the address is decoded. My question is about syncronization.
> Do I need to syncronize to the bclk pin on the ISA bus or should I bring
> that clock into my 100MHz clock domain to syncronize to that? Or is
> syncronization even necessary on the ISA bus. In all of the limited
> documentation that I have found on the ISA bus it isn't very specific.
> 
> I would appreciate if anyone has more specific technical documentation on
> the bus if they could email me a copy or a snippit of some code verified
> would be great. No one seems to care about the ISA bus anymore, it's all PCI
> but we are using PC/104 gear in our designs and therefore are at present
> using the ISA bus.
> 
> A follow up question is; is it better to design using a finite state machine
> approach for the ISA bus, or because mine is a scaled down version, is it
> necessary? I have done a quick VHDL design but it at present does not
> include any syncronization.
> 
> Thanks for the help
> 
> Jason

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 37401
Subject: Michelangelo's Counter
From: cappellainfuocata@yahoo.it (Banana)
Date: 9 Dec 2001 23:33:29 -0800
Links: << >>  << T >>  << A >>
Good Morning 
with this counter/divider modulo 3 I can reach 162.4 MHz 
on a Xilinx XCV1000 BG560 -4 but I need 165MHz, can you 
help me to reach this scope just changing the code or inserting 
some right constrain on Synplify Pro 7.02 or Xilinx XST 4.1 SP2 ??

Here's the counter/divider modulo 3 :

--*****************************************************
--*****************************************************
--*****************************************************
library IEEE;
use IEEE.std_logic_1164.all;


entity counter_divider_3 is
  port(
       clk : in STD_LOGIC;
       reset : in STD_LOGIC;
       clk_div_3 : out STD_LOGIC;
       count_3 : out STD_LOGIC_VECTOR(2 downto 0)
  );
end counter_divider_3;

architecture counter_divider_3 of counter_divider_3 is
component clk_adjust
  port (
       a : in STD_LOGIC;
       b : in STD_LOGIC;
       clk : in STD_LOGIC;
       aus : out STD_LOGIC
  );
end component;
component ffdr
  port (
       clk : in STD_LOGIC;
       eing : in STD_LOGIC;
       reset : in STD_LOGIC;
       aus : out STD_LOGIC
  );
end component;
component ffds
  port (
       clk : in STD_LOGIC;
       eing : in STD_LOGIC;
       preset : in STD_LOGIC;
       aus : out STD_LOGIC
  );
end component;


 constant GND_CONSTANT   : STD_LOGIC := '0';
 signal aus2 : STD_LOGIC;
 signal GND : STD_LOGIC;
 signal aus : STD_LOGIC_VECTOR (2 downto 0);

begin

U1 : ffdr
  port map(
       aus => aus(1),
       clk => clk,
       eing => aus(0),
       reset => reset
  );

U2 : clk_adjust
  port map(
       a => aus(0),
       aus => clk_div_3,
       b => aus(1),
       clk => clk
  );

U4 : ffdr
  port map(
       aus => aus(0),
       clk => clk,
       eing => aus2,
       reset => reset
  );

U5 : ffds
  port map(
       aus => aus2,
       clk => clk,
       eing => aus(1),
       preset => reset
  );


GND <= GND_CONSTANT;
aus(2) <= GND;
count_3 <= aus;


end counter_divider_3;




--*****************************************************
--*****************************************************
--*****************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity ffdr is
	port (
		reset : in std_logic;
		clk   : in std_logic;
		eing  : in std_logic;
		aus   : out std_logic
	);
end entity;

architecture ffdr_arch of ffdr is
signal TEMP_aus: std_logic;
begin

	process (clk, reset)
	begin

		if reset = '1' then
			TEMP_aus <= '0';
		elsif falling_edge(CLK) then
			TEMP_aus <= eing;
		end if;

	end process;

	aus <= TEMP_aus;

end architecture;




--*****************************************************
--*****************************************************
--*****************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity ffds is
	port (
		preset : in std_logic;
		clk   : in std_logic;
		eing  : in std_logic;
		aus   : out std_logic
	);
end entity;

architecture ffds_arch of ffds is
signal TEMP_aus: std_logic;
begin

	process (clk, preset)
	begin

		if preset = '1' then
			TEMP_aus <= '1';
		elsif falling_edge(CLK) then
			TEMP_aus <= eing;
		end if;

	end process;

	aus <= TEMP_aus;

end architecture;


--*****************************************************
--*****************************************************
--*****************************************************
library IEEE;
use IEEE.std_logic_1164.all;

entity clk_adjust is
	port (
		a     : in std_logic;
		clk   : in std_logic;
		b     : in std_logic;
		aus   : out std_logic
	);
end entity;

architecture clk_adjust_arch of clk_adjust is
signal TEMP_aus: std_logic;
begin

	process (clk)
	begin
		if rising_edge(CLK) then
			TEMP_aus <= a;
		end if;
	end process;

	aus <= TEMP_aus or b;

end architecture;

Article: 37402
Subject: XESS XSV-800 Gripes
From: VR <nospam@nonexistatdomainbi.com>
Date: Mon, 10 Dec 2001 10:26:45 +0000 (UTC)
Links: << >>  << T >>  << A >>
I don't normally randomly post gripes about something unless it really
sucks and makes me very very angry. If something sucks that much, I might
want to warn people not to use it as well. Guess what? The XESS XSV-800
with the Virtex XCV800 board really sux!! Don't buy it!

I am working on a really simple design, for which I needed an 8-bit input
and a few pushbuttons + small amount of FlashROM. The XSV-800 has exactly
one bank of 8 DIP switches & 4-buttons & a FlashROM. Great I thought, this
solves my problem...NOT!

The XSV-800 multiplexes the DIP switches with 
A) A CPLD on the board 
B) the FlashROM!

This is the only DIP switch (mounted on the board), and it just so happens
my design needs both FlashROM & DIP switches -- the multiplexing prevents
me from using both. But the multiplexing silliness doesn't end there! The
board also has a 10-segment LED bargraph display and two 7-segment
display...

But guess what? That's right!! All the LEDs are multiplexed with
data/address lines of the FlashROM & the Virtex/CPLD!

Really smart if you want to debug a display or look at a register without
having to use a scope/Logic Analyzer!

The DIP switch on the XSV-800 when in "ON" position(labeled on the DIP
switch) actually pulls the line low. I know that XESS did not make the DIP
switch, but the DIP switches on my Xilinx FPGA demoboard don't have ON/OFF
anywhere but ON/OFF is printed on the PCB(and is easy to see) and makes
sense when you use it. One could have been more careful in component
selection...

What's also bad is the DIP switches/buttons aren't near a re-enforced
portion of the PCB, so as you push on them the PCB flexes. Physical
switches in place of the DIP switch (like on other Xess boards) would have
been a much better idea anyway.

Even more clever is the fact that the breakout headers also map to pins
that are connected to SRAM. That's right, ALL "GPIOs" of the Virtex are
multiplexed with the onboard SRAM and you have to make sure the SRAM
ChipSelects are pulled high.

Other hardware problems include:

Voltage regulators that take in DC of 7.5V or even 8V get REALLY hot.
(There is a 7805 and a 317 on there). Also there is no on/off switch if
you use the DC in(or anything else as far as I know) which is a real
bonus. You can use ATX, but I didn't even bother.

There are also jumpers in very tights places, so even changing jumpers is
**really** hard if you don't want your fingers to get poked.

The XSV-800 can configure the FPGA via the on-board FlashROM (somehow, it
isn't working at the moment). It would have much nicer to have a separate
serial EEPROM to store the configuration data as opposed to using a
valuable FlashROM.

As if hardware problems weren't enough! The software issues...

The XSV has 4-banks of SRAM & 1 FlashROM, and you would expect for $1600
you would be able to program them from the PC. The only version of the
tools according to XESS that can do this is version 4.0.

Well XESS has ver 4.0 of their tools available, but they don't work! One
cannot download an image to/from FlashROM / SRAM on a Win2000 PC. A
co-worker engineer even spoke with their FAE who suggested not even using
the 4.0 tools!

I tried for hours to get 4.0 going, changing ECP/EPP/parallel port types,
checking drivers, etc, but to no avail.

The 3.3 tools do work to but do not allow one to download images to/from
FlashROM/SRAM! The downloads (through the parallel port in ECP mode) are
slow as hell too. I think the Xchecker @ 115200 is much faster -- at least
it works reliably.

The only really "good" thing about this board is that it does have some
interesting interfaces including an Ethernet port, VGA, USB, PS/2 and
Audio. But all that doesn't make a difference if using the simple things
is not possible.

And while I know it's quite possible to wire up my own DIP switch, LED,
etc (even to the multiplexed SRAM pins) that's what Xess should have done.

Hopefully no one else will make the mistake of buying this board.

I've used other Xess products in the past and I have found them to work
well. I know people from Xess read this newsgroup and provide great
(free) support, all that withstanding this is still bad...

For the record, I didn't buy this board, it was bought for some research
myself and others do at the Univ. I wasn't "clued in" when this board was
being purchased, had I been though I wouldn't have selected it.

VR.

Article: 37403
Subject: Re: SpartanIIE
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Mon, 10 Dec 2001 11:37:27 +0100
Links: << >>  << T >>  << A >>
Jumping in late due to holidays (lucky me :o)

Jan Gray a écrit :
> 
> [...] The new Spartan-IIE family [...] comes in TQ144 and PQ208
> QFP packages. "

Unfortunately, they don't come in any package between 256 and 456 balls.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 37404
Subject: Re: Translating....
From: "Giggio" <giggio@ciacca.com>
Date: Mon, 10 Dec 2001 12:18:26 +0100
Links: << >>  << T >>  << A >>
Thank you very much for your reply!
I think I understood :)

I find some problems linking the 3 counters with FSM, can you suggest me
something?
For example, which states for FSM?
How can I handle the first loop (i=o) when k should be ignored?
Thanks,
Luigi.



Article: 37405
Subject: Choice of Processor Cores in FPGAs - Both Embedded & Soft
From: sacrosantus@yahoo.com (Dennis)
Date: 10 Dec 2001 03:26:40 -0800
Links: << >>  << T >>  << A >>
Can the Community help me in understanding the basis for the Choice of
Processor Cores in FPGAs(Both embedded & soft) for different kinds of
applications?

Dennis Richards

Article: 37406
Subject: MaxplusII 9.6 under Win2k, any known problems?
From: m.kraemer@planet-interkom.de (=?ISO-8859-1?Q?Michael_Kr=E4mer?=)
Date: 10 Dec 2001 03:48:04 -0800
Links: << >>  << T >>  << A >>
Hello everyone,

I've got a new PC in my company and so I had to re-install the Altera
Maxplus II, V 9.6, which I know is a bit outdated, but still good for
me. The software installs, the features get licensed, but as soon as I
start the compiler, it hangs immediately and consumes 100% CPU
performance. No error message, no system crash. It does'nt matter
which design I compile. I've re-installed the software but the same
effect. I've downloaded fixes from Altera but again no cure.

The new PC is a 1.8 GHz machine and it runs Windows 2000 (the previous
was 300 MHz and WinNT). Did anybody have the same problem and if so,
what was the cure?

Thank you and best regards,

Michael

Article: 37407
Subject: FPGA Advantage and Atmel Figaro
From: "Bernd Scheuermann" <scheuermann@aifb.uni-karlsruhe.de>
Date: Mon, 10 Dec 2001 14:20:38 +0100
Links: << >>  << T >>  << A >>
Hi,

I'd like to configure FPGA Advantage 5.2 and Atmel IDS 7.5 (Figaro) such
that they are properly integrated to develop designs for Atmel FPGAs.

Maybe you know how to ...
a) ...enable IDS to call Leonardo Spectrum/ModelSIM in the design flow
b) ...enable FPGA Advantage to call the IDS place & route tools.

Thanx a lot!

Cheers,


Bernd


e-mail: scheuermann@aifb.uni-karlsruhe.de



Article: 37408
Subject: Timing Simulation Model
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Mon, 10 Dec 2001 15:40:13 +0100
Links: << >>  << T >>  << A >>
I have problems with timing simulation of a block RAM (undetermined
input pin state). The synthesis tool is Synplify, Place&Route is done by
Xilinx Foundation. For Block RAMs the higher level logical model is used
(no backannotation) instead of the physical model. I wonder who
generates these logical models for the block RAMs. The synthesis tool or
the P&R tool? I would say the P&R tool. Is this correct? Thank you.

Michael



Article: 37409
Subject: JBits programming questions.
From: Shi Zhong <sz@dcs.ed.ac.uk>
Date: Mon, 10 Dec 2001 16:10:26 +0000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0AF3B99FF02E1FC6A44E1FAD
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Dear all,

I have some questions about how to use jbits API to test my application:

I implemented a netlist in Xilinx Alliance Tools 3.1 and generated a
'test.bit' bitstream file for Virtex XCV50-BG256.  The pin information
was shown in the attached file 'test.pad'.

I would like to use virtexDS to test the circuit.  How can I set the
value into input pins and get back the value from output pins?

I read the demo programs. For example
CounterTestBenchBS.java--getCounterValue() function. But I am curious
how I can know a specified pin are mapped to which CLB (Row,Col?...etc)?

Looking forward your answer.

Many Thanks
Shi Zhong

--------------0AF3B99FF02E1FC6A44E1FAD
Content-Type: text/plain; charset=us-ascii;
 name="test.pad"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="test.pad"

Release 3.1i - Par D.19
Fri Jul 27 12:37:41 2001

Xilinx PAD Specification File
*****************************

Input file:       map.ncd
Output file:      test.ncd
Part type:        xcv50
Speed grade:      -5
Package:          bg256

Pinout by Pin Name:
+------------------------------------------------+-----------+--------+-------------+----------+------+----------+
|                    Pin Name                    | Direction | Pin    | IO Standard | Drive    | Slew | Resistor |
|                                                |           | Number |             | Strength | Rate |          |
+------------------------------------------------+-----------+--------+-------------+----------+------+----------+
| c2<0>                                          | INPUT     | C12    | LVTTL       |          |      |          |
| c2<10>                                         | INPUT     | A12    | LVTTL       |          |      |          |
| c2<11>                                         | INPUT     | G2     | LVTTL       |          |      |          |
| c2<12>                                         | INPUT     | N2     | LVTTL       |          |      |          |
| c2<13>                                         | INPUT     | R2     | LVTTL       |          |      |          |
| c2<14>                                         | INPUT     | P2     | LVTTL       |          |      |          |
| c2<15>                                         | INPUT     | T3     | LVTTL       |          |      |          |
| c2<16> (VREF)                                  | INPUT     | M2     | LVTTL       |          |      |          |
| c2<17>                                         | INPUT     | C2     | LVTTL       |          |      |          |
| c2<18>                                         | INPUT     | J2     | LVTTL       |          |      |          |
| c2<19>                                         | INPUT     | F2     | LVTTL       |          |      |          |
| c2<1>                                          | INPUT     | C11    | LVTTL       |          |      |          |
| c2<20>                                         | INPUT     | H2     | LVTTL       |          |      |          |
| c2<21>                                         | INPUT     | D2     | LVTTL       |          |      |          |
| c2<22>                                         | INPUT     | B1     | LVTTL       |          |      |          |
| c2<23> (VREF)                                  | INPUT     | R3     | LVTTL       |          |      |          |
| c2<24> (IRDY)                                  | INPUT     | K2     | LVTTL       |          |      |          |
| c2<25>                                         | INPUT     | A7     | LVTTL       |          |      |          |
| c2<26>                                         | INPUT     | F3     | LVTTL       |          |      |          |
| c2<27>                                         | INPUT     | B6     | LVTTL       |          |      |          |
| c2<28>                                         | INPUT     | A6     | LVTTL       |          |      |          |
| c2<29>                                         | INPUT     | A5     | LVTTL       |          |      |          |
| c2<2>                                          | INPUT     | A11    | LVTTL       |          |      |          |
| c2<30>                                         | INPUT     | C8     | LVTTL       |          |      |          |
| c2<31>                                         | INPUT     | B8     | LVTTL       |          |      |          |
| c2<3>                                          | INPUT     | B11    | LVTTL       |          |      |          |
| c2<4>                                          | INPUT     | B9     | LVTTL       |          |      |          |
| c2<5> (VREF)                                   | INPUT     | A8     | LVTTL       |          |      |          |
| c2<6> (DOUT_BUSY)                              | INPUT     | D18    | LVTTL       |          |      |          |
| c2<7>                                          | INPUT     | A9     | LVTTL       |          |      |          |
| c2<8>                                          | INPUT     | A13    | LVTTL       |          |      |          |
| c2<9> (VREF)                                   | INPUT     | B12    | LVTTL       |          |      |          |
| c3<0>                                          | OUTPUT    | V5     | LVTTL       | 12       | SLOW |          |
| c3<10>                                         | OUTPUT    | M3     | LVTTL       | 12       | SLOW |          |
| c3<11>                                         | OUTPUT    | N1     | LVTTL       | 12       | SLOW |          |
| c3<12>                                         | OUTPUT    | L1     | LVTTL       | 12       | SLOW |          |
| c3<13>                                         | OUTPUT    | M1     | LVTTL       | 12       | SLOW |          |
| c3<14> (TRDY)                                  | OUTPUT    | K1     | LVTTL       | 12       | SLOW |          |
| c3<15>                                         | OUTPUT    | L2     | LVTTL       | 12       | SLOW |          |
| c3<16>                                         | OUTPUT    | J1     | LVTTL       | 12       | SLOW |          |
| c3<17>                                         | OUTPUT    | K3     | LVTTL       | 12       | SLOW |          |
| c3<18> (VREF)                                  | OUTPUT    | H1     | LVTTL       | 12       | SLOW |          |
| c3<19>                                         | OUTPUT    | J3     | LVTTL       | 12       | SLOW |          |
| c3<1>                                          | OUTPUT    | W4     | LVTTL       | 12       | SLOW |          |
| c3<20>                                         | OUTPUT    | H3     | LVTTL       | 12       | SLOW |          |
| c3<21>                                         | OUTPUT    | G1     | LVTTL       | 12       | SLOW |          |
| c3<22>                                         | OUTPUT    | E1     | LVTTL       | 12       | SLOW |          |
| c3<23>                                         | OUTPUT    | F1     | LVTTL       | 12       | SLOW |          |
| c3<24>                                         | OUTPUT    | D1     | LVTTL       | 12       | SLOW |          |
| c3<25>                                         | OUTPUT    | E2     | LVTTL       | 12       | SLOW |          |
| c3<26>                                         | OUTPUT    | C1     | LVTTL       | 12       | SLOW |          |
| c3<27> (VREF)                                  | OUTPUT    | G3     | LVTTL       | 12       | SLOW |          |
| c3<28>                                         | OUTPUT    | C7     | LVTTL       | 12       | SLOW |          |
| c3<29>                                         | OUTPUT    | C5     | LVTTL       | 12       | SLOW |          |
| c3<2>                                          | OUTPUT    | V1     | LVTTL       | 12       | SLOW |          |
| c3<30>                                         | OUTPUT    | B3     | LVTTL       | 12       | SLOW |          |
| c3<31>                                         | OUTPUT    | A2     | LVTTL       | 12       | SLOW |          |
| c3<3>                                          | OUTPUT    | U2     | LVTTL       | 12       | SLOW |          |
| c3<4>                                          | OUTPUT    | U1     | LVTTL       | 12       | SLOW |          |
| c3<5>                                          | OUTPUT    | T2     | LVTTL       | 12       | SLOW |          |
| c3<6>                                          | OUTPUT    | R1     | LVTTL       | 12       | SLOW |          |
| c3<7>                                          | OUTPUT    | T1     | LVTTL       | 12       | SLOW |          |
| c3<8>                                          | OUTPUT    | P1     | LVTTL       | 12       | SLOW |          |
| c3<9>                                          | OUTPUT    | N3     | LVTTL       | 12       | SLOW |          |
| k1<0>                                          | INPUT     | C13    | LVTTL       |          |      |          |
| k1<1>                                          | INPUT     | V13    | LVTTL       |          |      |          |
| k1<2>                                          | INPUT     | Y14    | LVTTL       |          |      |          |
| k1<3>                                          | INPUT     | B14    | LVTTL       |          |      |          |
| k1<4>                                          | INPUT     | B13    | LVTTL       |          |      |          |
| l1<0>                                          | INPUT     | A3     | LVTTL       |          |      |          |
| l1<10>                                         | INPUT     | Y2     | LVTTL       |          |      |          |
| l1<11>                                         | INPUT     | V7     | LVTTL       |          |      |          |
| l1<12>                                         | INPUT     | Y5     | LVTTL       |          |      |          |
| l1<13>                                         | INPUT     | W7     | LVTTL       |          |      |          |
| l1<14>                                         | INPUT     | Y6     | LVTTL       |          |      |          |
| l1<15>                                         | INPUT     | V2     | LVTTL       |          |      |          |
| l1<16>                                         | INPUT     | W1     | LVTTL       |          |      |          |
| l1<17>                                         | INPUT     | P3     | LVTTL       |          |      |          |
| l1<18>                                         | INPUT     | V8     | LVTTL       |          |      |          |
| l1<19>                                         | INPUT     | Y7     | LVTTL       |          |      |          |
| l1<1> (VREF)                                   | INPUT     | B4     | LVTTL       |          |      |          |
| l1<20>                                         | INPUT     | W18    | LVTTL       |          |      |          |
| l1<21>                                         | INPUT     | W8     | LVTTL       |          |      |          |
| l1<22>                                         | INPUT     | Y8     | LVTTL       |          |      |          |
| l1<23> (INIT)                                  | INPUT     | U18    | LVTTL       |          |      |          |
| l1<24>                                         | INPUT     | W9     | LVTTL       |          |      |          |
| l1<25> (VREF)                                  | INPUT     | V9     | LVTTL       |          |      |          |
| l1<26> (D7)                                    | INPUT     | V19    | LVTTL       |          |      |          |
| l1<27>                                         | INPUT     | W20    | LVTTL       |          |      |          |
| l1<28>                                         | INPUT     | W11    | LVTTL       |          |      |          |
| l1<29>                                         | INPUT     | Y9     | LVTTL       |          |      |          |
| l1<2>                                          | INPUT     | V6     | LVTTL       |          |      |          |
| l1<30>                                         | INPUT     | W10    | LVTTL       |          |      |          |
| l1<31>                                         | INPUT     | V17    | LVTTL       |          |      |          |
| l1<3> (VREF)                                   | INPUT     | Y3     | LVTTL       |          |      |          |
| l1<4>                                          | INPUT     | C6     | LVTTL       |          |      |          |
| l1<5>                                          | INPUT     | B5     | LVTTL       |          |      |          |
| l1<6>                                          | INPUT     | Y4     | LVTTL       |          |      |          |
| l1<7>                                          | INPUT     | W5     | LVTTL       |          |      |          |
| l1<8>                                          | INPUT     | A4     | LVTTL       |          |      |          |
| l1<9>                                          | INPUT     | W6     | LVTTL       |          |      |          |
| m1<0>                                          | INPUT     | B2     | LVTTL       |          |      |          |
| m1<1>                                          | INPUT     | C9     | LVTTL       |          |      |          |
| m1<2>                                          | INPUT     | C4     | LVTTL       |          |      |          |
| m1<3>                                          | INPUT     | B7     | LVTTL       |          |      |          |
| m1<4>                                          | INPUT     | E3     | LVTTL       |          |      |          |
+------------------------------------------------+-----------+--------+-------------+----------+------+----------+

Dedicated or Special Pin Name:
+------------------------------------------------------------+--------+---------+
|               Dedicated or Special Pin Name                | Pin    | Voltage |
|                                                            | Number |         |
+------------------------------------------------------------+--------+---------+
| CCLK                                                       | B19    |         |
| CS                                                         | B18    |         |
| D1                                                         | E20    |         |
| D2                                                         | G19    |         |
| D3                                                         | J19    |         |
| D4                                                         | M19    |         |
| D5                                                         | P19    |         |
| D6                                                         | T20    |         |
| D7 (l1<26>)                                                | V19    |         |
| DIN_D0                                                     | C19    |         |
| DONE                                                       | W19    |         |
| DOUT_BUSY (c2<6>)                                          | D18    |         |
| DXN                                                        | W3     |         |
| DXP                                                        | V4     |         |
| GND                                                        | D4     |         |
| GND                                                        | M4     |         |
| GND                                                        | L12    |         |
| GND                                                        | L10    |         |
| GND                                                        | L4     |         |
| GND                                                        | K12    |         |
| GND                                                        | K10    |         |
| GND                                                        | C3     |         |
| GND                                                        | J12    |         |
| GND                                                        | J10    |         |
| GND                                                        | J4     |         |
| GND                                                        | E4     |         |
| GND                                                        | D16    |         |
| GND                                                        | D11    |         |
| GND                                                        | D9     |         |
| GND                                                        | K4     |         |
| GND                                                        | L17    |         |
| GND                                                        | V18    |         |
| GND                                                        | L11    |         |
| GND                                                        | V3     |         |
| GND                                                        | L9     |         |
| GND                                                        | U17    |         |
| GND                                                        | K17    |         |
| GND                                                        | U12    |         |
| GND                                                        | K11    |         |
| GND                                                        | U11    |         |
| GND                                                        | K9     |         |
| GND                                                        | U10    |         |
| GND                                                        | J17    |         |
| GND                                                        | U9     |         |
| GND                                                        | J11    |         |
| GND                                                        | U5     |         |
| GND                                                        | J9     |         |
| GND                                                        | U4     |         |
| GND                                                        | E17    |         |
| GND                                                        | T17    |         |
| GND                                                        | D17    |         |
| GND                                                        | T4     |         |
| GND                                                        | D12    |         |
| GND                                                        | M17    |         |
| GND                                                        | D10    |         |
| GND                                                        | M12    |         |
| GND                                                        | D5     |         |
| GND                                                        | M11    |         |
| GND                                                        | C18    |         |
| GND                                                        | M10    |         |
| GND                                                        | M9     |         |
| GND                                                        | U16    |         |
| INIT (l1<23>)                                              | U18    |         |
| IRDY                                                       | K18    |         |
| IRDY (c2<24>)                                              | K2     |         |
| M0                                                         | Y1     |         |
| M1                                                         | U3     |         |
| M2                                                         | W2     |         |
| PROGRAM                                                    | Y20    |         |
| TCK                                                        | A1     |         |
| TDI                                                        | C17    |         |
| TDO                                                        | A20    |         |
| TMS                                                        | D3     |         |
| TRDY                                                       | L20    |         |
| TRDY (c3<14>)                                              | K1     |         |
| VCCINT                                                     | U6     | 2.5     |
| VCCINT                                                     | L3     | 2.5     |
| VCCINT                                                     | D15    | 2.5     |
| VCCINT                                                     | D6     | 2.5     |
| VCCINT                                                     | F4     | 2.5     |
| VCCINT                                                     | F17    | 2.5     |
| VCCINT                                                     | R17    | 2.5     |
| VCCINT                                                     | C10    | 2.5     |
| VCCINT                                                     | U15    | 2.5     |
| VCCINT                                                     | V10    | 2.5     |
| VCCINT                                                     | L18    | 2.5     |
| VCCINT                                                     | R4     | 2.5     |
| VCCO_0                                                     | D8     | 3.30    |
| VCCO_0                                                     | D7     | 3.30    |
| VCCO_1                                                     | D13    | na      |
| VCCO_1                                                     | D14    | na      |
| VCCO_2                                                     | H17    | na      |
| VCCO_2                                                     | G17    | na      |
| VCCO_3                                                     | N17    | na      |
| VCCO_3                                                     | P17    | na      |
| VCCO_4                                                     | U13    | na      |
| VCCO_4                                                     | U14    | na      |
| VCCO_5                                                     | U7     | 3.30    |
| VCCO_5                                                     | U8     | 3.30    |
| VCCO_6                                                     | P4     | 3.30    |
| VCCO_6                                                     | N4     | 3.30    |
| VCCO_7                                                     | G4     | 3.30    |
| VCCO_7                                                     | H4     | 3.30    |
| VREF                                                       | A17    |         |
| VREF                                                       | M18    |         |
| VREF (c2<9>)                                               | B12    |         |
| VREF (c2<5>)                                               | A8     |         |
| VREF (l1<25>)                                              | V9     |         |
| VREF (c2<23>)                                              | R3     |         |
| VREF                                                       | V12    |         |
| VREF (c2<16>)                                              | M2     |         |
| VREF                                                       | Y18    |         |
| VREF (c3<18>)                                              | H1     |         |
| VREF                                                       | V20    |         |
| VREF                                                       | C20    |         |
| VREF                                                       | J18    |         |
| VREF (l1<3>)                                               | Y3     |         |
| VREF (l1<1>)                                               | B4     |         |
| VREF (c3<27>)                                              | G3     |         |
| WRITE                                                      | A19    |         |
+------------------------------------------------------------+--------+---------+

Pinout by Pin Number:
+--------------+-----------------------------------+-----------+------------+
|  Pin Number  |             Pin Name              | Direction | Constraint |
+--------------+-----------------------------------+-----------+------------+
| A1           | (TCK)                             |           |            |
| A2           | c3<31>                            | OUTPUT    |            |
| A3           | l1<0>                             | INPUT     |            |
| A4           | l1<8>                             | INPUT     |            |
| A5           | c2<29>                            | INPUT     |            |
| A6           | c2<28>                            | INPUT     |            |
| A7           | c2<25>                            | INPUT     |            |
| A8           | c2<5> (VREF)                      | INPUT     |            |
| A9           | c2<7>                             | INPUT     |            |
| A10          | ---                               | UNUSED    |            |
| A11          | c2<2>                             | INPUT     |            |
| A12          | c2<10>                            | INPUT     |            |
| A13          | c2<8>                             | INPUT     |            |
| A14          | ---                               | UNUSED    |            |
| A15          | ---                               | UNUSED    |            |
| A16          | ---                               | UNUSED    |            |
| A17          | (VREF)                            |           |            |
| A18          | ---                               | UNUSED    |            |
| A19          | (WRITE)                           |           |            |
| A20          | (TDO)                             |           |            |
| B1           | c2<22>                            | INPUT     |            |
| B2           | m1<0>                             | INPUT     |            |
| B3           | c3<30>                            | OUTPUT    |            |
| B4           | l1<1> (VREF)                      | INPUT     |            |
| B5           | l1<5>                             | INPUT     |            |
| B6           | c2<27>                            | INPUT     |            |
| B7           | m1<3>                             | INPUT     |            |
| B8           | c2<31>                            | INPUT     |            |
| B9           | c2<4>                             | INPUT     |            |
| B10          | ---                               | UNUSED    |            |
| B11          | c2<3>                             | INPUT     |            |
| B12          | c2<9> (VREF)                      | INPUT     |            |
| B13          | k1<4>                             | INPUT     |            |
| B14          | k1<3>                             | INPUT     |            |
| B15          | ---                               | UNUSED    |            |
| B16          | ---                               | UNUSED    |            |
| B17          | ---                               | UNUSED    |            |
| B18          | (CS)                              |           |            |
| B19          | (CCLK)                            |           |            |
| B20          | ---                               | UNUSED    |            |
| C1           | c3<26>                            | OUTPUT    |            |
| C2           | c2<17>                            | INPUT     |            |
| C3           | (GND)                             |           |            |
| C4           | m1<2>                             | INPUT     |            |
| C5           | c3<29>                            | OUTPUT    |            |
| C6           | l1<4>                             | INPUT     |            |
| C7           | c3<28>                            | OUTPUT    |            |
| C8           | c2<30>                            | INPUT     |            |
| C9           | m1<1>                             | INPUT     |            |
| C10          | (VCCINT)                          |           |            |
| C11          | c2<1>                             | INPUT     |            |
| C12          | c2<0>                             | INPUT     |            |
| C13          | k1<0>                             | INPUT     |            |
| C14          | ---                               | UNUSED    |            |
| C15          | ---                               | UNUSED    |            |
| C16          | ---                               | UNUSED    |            |
| C17          | (TDI)                             |           |            |
| C18          | (GND)                             |           |            |
| C19          | (DIN_D0)                          |           |            |
| C20          | (VREF)                            |           |            |
| D1           | c3<24>                            | OUTPUT    |            |
| D2           | c2<21>                            | INPUT     |            |
| D3           | (TMS)                             |           |            |
| D4           | (GND)                             |           |            |
| D5           | (GND)                             |           |            |
| D6           | (VCCINT)                          |           |            |
| D7           | (VCCO_0)                          |           |            |
| D8           | (VCCO_0)                          |           |            |
| D9           | (GND)                             |           |            |
| D10          | (GND)                             |           |            |
| D11          | (GND)                             |           |            |
| D12          | (GND)                             |           |            |
| D13          | (VCCO_1)                          |           |            |
| D14          | (VCCO_1)                          |           |            |
| D15          | (VCCINT)                          |           |            |
| D16          | (GND)                             |           |            |
| D17          | (GND)                             |           |            |
| D18          | c2<6> (DOUT_BUSY)                 | INPUT     |            |
| D19          | ---                               | UNUSED    |            |
| D20          | ---                               | UNUSED    |            |
| E1           | c3<22>                            | OUTPUT    |            |
| E2           | c3<25>                            | OUTPUT    |            |
| E3           | m1<4>                             | INPUT     |            |
| E4           | (GND)                             |           |            |
| E17          | (GND)                             |           |            |
| E18          | ---                               | UNUSED    |            |
| E19          | ---                               | UNUSED    |            |
| E20          | (D1)                              |           |            |
| F1           | c3<23>                            | OUTPUT    |            |
| F2           | c2<19>                            | INPUT     |            |
| F3           | c2<26>                            | INPUT     |            |
| F4           | (VCCINT)                          |           |            |
| F17          | (VCCINT)                          |           |            |
| F18          | ---                               | UNUSED    |            |
| F19          | ---                               | UNUSED    |            |
| F20          | ---                               | UNUSED    |            |
| G1           | c3<21>                            | OUTPUT    |            |
| G2           | c2<11>                            | INPUT     |            |
| G3           | c3<27> (VREF)                     | OUTPUT    |            |
| G4           | (VCCO_7)                          |           |            |
| G17          | (VCCO_2)                          |           |            |
| G18          | ---                               | UNUSED    |            |
| G19          | (D2)                              |           |            |
| G20          | ---                               | UNUSED    |            |
| H1           | c3<18> (VREF)                     | OUTPUT    |            |
| H2           | c2<20>                            | INPUT     |            |
| H3           | c3<20>                            | OUTPUT    |            |
| H4           | (VCCO_7)                          |           |            |
| H17          | (VCCO_2)                          |           |            |
| H18          | ---                               | UNUSED    |            |
| H19          | ---                               | UNUSED    |            |
| H20          | ---                               | UNUSED    |            |
| J1           | c3<16>                            | OUTPUT    |            |
| J2           | c2<18>                            | INPUT     |            |
| J3           | c3<19>                            | OUTPUT    |            |
| J4           | (GND)                             |           |            |
| J9           | (GND)                             |           |            |
| J10          | (GND)                             |           |            |
| J11          | (GND)                             |           |            |
| J12          | (GND)                             |           |            |
| J17          | (GND)                             |           |            |
| J18          | (VREF)                            |           |            |
| J19          | (D3)                              |           |            |
| J20          | ---                               | UNUSED    |            |
| K1           | c3<14> (TRDY)                     | OUTPUT    |            |
| K2           | c2<24> (IRDY)                     | INPUT     |            |
| K3           | c3<17>                            | OUTPUT    |            |
| K4           | (GND)                             |           |            |
| K9           | (GND)                             |           |            |
| K10          | (GND)                             |           |            |
| K11          | (GND)                             |           |            |
| K12          | (GND)                             |           |            |
| K17          | (GND)                             |           |            |
| K18          | (IRDY)                            |           |            |
| K19          | ---                               | UNUSED    |            |
| K20          | ---                               | UNUSED    |            |
| L1           | c3<12>                            | OUTPUT    |            |
| L2           | c3<15>                            | OUTPUT    |            |
| L3           | (VCCINT)                          |           |            |
| L4           | (GND)                             |           |            |
| L9           | (GND)                             |           |            |
| L10          | (GND)                             |           |            |
| L11          | (GND)                             |           |            |
| L12          | (GND)                             |           |            |
| L17          | (GND)                             |           |            |
| L18          | (VCCINT)                          |           |            |
| L19          | ---                               | UNUSED    |            |
| L20          | (TRDY)                            |           |            |
| M1           | c3<13>                            | OUTPUT    |            |
| M2           | c2<16> (VREF)                     | INPUT     |            |
| M3           | c3<10>                            | OUTPUT    |            |
| M4           | (GND)                             |           |            |
| M9           | (GND)                             |           |            |
| M10          | (GND)                             |           |            |
| M11          | (GND)                             |           |            |
| M12          | (GND)                             |           |            |
| M17          | (GND)                             |           |            |
| M18          | (VREF)                            |           |            |
| M19          | (D4)                              |           |            |
| M20          | ---                               | UNUSED    |            |
| N1           | c3<11>                            | OUTPUT    |            |
| N2           | c2<12>                            | INPUT     |            |
| N3           | c3<9>                             | OUTPUT    |            |
| N4           | (VCCO_6)                          |           |            |
| N17          | (VCCO_3)                          |           |            |
| N18          | ---                               | UNUSED    |            |
| N19          | ---                               | UNUSED    |            |
| N20          | ---                               | UNUSED    |            |
| P1           | c3<8>                             | OUTPUT    |            |
| P2           | c2<14>                            | INPUT     |            |
| P3           | l1<17>                            | INPUT     |            |
| P4           | (VCCO_6)                          |           |            |
| P17          | (VCCO_3)                          |           |            |
| P18          | ---                               | UNUSED    |            |
| P19          | (D5)                              |           |            |
| P20          | ---                               | UNUSED    |            |
| R1           | c3<6>                             | OUTPUT    |            |
| R2           | c2<13>                            | INPUT     |            |
| R3           | c2<23> (VREF)                     | INPUT     |            |
| R4           | (VCCINT)                          |           |            |
| R17          | (VCCINT)                          |           |            |
| R18          | ---                               | UNUSED    |            |
| R19          | ---                               | UNUSED    |            |
| R20          | ---                               | UNUSED    |            |
| T1           | c3<7>                             | OUTPUT    |            |
| T2           | c3<5>                             | OUTPUT    |            |
| T3           | c2<15>                            | INPUT     |            |
| T4           | (GND)                             |           |            |
| T17          | (GND)                             |           |            |
| T18          | ---                               | UNUSED    |            |
| T19          | ---                               | UNUSED    |            |
| T20          | (D6)                              |           |            |
| U1           | c3<4>                             | OUTPUT    |            |
| U2           | c3<3>                             | OUTPUT    |            |
| U3           | (M1)                              |           |            |
| U4           | (GND)                             |           |            |
| U5           | (GND)                             |           |            |
| U6           | (VCCINT)                          |           |            |
| U7           | (VCCO_5)                          |           |            |
| U8           | (VCCO_5)                          |           |            |
| U9           | (GND)                             |           |            |
| U10          | (GND)                             |           |            |
| U11          | (GND)                             |           |            |
| U12          | (GND)                             |           |            |
| U13          | (VCCO_4)                          |           |            |
| U14          | (VCCO_4)                          |           |            |
| U15          | (VCCINT)                          |           |            |
| U16          | (GND)                             |           |            |
| U17          | (GND)                             |           |            |
| U18          | l1<23> (INIT)                     | INPUT     |            |
| U19          | ---                               | UNUSED    |            |
| U20          | ---                               | UNUSED    |            |
| V1           | c3<2>                             | OUTPUT    |            |
| V2           | l1<15>                            | INPUT     |            |
| V3           | (GND)                             |           |            |
| V4           | (DXP)                             |           |            |
| V5           | c3<0>                             | OUTPUT    |            |
| V6           | l1<2>                             | INPUT     |            |
| V7           | l1<11>                            | INPUT     |            |
| V8           | l1<18>                            | INPUT     |            |
| V9           | l1<25> (VREF)                     | INPUT     |            |
| V10          | (VCCINT)                          |           |            |
| V11          | ---                               | UNUSED    |            |
| V12          | (VREF)                            |           |            |
| V13          | k1<1>                             | INPUT     |            |
| V14          | ---                               | UNUSED    |            |
| V15          | ---                               | UNUSED    |            |
| V16          | ---                               | UNUSED    |            |
| V17          | l1<31>                            | INPUT     |            |
| V18          | (GND)                             |           |            |
| V19          | l1<26> (D7)                       | INPUT     |            |
| V20          | (VREF)                            |           |            |
| W1           | l1<16>                            | INPUT     |            |
| W2           | (M2)                              |           |            |
| W3           | (DXN)                             |           |            |
| W4           | c3<1>                             | OUTPUT    |            |
| W5           | l1<7>                             | INPUT     |            |
| W6           | l1<9>                             | INPUT     |            |
| W7           | l1<13>                            | INPUT     |            |
| W8           | l1<21>                            | INPUT     |            |
| W9           | l1<24>                            | INPUT     |            |
| W10          | l1<30>                            | INPUT     |            |
| W11          | l1<28>                            | INPUT     |            |
| W12          | ---                               | UNUSED    |            |
| W13          | ---                               | UNUSED    |            |
| W14          | ---                               | UNUSED    |            |
| W15          | ---                               | UNUSED    |            |
| W16          | ---                               | UNUSED    |            |
| W17          | ---                               | UNUSED    |            |
| W18          | l1<20>                            | INPUT     |            |
| W19          | (DONE)                            |           |            |
| W20          | l1<27>                            | INPUT     |            |
| Y1           | (M0)                              |           |            |
| Y2           | l1<10>                            | INPUT     |            |
| Y3           | l1<3> (VREF)                      | INPUT     |            |
| Y4           | l1<6>                             | INPUT     |            |
| Y5           | l1<12>                            | INPUT     |            |
| Y6           | l1<14>                            | INPUT     |            |
| Y7           | l1<19>                            | INPUT     |            |
| Y8           | l1<22>                            | INPUT     |            |
| Y9           | l1<29>                            | INPUT     |            |
| Y10          | ---                               | UNUSED    |            |
| Y11          | ---                               | UNUSED    |            |
| Y12          | ---                               | UNUSED    |            |
| Y13          | ---                               | UNUSED    |            |
| Y14          | k1<2>                             | INPUT     |            |
| Y15          | ---                               | UNUSED    |            |
| Y16          | ---                               | UNUSED    |            |
| Y17          | ---                               | UNUSED    |            |
| Y18          | (VREF)                            |           |            |
| Y19          | ---                               | UNUSED    |            |
| Y20          | (PROGRAM)                         |           |            |
+--------------+-----------------------------------+-----------+------------+

#
# To preserve the pinout above for future design iterations,
# simply run "Lock Pins..." from the Design Manager's Design 
# menu, or invoke PIN2UCF from the command line. The location constraints
# above will be written into your specified UCF file. (The constraints
# listed below are in PCF format and cannot be directly used in the UCF file).
#
COMP "c2<0>" LOCATE = SITE "C12" ; 
COMP "c2<10>" LOCATE = SITE "A12" ; 
COMP "c2<11>" LOCATE = SITE "G2" ; 
COMP "c2<12>" LOCATE = SITE "N2" ; 
COMP "c2<13>" LOCATE = SITE "R2" ; 
COMP "c2<14>" LOCATE = SITE "P2" ; 
COMP "c2<15>" LOCATE = SITE "T3" ; 
COMP "c2<16>" LOCATE = SITE "M2" ; 
COMP "c2<17>" LOCATE = SITE "C2" ; 
COMP "c2<18>" LOCATE = SITE "J2" ; 
COMP "c2<19>" LOCATE = SITE "F2" ; 
COMP "c2<1>" LOCATE = SITE "C11" ; 
COMP "c2<20>" LOCATE = SITE "H2" ; 
COMP "c2<21>" LOCATE = SITE "D2" ; 
COMP "c2<22>" LOCATE = SITE "B1" ; 
COMP "c2<23>" LOCATE = SITE "R3" ; 
COMP "c2<24>" LOCATE = SITE "K2" ; 
COMP "c2<25>" LOCATE = SITE "A7" ; 
COMP "c2<26>" LOCATE = SITE "F3" ; 
COMP "c2<27>" LOCATE = SITE "B6" ; 
COMP "c2<28>" LOCATE = SITE "A6" ; 
COMP "c2<29>" LOCATE = SITE "A5" ; 
COMP "c2<2>" LOCATE = SITE "A11" ; 
COMP "c2<30>" LOCATE = SITE "C8" ; 
COMP "c2<31>" LOCATE = SITE "B8" ; 
COMP "c2<3>" LOCATE = SITE "B11" ; 
COMP "c2<4>" LOCATE = SITE "B9" ; 
COMP "c2<5>" LOCATE = SITE "A8" ; 
COMP "c2<6>" LOCATE = SITE "D18" ; 
COMP "c2<7>" LOCATE = SITE "A9" ; 
COMP "c2<8>" LOCATE = SITE "A13" ; 
COMP "c2<9>" LOCATE = SITE "B12" ; 
COMP "c3<0>" LOCATE = SITE "V5" ; 
COMP "c3<10>" LOCATE = SITE "M3" ; 
COMP "c3<11>" LOCATE = SITE "N1" ; 
COMP "c3<12>" LOCATE = SITE "L1" ; 
COMP "c3<13>" LOCATE = SITE "M1" ; 
COMP "c3<14>" LOCATE = SITE "K1" ; 
COMP "c3<15>" LOCATE = SITE "L2" ; 
COMP "c3<16>" LOCATE = SITE "J1" ; 
COMP "c3<17>" LOCATE = SITE "K3" ; 
COMP "c3<18>" LOCATE = SITE "H1" ; 
COMP "c3<19>" LOCATE = SITE "J3" ; 
COMP "c3<1>" LOCATE = SITE "W4" ; 
COMP "c3<20>" LOCATE = SITE "H3" ; 
COMP "c3<21>" LOCATE = SITE "G1" ; 
COMP "c3<22>" LOCATE = SITE "E1" ; 
COMP "c3<23>" LOCATE = SITE "F1" ; 
COMP "c3<24>" LOCATE = SITE "D1" ; 
COMP "c3<25>" LOCATE = SITE "E2" ; 
COMP "c3<26>" LOCATE = SITE "C1" ; 
COMP "c3<27>" LOCATE = SITE "G3" ; 
COMP "c3<28>" LOCATE = SITE "C7" ; 
COMP "c3<29>" LOCATE = SITE "C5" ; 
COMP "c3<2>" LOCATE = SITE "V1" ; 
COMP "c3<30>" LOCATE = SITE "B3" ; 
COMP "c3<31>" LOCATE = SITE "A2" ; 
COMP "c3<3>" LOCATE = SITE "U2" ; 
COMP "c3<4>" LOCATE = SITE "U1" ; 
COMP "c3<5>" LOCATE = SITE "T2" ; 
COMP "c3<6>" LOCATE = SITE "R1" ; 
COMP "c3<7>" LOCATE = SITE "T1" ; 
COMP "c3<8>" LOCATE = SITE "P1" ; 
COMP "c3<9>" LOCATE = SITE "N3" ; 
COMP "k1<0>" LOCATE = SITE "C13" ; 
COMP "k1<1>" LOCATE = SITE "V13" ; 
COMP "k1<2>" LOCATE = SITE "Y14" ; 
COMP "k1<3>" LOCATE = SITE "B14" ; 
COMP "k1<4>" LOCATE = SITE "B13" ; 
COMP "l1<0>" LOCATE = SITE "A3" ; 
COMP "l1<10>" LOCATE = SITE "Y2" ; 
COMP "l1<11>" LOCATE = SITE "V7" ; 
COMP "l1<12>" LOCATE = SITE "Y5" ; 
COMP "l1<13>" LOCATE = SITE "W7" ; 
COMP "l1<14>" LOCATE = SITE "Y6" ; 
COMP "l1<15>" LOCATE = SITE "V2" ; 
COMP "l1<16>" LOCATE = SITE "W1" ; 
COMP "l1<17>" LOCATE = SITE "P3" ; 
COMP "l1<18>" LOCATE = SITE "V8" ; 
COMP "l1<19>" LOCATE = SITE "Y7" ; 
COMP "l1<1>" LOCATE = SITE "B4" ; 
COMP "l1<20>" LOCATE = SITE "W18" ; 
COMP "l1<21>" LOCATE = SITE "W8" ; 
COMP "l1<22>" LOCATE = SITE "Y8" ; 
COMP "l1<23>" LOCATE = SITE "U18" ; 
COMP "l1<24>" LOCATE = SITE "W9" ; 
COMP "l1<25>" LOCATE = SITE "V9" ; 
COMP "l1<26>" LOCATE = SITE "V19" ; 
COMP "l1<27>" LOCATE = SITE "W20" ; 
COMP "l1<28>" LOCATE = SITE "W11" ; 
COMP "l1<29>" LOCATE = SITE "Y9" ; 
COMP "l1<2>" LOCATE = SITE "V6" ; 
COMP "l1<30>" LOCATE = SITE "W10" ; 
COMP "l1<31>" LOCATE = SITE "V17" ; 
COMP "l1<3>" LOCATE = SITE "Y3" ; 
COMP "l1<4>" LOCATE = SITE "C6" ; 
COMP "l1<5>" LOCATE = SITE "B5" ; 
COMP "l1<6>" LOCATE = SITE "Y4" ; 
COMP "l1<7>" LOCATE = SITE "W5" ; 
COMP "l1<8>" LOCATE = SITE "A4" ; 
COMP "l1<9>" LOCATE = SITE "W6" ; 
COMP "m1<0>" LOCATE = SITE "B2" ; 
COMP "m1<1>" LOCATE = SITE "C9" ; 
COMP "m1<2>" LOCATE = SITE "C4" ; 
COMP "m1<3>" LOCATE = SITE "B7" ; 
COMP "m1<4>" LOCATE = SITE "E3" ; 
#

--------------0AF3B99FF02E1FC6A44E1FAD--


Article: 37410
Subject: Re: IP Updates and Modelsim
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Mon, 10 Dec 2001 09:49:42 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Basuki's advice is good if you are using ModelSim PE or SE however it looks
like the original poster is using ModelSim XE in which case you should not
use the xilinx_lib.tcl script to update the libraries.  XE uses special
libraries which are not counted as user code in its line limits so they
should be downloaded from the Xilinx website and simply decompressed into
the XE install directory.  The location for the updated XE libraries is at:
http://support.xilinx.com/support/mxelibs/index.htm

Installation should be fairly easy and hopefully get you going again.

--  Brian



#BASUKI ENDAH PRIYANTO# wrote:

> Hi Simon,
>
> Download xilinx_lib.tcl from xilinx webpage.
> then, run the tcl script in your modelsim s/w.
>
> Basically, it will updates the new ip to your modelsim library.
>
> You can email me directly, if you can not find the script at xilinx
> webpage.
>
> Regards,
>
> Basuki
>
> :-----Original Message-----
> :From: Simon Deeley [mailto:deeleys@cf.ac.uk]
> :Posted At: Friday, 07 December, 2001 8:38 PM
> :Posted To: fpga
> :Conversation: IP Updates and Modelsim
> :Subject: IP Updates and Modelsim
> :
> :
> :Hi all,
> :I just installed the IP update and got a new synchronous fifo
> :thingy v3 (v2
> :before) but when I try to simulate it using model sim, the
> :compiler can't
> :find the files it needs:
> :
> :# -- Loading entity fifo
> :# ERROR: Could not find
> :c:/Modeltech_xe/win32xoem/../xilinx/vhdl/xilinxcorelib.sync_fifo_v3_0
> :# ERROR: fifo.vhd(56): cannot find expanded name:
> :xilinxcorelib.sync_fifo_v3_0
> :# ERROR: fifo.vhd(57): xilinxcorelib is not an entity.
> :# ERROR: fifo.vhd(74): Error in configuration specification.  Expected
> :entity aspect.
> :# ERROR: fifo.vhd(87): VHDL Compiler exiting
> :# ERROR: c:/Modeltech_xe/win32xoem/vcom failed.
> :# Error in macro ./fifo_tb.fdo line 6
> :# c:/Modeltech_xe/win32xoem/vcom failed.
> :#     while executing
> :# "vcom -skip e -93 -explicit   fifo.vhd"
> :
> :I go to the directory its looking in - there is stuff for
> :previous versions
> :but not for the IP I have updated - does anyone know where I can find
> :updates for the modelsim libraries?
> :
> :Thanks
> :
> :

--------------5AFCDE058E6D9503FA359D29
Content-Type: text/x-vcard; charset=us-ascii;
 name="brian.philofsky.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brian Philofsky
Content-Disposition: attachment;
 filename="brian.philofsky.vcf"

begin:vcard 
n:Philofsky;Brian
x-mozilla-html:FALSE
adr:;;;;;;
version:2.1
email;internet:brian.philofsky@xilinx.com
fn:Brian Philofsky
end:vcard

--------------5AFCDE058E6D9503FA359D29--


Article: 37411
Subject: Re: Michelangelo's Counter
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 10 Dec 2001 09:47:26 -0800
Links: << >>  << T >>  << A >>
A divide-by-3 is a trivial design. It fits into one slice = two 4-input LUTs,
just feeding the two outputs in parallel back to the LUT inputs. The two
remaining inputs of each LUT are "frosting on the cake".
This design, in Virtex-4  runs at 300 MHz, worst case.

Peter Alfke, Xilinx Applications
==============================================

Banana wrote:

> Good Morning
> with this counter/divider modulo 3 I can reach 162.4 MHz
> on a Xilinx XCV1000 BG560 -4 but I need 165MHz, can you
> help me to reach this scope just changing the code or inserting
> some right constrain on Synplify Pro 7.02 or Xilinx XST 4.1 SP2 ??
>
> Here's the counter/divider modulo 3 :
>
> --*****************************************************
> --*****************************************************
> --*****************************************************
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity counter_divider_3 is
>   port(
>        clk : in STD_LOGIC;
>        reset : in STD_LOGIC;
>        clk_div_3 : out STD_LOGIC;
>        count_3 : out STD_LOGIC_VECTOR(2 downto 0)
>   );
> end counter_divider_3;
>
> architecture counter_divider_3 of counter_divider_3 is
> component clk_adjust
>   port (
>        a : in STD_LOGIC;
>        b : in STD_LOGIC;
>        clk : in STD_LOGIC;
>        aus : out STD_LOGIC
>   );
> end component;
> component ffdr
>   port (
>        clk : in STD_LOGIC;
>        eing : in STD_LOGIC;
>        reset : in STD_LOGIC;
>        aus : out STD_LOGIC
>   );
> end component;
> component ffds
>   port (
>        clk : in STD_LOGIC;
>        eing : in STD_LOGIC;
>        preset : in STD_LOGIC;
>        aus : out STD_LOGIC
>   );
> end component;
>
>  constant GND_CONSTANT   : STD_LOGIC := '0';
>  signal aus2 : STD_LOGIC;
>  signal GND : STD_LOGIC;
>  signal aus : STD_LOGIC_VECTOR (2 downto 0);
>
> begin
>
> U1 : ffdr
>   port map(
>        aus => aus(1),
>        clk => clk,
>        eing => aus(0),
>        reset => reset
>   );
>
> U2 : clk_adjust
>   port map(
>        a => aus(0),
>        aus => clk_div_3,
>        b => aus(1),
>        clk => clk
>   );
>
> U4 : ffdr
>   port map(
>        aus => aus(0),
>        clk => clk,
>        eing => aus2,
>        reset => reset
>   );
>
> U5 : ffds
>   port map(
>        aus => aus2,
>        clk => clk,
>        eing => aus(1),
>        preset => reset
>   );
>
> GND <= GND_CONSTANT;
> aus(2) <= GND;
> count_3 <= aus;
>
> end counter_divider_3;
>
> --*****************************************************
> --*****************************************************
> --*****************************************************
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity ffdr is
>         port (
>                 reset : in std_logic;
>                 clk   : in std_logic;
>                 eing  : in std_logic;
>                 aus   : out std_logic
>         );
> end entity;
>
> architecture ffdr_arch of ffdr is
> signal TEMP_aus: std_logic;
> begin
>
>         process (clk, reset)
>         begin
>
>                 if reset = '1' then
>                         TEMP_aus <= '0';
>                 elsif falling_edge(CLK) then
>                         TEMP_aus <= eing;
>                 end if;
>
>         end process;
>
>         aus <= TEMP_aus;
>
> end architecture;
>
> --*****************************************************
> --*****************************************************
> --*****************************************************
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity ffds is
>         port (
>                 preset : in std_logic;
>                 clk   : in std_logic;
>                 eing  : in std_logic;
>                 aus   : out std_logic
>         );
> end entity;
>
> architecture ffds_arch of ffds is
> signal TEMP_aus: std_logic;
> begin
>
>         process (clk, preset)
>         begin
>
>                 if preset = '1' then
>                         TEMP_aus <= '1';
>                 elsif falling_edge(CLK) then
>                         TEMP_aus <= eing;
>                 end if;
>
>         end process;
>
>         aus <= TEMP_aus;
>
> end architecture;
>
> --*****************************************************
> --*****************************************************
> --*****************************************************
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity clk_adjust is
>         port (
>                 a     : in std_logic;
>                 clk   : in std_logic;
>                 b     : in std_logic;
>                 aus   : out std_logic
>         );
> end entity;
>
> architecture clk_adjust_arch of clk_adjust is
> signal TEMP_aus: std_logic;
> begin
>
>         process (clk)
>         begin
>                 if rising_edge(CLK) then
>                         TEMP_aus <= a;
>                 end if;
>         end process;
>
>         aus <= TEMP_aus or b;
>
> end architecture;


Article: 37412
Subject: Re: Altera pin drivers
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 10 Dec 2001 19:21:52 +0100
Links: << >>  << T >>  << A >>
"George P. Kosmopoulos" <gkosmo@ticon.net> schrieb im Newsbeitrag
news:9v1emu$8le$1@galileo.ticon.net...

> Max plus is the easiest tool i've ever used.

Maybe I was not clear enought. We had to use Max plus II (this is different
than Max Plus ??)
So what about the simulator? This is a piece of crap.
The VHDL compiler is a sissy, complains about legal VHDL constructs and
sometimes crashes on them. :-(
The whole designflow sometimes (not rarely) freezes. And it's slow anyway.

--
MfG
Falk





Article: 37413
Subject: Re: SpartanIIE
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 10 Dec 2001 19:24:48 +0100
Links: << >>  << T >>  << A >>
"Nicolas Matringe" <nicolas.matringe@ipricot.com> schrieb im Newsbeitrag
news:3C149067.D21D3DF5@ipricot.com...
> Jumping in late due to holidays (lucky me :o)
>
> Jan Gray a écrit :
> >
> > [...] The new Spartan-IIE family [...] comes in TQ144 and PQ208
> > QFP packages. "
>
> Unfortunately, they don't come in any package between 256 and 456 balls.

The only in-between package in the current Xilinx lines is a BG352. Hmm,
less balls and more area. The only benefit is the wider spacing, maybe good
for low cost, high volume.
Anybody got some numbers how much more expensive a board gets when using a
1mm ball pitch insted of 1.27mm???

--
MfG
Falk




Article: 37414
Subject: Re: Translating....
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 10 Dec 2001 19:33:54 +0100
Links: << >>  << T >>  << A >>
"Giggio" <giggio@ciacca.com> schrieb im Newsbeitrag
news:9v25ng$glp$1@nets3.rz.RWTH-Aachen.DE...
> Thank you very much for your reply!
> I think I understood :)
>
> I find some problems linking the 3 counters with FSM, can you suggest me
> something?
> For example, which states for FSM?
> How can I handle the first loop (i=o) when k should be ignored?

As I said, It all comes down to write down the command sequence, first just
the main (high level) commands, them going more into detail until you reach
the bitlevel.
From this you can draw functional timing diagramms.
From this you can make FSMs.

A small hint

process (clk)
begin
  if reset='1' then
    cnt_1<="0000";
    cnt_2<="0000";
    cnt_3<="0000";
  elsif clk='1' and clk'event then
    cnt_1<=cnt_1+1;
    if cnt_1=15 then
       cnt_2<=cnt_2+1;
       if cnt_2=15 then
          cnt_3<=cnt_3+1;
       end if;
     end if;
  end if;
end process;

--
MfG
Falk




Article: 37415
(removed)


Article: 37416
Subject: Re: Michelangelo's Counter
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 10 Dec 2001 19:52:46 +0100
Links: << >>  << T >>  << A >>
"Banana" <cappellainfuocata@yahoo.it> schrieb im Newsbeitrag
news:d23ae64d.0112092333.7c875d8f@posting.google.com...
> Good Morning
> with this counter/divider modulo 3 I can reach 162.4 MHz
> on a Xilinx XCV1000 BG560 -4 but I need 165MHz, can you
> help me to reach this scope just changing the code or inserting
> some right constrain on Synplify Pro 7.02 or Xilinx XST 4.1 SP2 ??

Hmm, you like instanciation, dont you. ? This code is really overkill for
such a problem. Anyway.
It looks like the is just one level of logic involved, so this should easy
reach 200 MHz. A problem can be that you are trying to work on the rising
and falling edge of the clock, which translates into the double frequency
requirement (when data goes from FFs of one clock edge to FFs on the other
clock edge.). At 160 Mhz, a half period is 3.12 ns, I dont know if the "good
old" Virtex is fast enought for that.
This divide by 3 counter can be made with two shift registers clocked on the
rising and falling edge. The shift registers form a ring buffer, where the
data is circulating in a circle (what a sentence ;-) The output of this
shift registers is XORd and gives the divided by three clock.
By the way, cant the DLL divide by three??

--
MfG
Falk




Article: 37417
(removed)


Article: 37418
(removed)


Article: 37419
Subject: SelectIO and Virtex II: PAR weirdness
From: David Miller <spam@quartz.net.nz>
Date: Tue, 11 Dec 2001 08:20:16 +1300
Links: << >>  << T >>  << A >>
Hi,

I am experiencing weirdness when generating images for Xilinx VirtexII 
parts.  The weirdness takes two forms, both come and go depending on 
what is in the source design.

I am not sure whether the problem(s) are my fault (in the code) or 
whether I am looking at a bona fide bug in PAR.  The code in question 
works fine in simulation (these things always do), and the bits that 
cause problems are tried and tested components in use in other designs 
that are running on older virtex tech.

Symptom one:

Without (an otherwise) known-good piece of code, it compiles fine. 
with: PAR complains:

ERROR:DesignRules:453 - Netcheck: conflicting switch directions found on
signal ADIO<9>.
WARNING:Route:33 - The router has found an error in the
routing of a signal:     ADIO<9>, the routing for this net will be
removed and the net will be  left  unrouted.  Please check to ensure
that the net is valid.

What does this mean?  Why would it do this?  How do I fix it?

Symptom two:

WARNING:Route:50 - The signal "PHY_RDATA_I<6>" has a driver, but the 
driver has
    not been placed so the signal cannot be routed.
WARNING:Route:51 - The signal "PHY_RDATA_IN<6>" is loaded, but the 
load(s) are
    not placed so the signal cannot be routed.

Why couldn't that driver be placed?

In this case, the image will build if a set of DDR IO's are left as 
LVTTL, but will not build if set to HSTL (as they should be).  The 
signal mentioned is in bank 4, and all of the HSTL I/O's are in banks 1 
and 2 -- the other side of the chip.

A related weirdness:

WARNING:DesignRules:455 - Blockcheck: The right edge of the device contains
    most of the configuration pins. This edge currently contains 
SelectIO IOB
    outputs (IO standard HSTL_II for comp QDRRAM_WE_N on site E21) that 
are not
    using the standard supply voltage. Special care must be taken in this
    situation. Please refer to the Xilinx Data Book for the unique 
requirements
    of the device's right edge.

But, on a XC2V1000FG456, E21 isn't in a bank that holds any 
configuration pins.  Is it possible that it is getting horribly confused 
about where pads are?


Environment: AldecHDL, Synplify Pro, Xilinx Alliance 3.3pl8 + VirtexII 
bitgen patch, VHDL, VirtexII xc2v1000fg456-5, Xilinx's PCI logicore




-- 
David Miller, BCMS (Hons)  | When something disturbs you, it isn't the
Endace Measurement Systems | thing that disturbs you; rather, it is
Mobile: +64-21-704-djm     | your judgement of it, and you have the
Fax:    +64-21-304-djm     | power to change that.  -- Marcus Aurelius


Article: 37420
Subject: Re: Translating....
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 10 Dec 2001 11:59:55 -0800
Links: << >>  << T >>  << A >>
Giggio wrote:

> ..I need to translate from C to VHDL a program that I did...

Consider creating a simulation model 
and testbench as step one.

VHDL can do nested loops and arrays.
A numeric and math library can cover
the * and sqrt.

It's much easier to carve the logic
into synth slices once you have the
basic translation complete and a
functional testbench.

  --Mike Treseler

Article: 37421
Subject: IP Core Update #1
From: "Bernd Scheuermann" <scheuermann@aifb.uni-karlsruhe.de>
Date: Mon, 10 Dec 2001 21:17:56 +0100
Links: << >>  << T >>  << A >>
Hi,

the MXE libraries of the latest IP core update #1 are precompiled for
ModelSIM Xilinx edition only. Do you know how to compile this update in
ModelSIM SE 5.5e?

Cheers,


Bernd

e-mail: scheuermann@aifb.uni-karlsruhe.de



Article: 37422
Subject: Re: Timing Simulation Model
From: Andy Peters <andy@exponentmedia.deletethis.com>
Date: Mon, 10 Dec 2001 20:57:59 GMT
Links: << >>  << T >>  << A >>
Michael Boehnel wrote:
> 
> I have problems with timing simulation of a block RAM (undetermined
> input pin state). The synthesis tool is Synplify, Place&Route is done by
> Xilinx Foundation. For Block RAMs the higher level logical model is used
> (no backannotation) instead of the physical model. I wonder who
> generates these logical models for the block RAMs. The synthesis tool or
> the P&R tool? I would say the P&R tool. Is this correct? Thank you.

If you're instantiating a library component, such as a RAM, then the
model is from the Xilinx simulation library.

If you are writing code that infers the RAM, then there's no "model"
other than your code.

BTW: you should carefully check Xilinx' simulation models.


-a

Article: 37423
Subject: Re: Altera pin drivers
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 10 Dec 2001 13:08:58 -0800
Links: << >>  << T >>  << A >>
Falk Brunner wrote:

> So what about the simulator? 
> The VHDL compiler is a sissy

Maxplus and Quartus are tools 
to place and route edif or vhdl netlists.
To do synthesis or simulation,
you need other tools.

       -- Mike Treseler

Article: 37424
Subject: Re: Michelangelo's Counter
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 10 Dec 2001 13:19:30 -0800
Links: << >>  << T >>  << A >>


Falk Brunner wrote:

> "
> By the way, cant the DLL divide by three??
>

Yes the DLL  can do it for free.
And the normal,  33% duty-cycle division takes only one slice and runs at 300
MHz, and for 50% duty cycle, there is a design at

http://www.xilinx.com/xcell/xl33/xl33_30.pdf

So there are plenty of ways to solve this non-problem.

Peter Alfke




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