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Messages from 37925

Article: 37925
Subject: Re: Look for FPGA Starterkit
From: newman5382@aol.com (newman)
Date: 25 Dec 2001 02:05:51 -0800
Links: << >>  << T >>  << A >>
"David G." <dgeerinck@yahoo.com> wrote in message news:<3c27e328$0$10318$ba620e4c@news.skynet.be>...
> Hi,
> I saw this year some basics of vhdl at school.
> I'm now looking for some kind of FPGA-starterkit who allows me
> to experiment on simple I/O like leds, LCD screens, com-ports,
> RAM, ETHERNET,etc that are accesible through a simple electronic board.
> 
> I heard of a Xilinx starterkit but found it a bit expesive
> for the pour student I am :-(
> 
> 
> Thanks.
> 
> David.

David,
  The Spartan IIE board from Nu Horizons is a low cost entry vehicle
that can run off the free Webpack software (see URL below). It however
does not have all your wish list items, but you may be able to
prototype some of the easier ones in.
  Is ethernet classified as simple by students nowadays?  If so, 
I had better go back to school! 

http://www.nuhorizons.com/EngineeringServices/SpartanIIEBoard.html

Newman

Article: 37926
Subject: Lattice Filter Schematic?
From: "Daniel Yap" <daniu_yap@hotmail.com>
Date: Tue, 25 Dec 2001 18:09:17 +0800
Links: << >>  << T >>  << A >>
Hi,
I am looking for a schematic diagram on Lattice Filter. Anyone can provide
me some diagram on it? Coz  I am doing a FPGA project on this filter and I
need to understand the algorithm.

Daniel Yap



Article: 37927
Subject: Re: Where could I get a signal waveform editor?
From: wacky_me@rediffmail.com (freny)
Date: 25 Dec 2001 02:13:36 -0800
Links: << >>  << T >>  << A >>
Kevin Brace  <nospamtomyaddresskevinbraceusenet@hotmail.comnospamtomyaddress> wrote in message news:<3C281960.DB85C679@hotmail.comnospamtomyaddress>...
> I am wondering if there is kind of software which I can easily draw and
> edit bus signal waveforms with a mouse and a keyboard, and print it out
> from a printer.
> I can think of Altera MAX+PLUS II-BASELINE's waveform editor, but does
> anyone else know something better?
> I will like to improve my productivity, and one thing that took forever
> during a design I worked on was drawing sample waveforms of a design I
> am working on sheets of paper with a pencil and a ruler.
> From these sample waveforms I think about how I will design state
> machines and when I should change a value of a FF.
> After the state machine design is done, I go into HDL coding.
> So, does anyone know such a tool I am talking about?
> 
> 
> 
> Thanks,
> 
> 
> 
> Kevin Brace (don't respond to me directly, respond within the newsgroup)


u can try LATEX ...its pretty good

Article: 37928
(removed)


Article: 37929
Subject: Re: Where could I get a signal waveform editor?
From: "jrschenk" <jrschenk@t-online.de>
Date: Tue, 25 Dec 2001 12:51:16 +0100
Links: << >>  << T >>  << A >>

"Kevin Brace"
<nospamtomyaddresskevinbraceusenet@hotmail.comnospamtomyaddress> wrote in
message news:3C281960.DB85C679@hotmail.comnospamtomyaddress...
> I am wondering if there is kind of software which I can easily draw and
> edit bus signal waveforms with a mouse and a keyboard, and print it out
> from a printer.
> I can think of Altera MAX+PLUS II-BASELINE's waveform editor, but does
> anyone else know something better?
> I will like to improve my productivity, and one thing that took forever
> during a design I worked on was drawing sample waveforms of a design I
> am working on sheets of paper with a pencil and a ruler.
> From these sample waveforms I think about how I will design state
> machines and when I should change a value of a FF.
> After the state machine design is done, I go into HDL coding.
> So, does anyone know such a tool I am talking about?
>
>
>
> Thanks,
>
>
>
> Kevin Brace (don't respond to me directly, respond within the newsgroup)


You could try timing designer from Chronology.
http://www.forteds.com/products/td_overview.html



Article: 37930
Subject: Re: Where could I get a signal waveform editor?
From: ZhengLin <zdzlin@163.com>
Date: Tue, 25 Dec 2001 05:41:29 -0800
Links: << >>  << T >>  << A >>
Testbench and Modelsim can do these work, you may try to use them!

Article: 37931
(removed)


Article: 37932
Subject: Re: Where could I get a signal waveform editor?
From: "Johnsonw10" <johnsonw10_NOSPAM@hotmail.com>
Date: Tue, 25 Dec 2001 22:54:45 GMT
Links: << >>  << T >>  << A >>
SynaptiCAD  has a tool called "Waveformer" which you may want to take a look
at. Their website is http://www.syncad.com/.

HTH,
Jim

"Kevin Brace"
<nospamtomyaddresskevinbraceusenet@hotmail.comnospamtomyaddress> wrote in
message news:3C281960.DB85C679@hotmail.comnospamtomyaddress...
> I am wondering if there is kind of software which I can easily draw and
> edit bus signal waveforms with a mouse and a keyboard, and print it out
> from a printer.
> I can think of Altera MAX+PLUS II-BASELINE's waveform editor, but does
> anyone else know something better?
> I will like to improve my productivity, and one thing that took forever
> during a design I worked on was drawing sample waveforms of a design I
> am working on sheets of paper with a pencil and a ruler.
> From these sample waveforms I think about how I will design state
> machines and when I should change a value of a FF.
> After the state machine design is done, I go into HDL coding.
> So, does anyone know such a tool I am talking about?
>
>
>
> Thanks,
>
>
>
> Kevin Brace (don't respond to me directly, respond within the newsgroup)



Article: 37933
Subject: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
From: hrzic <hrzic@worldnet.att.net>
Date: Tue, 25 Dec 2001 16:13:23 -0800
Links: << >>  << T >>  << A >>
I have a problem using RAMB4_S8_S16. 
Map tool reports "Loadless block "EX_SW" (RAMB4_S8_S16) removed." and remove RAM from design.

What is wrong with this design?

Thanks,
Branko

`timescale 1ns / 10ps

	module	EXECUTE(
			.fpga_clk(fpga_clk),
			.SW_RX_upisi(SW_RX_upisi),
			.SW_RX_procitaj(SW_RX_procitaj),
			.SW_EX_upisi(SW_EX_upisi),
			.SW_EX_procitaj(SW_EX_procitaj)

			);
	
	
			input					fpga_clk;
			output	[2:0]		SW_RX_upisi;
			input		[2:0]		SW_RX_procitaj;
			input		[2:0]		SW_EX_upisi;
			output	[2:0]		SW_EX_procitaj;		

		
/*			wire		[7:0] 	RX_addrB_SW;
			wire		[15:0]	RX_read_dataB_SW;
			wire					RX_wrB_SW;
*/			reg		[7:0] 	EX_addrB_SW;
			reg		[15:0] 	EX_write_dataB_SW;	
			wire		[15:0]	EX_read_dataB_SW;
			reg					EX_wrB_SW;

/*			reg		[8:0] 	RX_addrA_SW;
			reg		[7:0] 	RX_write_dataA_SW;	
			reg					RX_wrA_SW;
*/			reg		[8:0] 	EX_addrA_SW;
			wire		[7:0] 	EX_read_dataA_SW;	
			reg		[7:0] 	EX_write_dataA_SW;	
			reg					EX_wrA_SW;

			reg		[2:0]		SW_RX_upisi;
			reg		[2:0]		SW_EX_procitaj;

			reg 		[17:0]	Addr_EX;
			reg					AddrSet_EX;
			reg 					rw_EX;
			reg		[15:0]	DataWrite_EX;		
		
		
			reg		[5:0]		taking;			// byte pointer in package
			reg		[7:0]		EX_data;
			reg		[2:0]		NextSW_EX_procitaj;
			reg		[2:0]		CycleEX;
		

			wire					gnd = 1'b0;
			wire					pwr = 1'b1;
	

	
		RAMB4_S8_S16 EX_SW (
								.ADDRA(EX_addrA_SW), .DOA(EX_read_dataA_SW),
								.WEA(EX_wrA_SW), 						.DIA(EX_write_dataA_SW), 				
								.ADDRB(EX_addrB_SW), .DIB(EX_write_dataB_SW),
								.WEB(EX_wrB_SW), 						.DOB(EX_read_dataB_SW), 
	                     .CLKA(fpga_clk), .CLKB(fpga_clk),  	
	   						.RSTA(gnd),  .ENA(pwr), .RSTB(gnd), .ENB(pwr));	
	

		always @ (posedge fpga_clk) begin	

			if (CycleEX == 0 && SW_EX_procitaj != SW_EX_upisi)		EX_addrA_SW <= (SW_EX_procitaj * 64) + taking;
			if (CycleEX == 0 && SW_EX_procitaj != SW_EX_upisi)		EX_data <= EX_read_dataA_SW;
			if (CycleEX == 1) 												EX_addrA_SW <= EX_addrA_SW +1;

			EX_addrB_SW <= 0;
			EX_write_dataB_SW <= 0;
			EX_wrB_SW <= 0;

			rw_EX <= 1;
/*			RX_wrA_SW <= 0;
			RX_addrA_SW <= 0;
*/
			EX_write_dataA_SW <= 0;

		end

	

		always @ (posedge fpga_clk) begin
			case(CycleEX)
			0	:	if(SW_EX_procitaj != SW_EX_upisi) begin
//							EX_addrA_SW <= (SW_EX_procitaj * 64) + taking;
//							EX_data <= EX_read_dataA_SW;
						EX_wrA_SW <= 0;					// read
						CycleEX <= 1;						// start parameters for packet transfer					
						end
			1	:	begin  
						taking <= taking + 1;
//							EX_addrA_SW <= EX_addrA_SW +1;

						// obrada comande

						if (taking > 64) begin
							taking <= 0;
							if (NextSW_EX_procitaj != SW_EX_upisi)	begin
								SW_EX_procitaj <= SW_EX_procitaj + 1;
								CycleEX <= 0;
								end
							else CycleEX <= 2;
							end
						end
			2	:	if(NextSW_EX_procitaj != SW_EX_upisi) begin // do not add upisi counter if you catch procitaj counter			
						SW_EX_procitaj <= SW_EX_procitaj + 1;
						NextSW_EX_procitaj <= NextSW_EX_procitaj + 1;
						CycleEX <= 0;
						end
			default	: CycleEX <= 0;				// start from beginning
			endcase

		end

	endmodule

Article: 37934
(removed)


Article: 37935
Subject: Innoveda Speedwave vs. Modelsim?
From: Andy Hall <dont_spam_andy@dont_spam_gordian_either.com>
Date: Tue, 25 Dec 2001 17:40:24 -0800
Links: << >>  << T >>  << A >>
  Hello,

I'm wondering if anybody has used both Innoveda's Speedwave and
Modelsim, and if so, whether you could give me your opinions on one
vs. the other. Following is some background / context / preliminary 
conclusions, read as little as you like. 

I'm the VHDL guy at a small design house. I've used speedwave for ~ 5
years, except for one class I took that used Model Tech. I've been
able to get the job done with Speedwave, though I've filed my share
(perhaps more) of bug reports, and in the mean time made a lot of
excuses to coworkers who were learning vhdl with it (especially the 
unix version). I've even been a beta test site a few times, feeling it
was my best leverage point for getting things fixed, though they
weren't able to fix everything by whichever release time (and other
things broke in the process). Support has been okay, at least to the
point of their acknowleging defects, then silence. Updates have been
infrequent, and patches nearly non-existant. 

During this time we had an odd licensing agreement with Viewlogic and
then Innoveda, which got us the tools relatively cheaply, which kept
us locked in. But Innoveda isn't willing to continue with it this
year, and instead wants to sell us the seats, from scratch. (I'm not
considering leaving viewdraw, we need that for PCBs.) 

So I'm in the position where I have to buy a simulator seat (vhdl &
verilog cosimulation; unix would be good for networking reasons, linux
if possible, preferably not windoze only; primarily xilinx, up to 200K
gates as yet, occasional asic). I am hesitant to throw that kind of
money at a tool that I've had so many problems with. (Of course on the
other hand I'm familiar with the problems, and work-arounds are
already in the code base. But on the *other* other hand, with their
latest tool release, VHDL Compiler 7.2, I've found three brand new
bugs, on code that had worked with earlier versions.) I have what
appears to be an attractive offer from Model Tech, but only good till
the end of the quarter, and for other reasons I need to make a
decision this week.

Yes, I feel stupid and silly for being at this point without having
more of a grasp on the tool options available, but this only came up
last friday. I had been ready to stick with the Known Evil if I could
have gotten a better offer on the seats from Innoveda, and I really
didn't want to deal with a tool evaluation, potentially changing our
design flow etc., but now I need to. Progress on innoveda tools in
general has always been three steps forward, two back, and I don't see
this changing any time soon. If there's a "world class" solution, for
similar cost, which isn't also problematic, then I want us to be there. 

(BTW, I'm not totally sure about these, but Speedwave is I think
Vantage/VSS, which might be Synopsys? And their verilog compiler VCSi
sounds like it's also OEMed from Synopsys? So maybe I'm asking about
Synopsys vs. Model Tech, independent of the additional bells &
whistles Innoveda provides in Fusion.)

Anyway, I've done some research, though not as thorough as I'd like. 
I've heard Modelsim has like 60% of the market share (which can be
either a plus or a minus, depending on whether the company involved
makes HDL simulators or operating systems; so apparently more of a
plus), and that they're sticklers for adhering to the standards. I
have an eval license and have been learning the tool, though I lost
the use of the weekend due to a wrong unix host ID and then Win2K
licensing bogosities. Their platform mix is good. There are some other
features (code coverage, breakpoints within packages [I think?], some
platform independence, and peformance analysis, plus presumably
improved speed) that are of interest but which I wouldn't have under
speedwave.

I've seen an Innoveda press release saying that they won't do any more 
development on FPGA tools, though I don't know if these tools qualify,
or if it's just like their no longer OEMing of FPGA Express and such. 
I've searched the comp.arch.vhdl archives, and haven't seen many
complaints about modelsim, aside from licensing grief which is
temporary. And it seems learned that they're pretty open about what
sort of bugs are already known about when a tool is released. 

What a change would lose for me is the ability to do mixed schematic /
hdl simulations, though we've only used this once or twice. Also
there's the impact on my legacy simulation command files. But I use
testbenches where possible, command files only to set up waveforms,
high level control inputs etc., so hopefully this would be minimized.
Both tools are apparently usable for asic signoff.

The modelsim unix version has been working fine (tutorials only as
yet, I'm sure I'll need to recode something before attacking my main
project). Their port of tools written for PCs to the unix platform
feels a lot more solid and complete than Innoveda's, which uses a
package which translates Windoze calls to unix. 

I notice there is one feature missing in the modelsim waveform viewer,
which I used a fair amount under speedwave: being able to have more
than one Values column, tied to each cursor, so I can see values at
different times simultaneously. But there's going to be a lot of
functionality that I won't be able to test quickly, so there will be a
lot that I miss. Do people here have opinions on the subject? Gotcha's, 
warnings, or "what took you so long"s?

Unless I hear anything earth shattering I'll probably do the switch. 
But even so it would be nice to have some validation, just so I can
relax on vacation. :-) Thanks for your time ...

  Andy Hall
  andy at gordian dot com
  Gordian

Article: 37936
Subject: Re: Where could I get a signal waveform editor?
From: "Eric Pearson" <ecp@mgl.ca>
Date: Tue, 25 Dec 2001 22:43:02 -0500
Links: << >>  << T >>  << A >>
Hi Kevin...

I've been using Excel. You can also to some simulation for boundary testing,
and
the cell coloring features are useful for pipeline tracking.

Eric Pearson

"Kevin Brace"
<nospamtomyaddresskevinbraceusenet@hotmail.comnospamtomyaddress> wrote in
message news:3C281960.DB85C679@hotmail.comnospamtomyaddress...
> I am wondering if there is kind of software which I can easily draw and
> edit bus signal waveforms with a mouse and a keyboard, and print it out
> from a printer.
> I can think of Altera MAX+PLUS II-BASELINE's waveform editor, but does
> anyone else know something better?
> I will like to improve my productivity, and one thing that took forever
> during a design I worked on was drawing sample waveforms of a design I
> am working on sheets of paper with a pencil and a ruler.
> From these sample waveforms I think about how I will design state
> machines and when I should change a value of a FF.
> After the state machine design is done, I go into HDL coding.
> So, does anyone know such a tool I am talking about?
>
>
>
> Thanks,
>
>
>
> Kevin Brace (don't respond to me directly, respond within the newsgroup)



Article: 37937
Subject: Re: availability of VirtexII production silicon
From: Jkkfjf <jlgkgk@kjldskf.net>
Date: Wed, 26 Dec 2001 05:17:45 GMT
Links: << >>  << T >>  << A >>
> >There were, sigh, several little things to fix. And at the going price for
> >a mask set ( multi-$100k) we do a lot of simulations, and manufacturing
> >takes many weeks or months.
> >I think we all agree that these chips are quiet complex, almost as complex
> >as software  ;-)
> 
> I am glad quiet complex. If they were loud and complex, I guess we
> would've been in a lot more trouble :-). Actually having been
> struggling with a 400uX420u .25u standard cell digital macro running
> at 500 MHz for the last three weeks, I should be more respectful. It
> is amazing how bad the generic standard cell libraries are and how
> good a virtex-ii is.
> Muzaffer Kal

My goodness, it's Christmas (here in the USA), and you engineers are
*STILL* at your desks?  For shame, take some time off for the holidays.

Which foundry product-line (NEC, Toshiba, TI, LSI, IBM, TSMC, UMC, etc.) 
and standard-cell library (Artisan Components?!?) are you using?  I
heard
the vendor can make a big difference.  For example, IBM's state-of-the-
art fabs charge the most per wafer, but also yield the best performance.

TSMC and UMC are generally on the cheaper side, and yield
correspondingly
lower performance (in terms of highest clock frequency.)  Funny, we're
using TSMC's standard-cell 0.18 process, and their library documentation
recommends " ~400MHz " as the highest design target.  (Ok, I may be
looking at outdated spec-sheets.)

Article: 37938
Subject: Re: Where could I get a signal waveform editor?
From: "Srinivasan Venkataramanan" <srinivasan@siliconsystems.co.in>
Date: Wed, 26 Dec 2001 13:11:12 +0530
Links: << >>  << T >>  << A >>
Hi,
  Try

1.> http://members.aol.com/d2fabrizio/
2.> http://www.timingtool.com/

HTH,
Srinivasan


"Kevin Brace"
<nospamtomyaddresskevinbraceusenet@hotmail.comnospamtomyaddress> wrote
in message news:3C281960.DB85C679@hotmail.comnospamtomyaddress...
> I am wondering if there is kind of software which I can easily draw
and
> edit bus signal waveforms with a mouse and a keyboard, and print it
out
> from a printer.
> I can think of Altera MAX+PLUS II-BASELINE's waveform editor, but
does
> anyone else know something better?
> I will like to improve my productivity, and one thing that took
forever
> during a design I worked on was drawing sample waveforms of a design
I
> am working on sheets of paper with a pencil and a ruler.
> From these sample waveforms I think about how I will design state
> machines and when I should change a value of a FF.
> After the state machine design is done, I go into HDL coding.
> So, does anyone know such a tool I am talking about?
>
>
>
> Thanks,
>
>
>
> Kevin Brace (don't respond to me directly, respond within the
newsgroup)

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"




Article: 37939
Subject: Re: Look for FPGA Starterkit
From: arlington_sade@yahoo.com (arlington)
Date: 26 Dec 2001 10:36:27 -0800
Links: << >>  << T >>  << A >>
newman5382@aol.com (newman) wrote in message news:<e6038423.0112250205.2dc10d88@posting.google.com>...
> "David G." <dgeerinck@yahoo.com> wrote in message news:<3c27e328$0$10318$ba620e4c@news.skynet.be>...
> > Hi,
> > I saw this year some basics of vhdl at school.
> > I'm now looking for some kind of FPGA-starterkit who allows me
> > to experiment on simple I/O like leds, LCD screens, com-ports,
> > RAM, ETHERNET,etc that are accesible through a simple electronic board.
> > 
> > I heard of a Xilinx starterkit but found it a bit expesive
> > for the pour student I am :-(
> > 
> > 
> > Thanks.
> > 
> > David.
> 
> David,
>   The Spartan IIE board from Nu Horizons is a low cost entry vehicle
> that can run off the free Webpack software (see URL below). It however
> does not have all your wish list items, but you may be able to
> prototype some of the easier ones in.
>   Is ethernet classified as simple by students nowadays?  If so, 
> I had better go back to school! 
> 
> http://www.nuhorizons.com/EngineeringServices/SpartanIIEBoard.html
> 
> Newman

Where can I buy 10 XC2S200E in the SF Bay Area ? Thanks.

Article: 37940
Subject: Re: Kindergarten Stuff
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 26 Dec 2001 19:48:18 +0000
Links: << >>  << T >>  << A >>


Ed Ngai wrote:

> Rick Filipkiewicz wrote:
>
>
> > I've finally found him - the other FX780/880 user! In fact Intel didn't obsolete
> > them they sold them to Altera. I believe Altera just wanted access to the Flash
> > technology and so they, Altera, obsoleted them 18 months or so later. By then,
> > of course, the XC95K devices were on stream ...
>
> I can't believe it, You Too?!  Brings back the ole days of DOS 3.3 and PLD
> SHell.
> in fact ... scrounge around a bit, here it is..  PLDShell R1.0 Featuring PLDasm,
> reg card and everything. I made my 1st attempt of a state machine back then.
>

I'm glad you didn't prefix ``ole'' with ``good''.

We were more or less compelled to use these devices, if we wanted to use CPLDs at all,  since the
client had an unmoveable requirement for field upgrade capability and QFP sockets were, and still
are IMO, very bad news.

Just remembered that, of course, the 740/780 didn't have the Flash - that came in with the 880. So
we kept the configuration in a 256K EPROM (the fitter could output a file that consisted of
TDI/TMS pairs) & used a PAL to stuff it into the CPLD. In that sense the devices were much more
like an SRAM based FPGA.



Article: 37941
Subject: Re: Innoveda Speedwave vs. Modelsim?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 26 Dec 2001 20:12:27 +0000
Links: << >>  << T >>  << A >>


Andy Hall wrote:

>   Hello,
>

<snip>

I've been using ModelSim for a long time now.  As far as I can see its now
about as bullet-proof, at least for Verilog, as an EDA tool ever gets. The
only caveat I can see from your point of view is that most of the bugs that
are turning up these days (you are right about their near-Xilinx level of
openness) seem to be in Verilog/VHDL mixed simulation or VHDL alone.

>
> The modelsim unix version has been working fine (tutorials only as
> yet, I'm sure I'll need to recode something before attacking my main
> project). Their port of tools written for PCs to the unix platform
> feels a lot more solid and complete than Innoveda's, which uses a
> package which translates Windoze calls to unix.
>

We have the PC version (aka the -PE) but I was told by a support guy that,
in fact, all the development work has always been done on Unix/Linux and
then ported to the PC platform. They had Linux versions running in house a
long time before they were released.

One day I'll persuade my colleagues to stump up the dosh for the Linux
version .... there are times when I'd dearly like the waveform comparator
or to have the -fast compiler switch work.

Surely it wouldn't be too hard with a bit of Perl to make a VHDL netlist
from the schematic portion of your flow ? Its what we do for board level
simulation (except, of course, its Verilog).




Article: 37942
Subject: Re: Virtex-2 maximum clock speed
From: "Carl Brannen" <carl.brannen@terabeam.com>
Date: Wed, 26 Dec 2001 22:36:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
Austin, with regard to "A really good engineer who knows the structure may
(only may) get a better
result.  That is because the engineer does not really know the structure.  A
good example is the FPGA editor view which is a simplistic representation of
the chip -- not at all how it is really implemented.  The synthesis tools
now know all of the tricks and truly know the structures, and their costs."

I disagree.

(1) The tools have very little idea what the silicon is capable of.
(2) The FPGA editor provides an engineer full knowledge of what the silicon
is capable of.  The delays are there, as are all the bits that can be
manipulated.  If the synthesis tools can make it, it is observable with FPGA
Editor.
(3) If you want some examples, I'll publish my arithmetic templates.  They
allow all kinds of stuff to be put in a slice that the tools simply can't do.

Maybe someday the tools will be able to match a "really good engineer", but it
hasn't happened yet.  Even if the tools had full knowledge of what can be put
into a Virtex slice, they don't know how to do a global optimization for
the design.

Carl


-- 
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via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 37943
Subject: Re: Look for FPGA Starterkit
From: "Tony Burch" <tony@BurchED.com.au>
Date: Thu, 27 Dec 2001 09:47:19 +1100
Links: << >>  << T >>  << A >>
Hi David,

> Hi,
> I saw this year some basics of vhdl at school.
> I'm now looking for some kind of FPGA-starterkit who allows me
> to experiment on simple I/O like leds, LCD screens, com-ports,
> RAM, ETHERNET,etc that are accesible through a simple electronic board.
>

Perhaps you could consider the B5-Super-Value-Pack
from Burch Electronic Designs:
http://www.burched.com.au/B5SuperValuePack.html

It is priced to be affordable for every development
lab, and for students.

It allows experimenting with SRAM, SWITCHES, LEDS
PERIPHERAL-CONNECTORS (vga, rs232 com, mouse, keyboard,
buzzer), PARALLEL-PORT-INTERFACE, IDE-INTERFACE,
SOLIDSTATE-HARDDISK Flash Memory Disk and 7SEG-DISPLAYS.

We offer items in this set for sale separately, conistent
with our philosopy of allowing users to "buy and plug on
only what you need for your system".
So, if the Super-Value-Pack set is too much intitially,
then you can get the base B5-SPARTAN2+ unit,
http://www.burched.com.au/B5Spartan2.html
and maybe one or two plug-on modules to get you started,
and then add modules as you can afford it.

> I heard of a Xilinx starterkit but found it a bit expesive
> for the pour student I am :-(
>
>
> Thanks.
>
> David.
>

Best regards
Tony Burch
http://www.BurchED.com
Low cost FPGA boards, for seriously
powerful prototyping and education





Article: 37944
Subject: ROM die area question
From: brad@tinyboot.com (Brad Eckert)
Date: 26 Dec 2001 16:13:10 -0800
Links: << >>  << T >>  << A >>
Hi all,

I'm going to use block RAM as a 128x32 decoder ROM in a FPGA-based CPU
model. I think if the design were converted to ASIC, the ROM would be
fairly small. Comparing gates, does anyone know about how many 16-bit
registers would fit in the die area used by a typical 128x32 ROM?

--
Brad Eckert

Article: 37945
Subject: NEW: Subscribe To Newsletter
From: ffa-list@chchpoly.ac.nz
Date: Wednesday, 26 Dec 2001 19:18:50 -0600
Links: << >>  << T >>  << A >>
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Article: 37946
Subject: Re: Look for FPGA Starterkit
From: newman5382@aol.com (newman)
Date: 26 Dec 2001 20:21:16 -0800
Links: << >>  << T >>  << A >>
arlington_sade@yahoo.com (arlington) wrote in message news:<63d93f75.0112261036.628fa740@posting.google.com>...
> newman5382@aol.com (newman) wrote in message news:<e6038423.0112250205.2dc10d88@posting.google.com>...
> > "David G." <dgeerinck@yahoo.com> wrote in message news:<3c27e328$0$10318$ba620e4c@news.skynet.be>...
> > > Hi,
> > > I saw this year some basics of vhdl at school.
> > > I'm now looking for some kind of FPGA-starterkit who allows me
> > > to experiment on simple I/O like leds, LCD screens, com-ports,
> > > RAM, ETHERNET,etc that are accesible through a simple electronic board.
> > > 
> > > I heard of a Xilinx starterkit but found it a bit expesive
> > > for the pour student I am :-(
> > > 
> > > 
> > > Thanks.
> > > 
> > > David.
> > 
> > David,
> >   The Spartan IIE board from Nu Horizons is a low cost entry vehicle
> > that can run off the free Webpack software (see URL below). It however
> > does not have all your wish list items, but you may be able to
> > prototype some of the easier ones in.
> >   Is ethernet classified as simple by students nowadays?  If so, 
> > I had better go back to school! 
> > 
> > http://www.nuhorizons.com/EngineeringServices/SpartanIIEBoard.html
> > 
> > Newman
> 
> Where can I buy 10 XC2S200E in the SF Bay Area ? Thanks.

David,
  I realized my handle might have suggested that I was affiliated
with Nu Horizons, but I am not, so I really do not have any idea
where to get 10 XC2S200E devices in the SF Bay area ... sorry  ...
but maybe someone else will respond.  

Newman

Article: 37947
Subject: Re: Innoveda Speedwave vs. Modelsim?
From: newman5382@aol.com (newman)
Date: 26 Dec 2001 20:49:32 -0800
Links: << >>  << T >>  << A >>
> have an eval license and have been learning the tool, though I lost
> the use of the weekend due to a wrong unix host ID and then Win2K
> licensing bogosities. Their platform mix is good. There are some other
> features (code coverage, breakpoints within packages [I think?], some
> platform independence, and peformance analysis, plus presumably
> improved speed) that are of interest but which I wouldn't have under
> speedwave.
> 
.> 
>   Andy Hall
>   andy at gordian dot com
>   Gordian

Andy,
  I've never used Speedwave before, but at least one of the items 
you mentioned (code coverage) is not part of the Modelsim PE edition,
and the SE edition is a bit more expensive.  If you have the Altera
License Subscription, it comes with a decent Modelsim Altera Edition license
that might get you over the hump to give you more time to make a 
bigger decision.

  I've been very happy with using Modelsim PE.  One thing that I 
dont get is why the PLI interface is included with the Verilog version,
and the VHDL Foreign Interface is NOT included with the VHDL version.

  Below is a link to a PE vs SE comparison chart.

http://www.model.com/products/prodcomp.asp

Good luck,
Newman

Article: 37948
Subject: vector reversed in netlist of XC9572XL
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Thu, 27 Dec 2001 11:25:31 +0200
Links: << >>  << T >>  << A >>

Design entry: Verilog
Synthesis: Synplify v6.24
P&R: Xilinx M3.1i SP8 IP4
OS: Sun Solaris 2.6
Technology: Xilinx XC9572XL-5TQ100C

Xilinx tools reverse vectors in netlists generated by themselves.

I have vectors like:

output [1:2] add_ck_a;
output [1:4] dck;
input [4:5] drp_mux_c;

I synthesize my code in Synplify and run Design Manager and
Design Manager generates Verilog netlist in which the vectors
above are reversed:

input [5:4] drp_mux_c;
output [2:1] add_ck_a;
output [4:1] dck;

I know this can be compensated by instantiation.
But is it possible to keep the vector direction during implementation?

Utku

Article: 37949
Subject: Re: Innoveda Speedwave vs. Modelsim?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 27 Dec 2001 10:59:16 +0000
Links: << >>  << T >>  << A >>


newman wrote:

>
>   I've been very happy with using Modelsim PE.  One thing that I
> dont get is why the PLI interface is included with the Verilog version,
> and the VHDL Foreign Interface is NOT included with the VHDL version.
>
>

The reason you get the PLI & not the FLI is that those clever people at
Gateway/Cadence included the PLI from the beginning & so it became part of the
spec when Verilog was IEEE'ed. Hence anyone wanting to claim full Verilog-1995
compliance has to include support for at least PLI 1.0. ModelSIM now supports
the PLI 2.0 (VPI) calls as well; IIRC these were for some time Cadence
proprietary.







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