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Messages from 38050

Article: 38050
Subject: Large ROM question
From: dottavio@ised.it (Antonio)
Date: 2 Jan 2002 23:24:14 -0800
Links: << >>  << T >>  << A >>
Good Morning,
I've to implement a ROM with about 1000 values, 
there are many example where this is achieved initializing the
constant
in the package where the rom is described but this means manually
write
about 1000 values. I know how to read data from a file and assign it
to
a variable but I think this do not produce a ROM when I synthesize the
project, so how I can solve this problem ??


Following there is the code for the package with the rom not filled,
and
the ROMx3 entity and architecture pair.

package SRRC_coeffs is								  
  
  constant ROMx3_WIDTH : INTEGER := 12; 
  subtype  ROMx3_WORD  is STD_LOGIC_VECTOR (1 to ROMx3_WIDTH);
  type     ROMx3_TABLE is array (0 to 1000) of ROMx3_WORD;  
  
  constant ROM_SRRCx3 : ROMx3_TABLE ;

end SRRC_coeffs ;



while the ROM is described by the following :



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.SRRC_coeffs.all; 

entity ROMx3 is 
  port(    reset      : in STD_LOGIC   ;
           clk	      : in STD_LOGIC   ;
    	   fir_sel_1  :	in STD_LOGIC   ;
           fir_sel_0  :	in STD_LOGIC   ;
	   addr_6     : in STD_LOGIC   ;
	   addr_5     : in STD_LOGIC   ;
	   addr_4     : in STD_LOGIC   ;
	   addr_3     : in STD_LOGIC   ;
	   addr_2     : in STD_LOGIC   ;
	   addr_1     : in STD_LOGIC   ;
	   addr_0     : in STD_LOGIC   ;
           SRRC_out   : out ROMx3_WORD);
end; 
 
architecture ROMx3_arch of ROMx3 is 
begin 			
	process(clk, reset)
    begin
        if( reset = '1' ) then
	    SRRC_out <= "000000000000";
       	elsif rising_edge(clk) then
	    SRRC_out <= ROM_SRRCx3( conv_integer(fir_sel_1 & fir_sel_0 &
addr_6 & addr_5 & addr_4 & addr_3 & addr_2 & addr_1 & addr_0) );
    	end if;
    end process;
end ROMx3_arch;



By the way also another problem, I need 3 of these ROM (with different
values and size)
and depending on the data rate I've to take values from one or
another, is a multiplexer
the best and speedest solution or there's another way ??

Article: 38051
Subject: Re: Atmel FPSLIC - Problem with concurrent statements
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Thu, 3 Jan 2002 10:26:19 +0100
Links: << >>  << T >>  << A >>
> I strongly encourage you to be a friend of simulators.  Your problem of
> connecting the microcontroller to the FPGA is a common one.  In the "it
> would be really nice" category, it would be really nice if Atmel (or any
> other microcontroller/microprocessor/DSP/PCI-interface/etc chip vendor)
> would provide bus-functionals model of their chips.  I mean, I've
> written maybe a dozen of these sorts of models.  From your FPGA's point
> of view, all you care about are transactions on the processor's bus.
> The op-codes the processor is executing don't matter.
>
Atmel does better than that :-)
System Designer contains Mentor Seamless Coverification S/W.
There is a full simulation model of the AVR core capable of generating bus
cycles
to the AT40K FPGA in the FPSLIC. No need to write anything at all.

The step to connect the FPGA and the AVR is simple.

1) Compile the HDL code with Modelsim and make sure there are no errors.
2) From System Designer, start the AVR-FPGA interface tool.
    Modelsim is started in the background, and the HDL code is recompiled
and
    all "top-level" modules are extracted.
    You choose the right one, and a window with two columns appear.
    Right column contains all the signals of the FPGA.
    Left column contains all the signals from the AVR+SRAM that can be used
by the FPGA.

    You select one signal from the right and one signal from the left and
press the connect button.
    This is repeated for all signals you want to connect.
    When you exit , make sure that a test harness is generated. (This
creates a simulation
    which instantiates the FPGA and the Seamless Models for the AVR and the
memory.

    You probably need to edit this to create the initial conditions.
    Clock and Reset typically.

3) Start PreLayout verification.
    This starts Seamless, which in its turn starts Modelsim & AVR Studio.
    Load the compiled/assembled AVR code into Studio.
    Open a Wave window in Modelsim, select the signals you want to look at
(or all signals)
    and "run".
    You can now work with AVR studio, like you have connected it to an
emulator.
    Whenever you want to , you can look at the wave window in Modelsim.

Note that with Seamless you need to activate/deactivate Modelsim/Studio.
When Modelsim is stopped, AVR Studio is frozen. When focus is on AVR Studio
Modelsim is not accessible. There are two buttons in special version of AVR
studio
which
1) Can set focus on Modelsim and also
2) Can set focus back to Studio.


It needs to be seen!


There are Seamless Models available for the AT91 as well, but Seamless for
ARM is really expensive.

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.





Article: 38052
Subject: Help on RAM-based Shift Registers
From: "Daniel Yap" <daniu_yap@hotmail.com>
Date: Thu, 3 Jan 2002 18:06:37 +0800
Links: << >>  << T >>  << A >>
Hello,

I need some guideline about how to make a RAM-based Shift Registers for a
FIR filter with 32 Taps. Any idea or clue about doing it? My target
implementation is into the Altera FPGA board.

Thank you.

Daniel



Article: 38053
Subject: PCI Solution: LogiCore?
From: p.van.beek@zes.nl (Peter van Beek)
Date: 3 Jan 2002 03:41:19 -0800
Links: << >>  << T >>  << A >>
Hello everybody,

Currently I am doing some investigation for an appropriate PCI
solution. We want to implement an application that is able to send 32
bits data (with a rate of 25 Mhz) to the PCI bus. This will be done by
means of an FPGA, using the VHDL design flow. We're doing some
evaluation with a Xilinx Spartan II PCI demo board. The VHDL design
flow is supported by WebPACK ISE.

The most common way turns out to be using LogiCore. Unfortunaly
synthesizing LogiCore is not supported by ISE. I don't have much
insight in this process, can somebody tell me what exactly happens
during synthesizing. Also suggestions about which compiler to use are
welcome.

Are there any other options except using LogiCore? Maybe an off the
shelf solution that already contains a stand alone PCI interface
(maybe at other companies).

Best regards,

Peter van Beek
design engineer
Zevenaar Elektronica en Sensoren
Arnhem, The Netherlands
(31)263653393

Article: 38054
Subject: Automatically pipeline combinatorial EDIF
From: "Ashley" <ashley.sutcliffe@celoxica.com>
Date: Thu, 3 Jan 2002 12:34:37 -0000
Links: << >>  << T >>  << A >>
Hi all,
I am looking for a stand-alone tool that can be used to automatically stick
registers into some combinatorial EDIF to make a pipeline. I am interested
in everything from full-blown commercial products to shareware and
university stuff.

Does such a thing exist?
Is it any good?

Thanks

Ashley



Article: 38055
Subject: Re: Automatically pipeline combinatorial EDIF
From: Steven Derrien <sderrien@irisa.fr>
Date: Thu, 03 Jan 2002 14:20:01 +0100
Links: << >>  << T >>  << A >>


Ashley wrote:

> Hi all,
> I am looking for a stand-alone tool that can be used to automatically stick
> registers into some combinatorial EDIF to make a pipeline. I am interested
> in everything from full-blown commercial products to shareware and
> university stuff.

Most synthesis tools have such retiming capabilities, I have been using
synopsys FC-II on virtex devices and it gives faitly good results (got 110MHz
floating point add on virtex-E).
However, I don't know if it can work directly on EDIF netlists, but It might be
worth to try.

I have have also been working on my own implementation of an edif based
standalone placement driven retiming/pipelining tool (written in C++ with a
Edif parser and the LEDA clas library).
Although the whole algorithm works fine, we found that the hardest part of the
job was to be able to have a good estimate of the delays. This is the key point
since it influences the final pipeline performance (FCII had better results
than ours (by 20-30 %)).


> Does such a thing exist?

Ours is not really usable, since the work was stalled (we didn't get the money
to get some student on it). Otherwise, your could have a look to the SIS tools
(works on BLIFF files, but there are EDIF->Bliff converters).

BTW, I find it a very good thing that celoxica finaly starts to look at
automatic retiming and pipelining transformations. I have been surprised to
notice that DK1 wouldn't allow such features.

Good luck

Steven DERRIEN
IRISA, France


>
> Thanks
>
> Ashley


Article: 38056
Subject: Re: Problem/Question about the timing report on Xilinx ISE 4.1
From: hamish@cloud.net.au
Date: 03 Jan 2002 13:41:49 GMT
Links: << >>  << T >>  << A >>
Kenneth <kenneth.lee@terapower.com.hk> wrote:
> Within the design, it is supposed the the timing constraint for 
> the logic using the clk_4x should be 5ns.  However, from the 
> timing report it showed a strange result.  It shows that the 
> requirement is 2.5ns rather than the 5ns, and the timing of 
> the rising edge of the clk_4x signal is very strange too.

> Do anyone have idea about this problem?  Thanks in advance.

Could you post your UCF and possibly also your code?

By the way you might encounter a lot of clock jitter with
this arrangement. Especially with two DCMs in series. The
best approach would be to have a 200MHz clock input pin
and to create 50 and 100MHz clocks from that. If you have 
Virtex-II you could use the CLKFX (synthesized output)
and the CLK2X on a single DCM instead of two in series.


regards
Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38057
Subject: Re: Automatically pipeline combinatorial EDIF
From: Andreas Wassatsch <wassatsch@mppmu.mpg.de>
Date: Thu, 03 Jan 2002 16:18:35 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------9F304DCF373DEA05321FFF60
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Ashley wrote:
> 
> Hi all,
> I am looking for a stand-alone tool that can be used to automatically stick
> registers into some combinatorial EDIF to make a pipeline. I am interested
> in everything from full-blown commercial products to shareware and
> university stuff.

if you are looking for a cell level pipeline implementation ( each comb
cell with it's own pipelineregister ) propably the toolset DYNAMIC can
do this job.

DYNAMIC (
http://www-md.e-technik.uni-rostock.de/forschung/projekte/DynCMOS.htm )
was actually developed as solution for logic synthesis in an asic design
flow based on dynamic circuit technics like TSPC (True Single Phase
Clock Logic).

The implemented mpr algorithmen produce a very fine granular pipeline
structure, which is needed by the dynamic circuit implementation.

Some special optimizations are included to reduce the implementation
costs (area, power,... ) of the pipeline structure.

If you does'nt need such a fine granularity, i think the synopsys
design_compiler for instance can do the job for you by the
pipeline_design command

> Does such a thing exist?
> Is it any good?
> 
> Thanks
> 
> Ashley


Article: 38058
Subject: Re: Q: Cable for multiple LVDS signals - ?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 03 Jan 2002 07:28:05 -0800
Links: << >>  << T >>  << A >>
Alex,

Since LVDS is an IEEE standard, the question is generic: what cable is best
used for IEEE standard LVDS signal levels?

At these speeds I strongly suggest using a circuit simulator (like hspice).
The IBIS models can be directly imported as subcircuits into hspice_2000, which
can then be used to drive uline transmission line models.  There are a number
of coaxial cable models built into hspice, or you can provide your own
parameters using the wline or uline (old, but still supported as a legacy mode
t-line model).

If the simulator does not support hspice, the output waveform can be idealized
as a controlled slope rising and falling edge waveform per the IEEE standard.

This is how all backplane high speed interfaces need to be simulated, or cable
assemblies at these high speeds.

You need to provide a psuedo-random pattern for the data so that you can
evaluate the intersymbol interference, as well as the attenuation of different
frequencies in the data pattern.

Then you may observe the resulting eye pattern at the receive end of the cable.

Austin

Alex Sherstuk wrote:

> What kind of cable can be used to pass multiple LVDS signals at 300MHZ from
> one VIRTEX-E/SPARTAN2E chip to other?
> Who manufactures appropriate cable?
> Is it possible to use CAT6?
> Is there something like flat cable for such purposes?
>
> Thanks,
>    Alex Sherstuk
>     sherstuk@iname.com


Article: 38059
Subject: Re: Cable for multiple LVDS signals - ?
From: "Patrick McGuirk" <pmcguirk@mrcmicroe.com>
Date: Thu, 3 Jan 2002 09:17:45 -0700
Links: << >>  << T >>  << A >>
I have a similar type problem.  However, I need a 'crossover' type cable
with 12 pairs of LVDS signals.  By crossover, I mean the cable contains a
transmit and receive link.  Thus the transmit pairs must crossover to the
receive pairs.  (You cannot have pin 1 connect to pin 1 or else it won't
work)

All I've found so far are RJ-45 crossover type cables, which only have 4
pairs of signals, and the following from Myricom:
http://www.myricom.com/myrinet/cables/m2f-cb.html
The Myricom option appears pricey, and the cables are quite long, but they
do have 18 pairs of signals and a crossover type pinout.

Surely, someone has been using LVDS in Virtex parts and encountered a
similar problem (and solution?).
Thanks,
Pat

Alex Sherstuk <sherstuk@iname.com> wrote in message
news:BtRY7.60967$va.32338765@news2.rdc1.mi.home.com...
> What kind of cable can be used to pass multiple LVDS signals at 300MHZ
from
> one VIRTEX-E/SPARTAN2E chip to other?
> Who manufactures appropriate cable?
> Is it possible to use CAT6?
> Is there something like flat cable for such purposes?
>
> Thanks,
>    Alex Sherstuk
>     sherstuk@iname.com
>
>
>



Article: 38060
Subject: Re: Q: Cable for multiple LVDS signals - ?
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 03 Jan 2002 17:32:25 +0100
Links: << >>  << T >>  << A >>
"Alex Sherstuk" <sherstuk@iname.com> writes:

> What kind of cable can be used to pass multiple LVDS signals at 300MHZ from
> one VIRTEX-E/SPARTAN2E chip to other?
> Who manufactures appropriate cable?
> Is it possible to use CAT6?
> Is there something like flat cable for such purposes?

You are likely to get problems with skew due to the different lenght
of the various pairs in the cable. 

SCI is using LVDS (actually the IEEE LVDS was created as a part of the
SCI standardization). Dolphin (www.dolphinics.no) have been shipping
SCI interfaces for several years which are running at 667 MBytes/s
(167MHz clock sampled at both edges, 16 data pairs, one flag pair)
over 5m LVDS cables. These are manufactured by Madison, 3M, and FCI.
FCI have some neat flat flexprint cables.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 38061
Subject: Re: Virtex-2 maximum clock speed
From: Kevin Brace <nospamtomekevinbraceusenet@nospamtomehotmail.com>
Date: Thu, 03 Jan 2002 10:44:30 -0600
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> 
> 
> Austin,
> 
> If that's so - and I agree - then why isn't FPGA Editor part of the WebPACK tool set ?
> 
> One thing you missed out - AFAIK FPGA Editor is the only way of constructing hard
> marcos ?

        I will also like to see FPGA Editor included with ISE WebPACK.
Perhaps, Xilinx's excuse for not including FPGA Editor is something
like, "ISE WebPACK is a beginner's tool, and FPGA Editor is too advanced
for ISE WebPACK."
Even if FPGA Editor is included with ISE WebPACK, I doubt most users
will use it, but I don't think it will hurt to include it.
Looking at ISE WebPACK's directory where the executables are stored, I
found a small (20K byte) program called fpga_edline.exe.
What does this program do?




Kevin Brace (don't respond to me directly, respond within the newsgroup)

Article: 38062
Subject: Re: Atmel FPSLIC - Problem with concurrent statements
From: Andy Peters <andy@exponentmedia.nospam.com>
Date: Thu, 03 Jan 2002 18:01:55 GMT
Links: << >>  << T >>  << A >>
Ulf,

that's cool! :)

--andy

Ulf Samuelsson wrote:

>>I strongly encourage you to be a friend of simulators.  Your problem of
>>connecting the microcontroller to the FPGA is a common one.  In the "it
>>would be really nice" category, it would be really nice if Atmel (or any
>>other microcontroller/microprocessor/DSP/PCI-interface/etc chip vendor)
>>would provide bus-functionals model of their chips.  I mean, I've
>>written maybe a dozen of these sorts of models.  From your FPGA's point
>>of view, all you care about are transactions on the processor's bus.
>>The op-codes the processor is executing don't matter.
>>
>>
> Atmel does better than that :-)
> System Designer contains Mentor Seamless Coverification S/W.
> There is a full simulation model of the AVR core capable of generating bus
> cycles
> to the AT40K FPGA in the FPSLIC. No need to write anything at all.
> 
> The step to connect the FPGA and the AVR is simple.
> 
> 1) Compile the HDL code with Modelsim and make sure there are no errors.
> 2) From System Designer, start the AVR-FPGA interface tool.
>     Modelsim is started in the background, and the HDL code is recompiled
> and
>     all "top-level" modules are extracted.
>     You choose the right one, and a window with two columns appear.
>     Right column contains all the signals of the FPGA.
>     Left column contains all the signals from the AVR+SRAM that can be used
> by the FPGA.
> 
>     You select one signal from the right and one signal from the left and
> press the connect button.
>     This is repeated for all signals you want to connect.
>     When you exit , make sure that a test harness is generated. (This
> creates a simulation
>     which instantiates the FPGA and the Seamless Models for the AVR and the
> memory.
> 
>     You probably need to edit this to create the initial conditions.
>     Clock and Reset typically.
> 
> 3) Start PreLayout verification.
>     This starts Seamless, which in its turn starts Modelsim & AVR Studio.
>     Load the compiled/assembled AVR code into Studio.
>     Open a Wave window in Modelsim, select the signals you want to look at
> (or all signals)
>     and "run".
>     You can now work with AVR studio, like you have connected it to an
> emulator.
>     Whenever you want to , you can look at the wave window in Modelsim.
> 
> Note that with Seamless you need to activate/deactivate Modelsim/Studio.
> When Modelsim is stopped, AVR Studio is frozen. When focus is on AVR Studio
> Modelsim is not accessible. There are two buttons in special version of AVR
> studio
> which
> 1) Can set focus on Modelsim and also
> 2) Can set focus back to Studio.
> 
> 
> It needs to be seen!
> 
> 
> There are Seamless Models available for the AT91 as well, but Seamless for
> ARM is really expensive.
> 
> --
> Best Regards
> Ulf at atmel dot com
> These comments are intended to be my own opinion and they
> may, or may not be shared by my employer, Atmel Sweden.
> 
> 
> 
> 
> 



Article: 38063
Subject: Re: Virtex-2 maximum clock speed
From: Andy Peters <andy@exponentmedia.nospam.com>
Date: Thu, 03 Jan 2002 18:02:57 GMT
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:

> 
> Austin Lesea wrote:
> 
> 
>>The FPGA editor is not the real view of the chip (obviously).   I do agree that it
>>is all you need to construct a really high performance working design (we use it
>>all of the time to verify features functions and specifications).
>>
>>Austin
>>
>>
> 
> Austin,
> 
> If that's so - and I agree - then why isn't FPGA Editor part of the WebPACK tool set ?

Because the higher-ups said that they've gotta charge for something?

--a


Article: 38064
Subject: Re: asic vs. fpga
From: klonsky@hotmail.com (Noel Klonsky)
Date: 3 Jan 2002 10:09:30 -0800
Links: << >>  << T >>  << A >>
...and flexibility

Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3C337878.CF8F73F3@dplanet.ch>...
> The difference is simple. Development time and cost.
> Look up the various FPGA manufacturers, altera, xilinx, and so on,
> they explain that in detail.
> 
> Rene
> -- 
> Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> 
> Matthias Weber wrote:
> > 
> > hi,
> > 
> > i am searching for a link, book, university lessons explaining the architecture of asic and fpga and their differences.
> > 
> > thanks,
> > 
> > matthias

Article: 38065
Subject: Re: PCI Solution: LogiCore?
From: "clevin1234" <clevin1234@home.com>
Date: Thu, 03 Jan 2002 18:10:20 GMT
Links: << >>  << T >>  << A >>
You might want to check out QuickLogic's PCI Solutions.  They offer FPGA's
with embedded PCI cores for both target and master/target 32 bit PCI
applications.  The web site is www.quicklogic.com.


"Peter van Beek" <p.van.beek@zes.nl> wrote in message
news:b11cef2.0201030341.631c75e0@posting.google.com...
> Hello everybody,
>
> Currently I am doing some investigation for an appropriate PCI
> solution. We want to implement an application that is able to send 32
> bits data (with a rate of 25 Mhz) to the PCI bus. This will be done by
> means of an FPGA, using the VHDL design flow. We're doing some
> evaluation with a Xilinx Spartan II PCI demo board. The VHDL design
> flow is supported by WebPACK ISE.
>
> The most common way turns out to be using LogiCore. Unfortunaly
> synthesizing LogiCore is not supported by ISE. I don't have much
> insight in this process, can somebody tell me what exactly happens
> during synthesizing. Also suggestions about which compiler to use are
> welcome.
>
> Are there any other options except using LogiCore? Maybe an off the
> shelf solution that already contains a stand alone PCI interface
> (maybe at other companies).
>
> Best regards,
>
> Peter van Beek
> design engineer
> Zevenaar Elektronica en Sensoren
> Arnhem, The Netherlands
> (31)263653393



Article: 38066
Subject: Re: PCI Solution: LogiCore?
From: "Colin Cook" <colin@cook-tech.com>
Date: Thu, 3 Jan 2002 15:53:10 -0700
Links: << >>  << T >>  << A >>
Peter,

First of all am I to assume that you purchased the Spartan II demo without a
PCI license. If so, you will need to buy it (2K for a one time license).
The PCI license is what allows you to generate the PCI edif file for your
design flow using the Xilinx web site.

Second ISE does support LogiCore, but WebPACK may not, I don't use WebPACK
so I am not sure.
LogiCore is just a general name Xilinx uses for all cores they support.

Now assuming that you purchased the PCI core, lets talk about your
application.
Getting a sustained 25Mhz data rate throughput on a 33Mhz bus is not a slam
dunk. If there are others devices on the bus your in real trouble. So lets
assume that the bus is yours alone. You will need to do burst transfers,
Xilinx's core supports this so your in luck. Once you get the PCI core
license, Xilinx will give you all sorts of documentation to show you how to
do bursts. To get 25Mhz I think you will need to do at lease 16 data
transfers per cycle.

Good luck.


Colin Cook
Cook Technologies
Embedded System Design Services.


Peter van Beek <p.van.beek@zes.nl> wrote in message
news:b11cef2.0201030341.631c75e0@posting.google.com...
> Hello everybody,
>
> Currently I am doing some investigation for an appropriate PCI
> solution. We want to implement an application that is able to send 32
> bits data (with a rate of 25 Mhz) to the PCI bus. This will be done by
> means of an FPGA, using the VHDL design flow. We're doing some
> evaluation with a Xilinx Spartan II PCI demo board. The VHDL design
> flow is supported by WebPACK ISE.
>
> The most common way turns out to be using LogiCore. Unfortunaly
> synthesizing LogiCore is not supported by ISE. I don't have much
> insight in this process, can somebody tell me what exactly happens
> during synthesizing. Also suggestions about which compiler to use are
> welcome.
>
> Are there any other options except using LogiCore? Maybe an off the
> shelf solution that already contains a stand alone PCI interface
> (maybe at other companies).
>
> Best regards,
>
> Peter van Beek
> design engineer
> Zevenaar Elektronica en Sensoren
> Arnhem, The Netherlands
> (31)263653393



Article: 38067
Subject: Re: A Fast counter in VHDL?
From: "Jason Berringer" <jberringer@trace-logic.com>
Date: Thu, 3 Jan 2002 18:23:23 -0500
Links: << >>  << T >>  << A >>
 >    Why don't you post your code so that we can all take a look at it.  It
> will help us diagnose your problem.

The entire circuit is a frequency counter which is designed to measure
frequencies in the range of 50 kHz to 350 kHz. I have two identical banks of
two counters set up(while one bank is being held with it's counts to be
output the other bank is counting). One counter to count the frequency to be
measured and one counter to count the 100MHz reference pulses. Every 1 kHz
an interrupt is genereated and both values are spit out to an awaiting
processor to do the math/filtering/etc on the data. I hope that makes sense.
As you can see the 100MHz reference counter is the key to everything so I
have to make sure this is working at the desired frequency. The code has
about 6 different blocks in total, here is the code for the counter:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
 generic(width : integer := 32);
 port(
  clk   : in  std_logic;
  cnt_clr  : in  std_logic;
  cnt_enable : in  std_logic;
  reset  : in  std_logic;
  cnt_out  :   out std_logic_vector(width-1 downto 0)
  );
end counter;

architecture RTL_counter of counter is

signal countL : std_logic_vector(cnt_out'range);

begin

P1: process (reset, cnt_clr, clk, cnt_enable) begin
 if (reset = '1' or cnt_clr = '0') then
  countL <= (others => '0');
 elsif (rising_edge(clk)) then
  if (cnt_enable = '1') then
   countL <= countL + 1;
  end if;
 end if;
end process;

cnt_out <= countL;

end RTL_counter;




Article: 38068
Subject: Re: PCI Solution: LogiCore?
From: "Austin Franklin" <austin@dark98room.com>
Date: Thu, 3 Jan 2002 18:53:48 -0500
Links: << >>  << T >>  << A >>
>. We want to implement an application that is able to send 32
> bits data (with a rate of 25 Mhz) to the PCI bus.

What exactly do you mean by that?  How long is your burst, is it
sustained...forever?  Do you really mean 100M Bytes/second, which is what 32
bits at 25Mhz is...

I believe you will be very hard pressed to get a sustained data rate of 100M
Bytes/sec on a 33Mhz, 32 bit PCI bus...unless you are the only device on the
bus.  You might want to consider using a 64 bit PCI bus, or 66Mhz...





Article: 38069
Subject: Spartan-IIE interfacing issues
From: doug@frombob.to (Doug)
Date: 3 Jan 2002 17:07:06 -0800
Links: << >>  << T >>  << A >>
I need to interface some old-fashioned 5V logic to a Spartan-IIE FPGA,
which has 3.3V I/O.

I know I could use something like a 74LVX3245, but apparently it can
be safely done with resistors as well.  In the appnote "Spartan-IIE
Family:  Frequently Asked Questions" (Xilinx document #FAQ100), it
says:

"The Spartan-IIE is 3.3V I/O compatible and will only support 5.0V
I/Os when an external pull-up resistor is used."

...and that's all the info I've been able to find so far.

Before I proceed, I would like to see more specific recommendations
(preferably from Xilinx!) about how best to do this.  Is anyone out
there aware of any other documents detailing Xilinx' recommended
method, specifically for the Spartan-IIE family?

Thanks in advance,

Doug Jones

Article: 38070
Subject: Re: A Fast counter in VHDL?
From: Peter Alfke <palfke@earthlink.net>
Date: Fri, 04 Jan 2002 04:18:59 GMT
Links: << >>  << T >>  << A >>
Jason,
if I understand you right, your frequency counter has a time base of ~1 ms. You
count the unknown frequency of 50 to 350 kHz, and also the time-base frequency
of 100 MHz, giving you a timing uncertainty of only 10 ns.
I would ( and perhaps you do) start the 100 MHz counter upon receiving a rising
edge of your unknown frequency, and also stop the time base upon receiving a
similar rising edge. The frequency can then be calculated by dividing the
event-count value by the time-base value. This gives you good resolution of one
part in 100 000, inspite of the short measurement time and the low frequency
being measured.
A 16 or 17-bit synchronous counter, using the free carry chain, will surely run
at >100 MHz. But if you do have a problem, you can build a ripple counter and
wait a few ns after the end of the count period. That's how I have built 400
MHz counters in XC4000XL, and plan to build a 1 GHz counter in Virtex-II.
There are some additional tricks that will be the subject of an upcoming app
note.

Peter Alfke, Xilinx Applications
==============================
Jason Berringer wrote:

>  >    Why don't you post your code so that we can all take a look at it.  It
> > will help us diagnose your problem.
>
> The entire circuit is a frequency counter which is designed to measure
> frequencies in the range of 50 kHz to 350 kHz. I have two identical banks of
> two counters set up(while one bank is being held with it's counts to be
> output the other bank is counting). One counter to count the frequency to be
> measured and one counter to count the 100MHz reference pulses. Every 1 kHz
> an interrupt is genereated and both values are spit out to an awaiting
> processor to do the math/filtering/etc on the data. I hope that makes sense.
> As you can see the 100MHz reference counter is the key to everything so I
> have to make sure this is working at the desired frequency. The code has
> about 6 different blocks in total, here is the code for the counter:
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity counter is
>  generic(width : integer := 32);
>  port(
>   clk   : in  std_logic;
>   cnt_clr  : in  std_logic;
>   cnt_enable : in  std_logic;
>   reset  : in  std_logic;
>   cnt_out  :   out std_logic_vector(width-1 downto 0)
>   );
> end counter;
>
> architecture RTL_counter of counter is
>
> signal countL : std_logic_vector(cnt_out'range);
>
> begin
>
> P1: process (reset, cnt_clr, clk, cnt_enable) begin
>  if (reset = '1' or cnt_clr = '0') then
>   countL <= (others => '0');
>  elsif (rising_edge(clk)) then
>   if (cnt_enable = '1') then
>    countL <= countL + 1;
>   end if;
>  end if;
> end process;
>
> cnt_out <= countL;
>
> end RTL_counter;


Article: 38071
Subject: Re: Actel 54sx series clock doubler
From: rk <stellare@nospamplease.erols.com>
Date: Thu, 03 Jan 2002 23:31:53 -0500
Links: << >>  << T >>  << A >>
john wrote:

> I am working with and ACTEL 54sx series device and I'd like to make a
> traditional xor gate clock doubler. I am using the Viewlogic schematic
> capture tool.
> 
>              -------          ---
>          ---| Delay |--------|   |
>          |   -------         |xor|-------------
>   clk -----------------------|   |
>                               ---
> 
> What i'm looking for is an attribute setting that will prevent the
> logic compiler from optimizing away a series connected gate string...

Attach a PRESERVE to the net on the output of the gate that you wish to
"preserve."  That will tell the compiler not to optimize it away.

Alternatively, you can use the BUFD component in the library.  There's
an inverting version of that too, INVD.

Of course, with an asynchronous circuit like this, you're on your own
...

-- rk
Just an OldEngineer

Article: 38072
Subject: Re: asic vs. fpga
From: Peter Alfke <palfke@earthlink.net>
Date: Fri, 04 Jan 2002 04:36:37 GMT
Links: << >>  << T >>  << A >>


Matthias Weber wrote:

> hi,
>
> i am searching for a link, book, university lessons explaining the architecture of asic and fpga and their differences.
>

Matthias, the differences are not so much in the architecture as in the economics.
If you have infinite amounts of money and time, and never make a mistake and never intend to change your design, then
ASICs are great ( Low price per chip, high performance, low power).
But this comes at a high price in non-recurring engineering charges (  $ 1 000 000 for a state-of-the art big circuit )
and it takes months to get the first chip. And you must always order and pay for a specific quantity, and never make a
mistake or a change.

That's why more and more designers prefer the FPGA solution that does not have these high up-front costs and long waiting
time, and can be bought in any quantity at any time, and be modified ad infinitum.
State-of-the-art ASICs have very high NRE costs, while old-fashioned ASICs are cheaper, but offer no real performance
advantage over FPGAs.
I admit to being biased, but the trend is clearly in favor of FPGAs.  :-)

Gutes Neues Jahr !

Peter Alfke, Xilinx Applications


Article: 38073
Subject: ACTEL SX-A serie and ROM implementation ...
From: meng.engineering@bluewin.ch (Markus Meng)
Date: 3 Jan 2002 22:58:17 -0800
Links: << >>  << T >>  << A >>
Hi all,

for a type II PCMCIA card we need something that is operational
after power up. We need to implement attribute memory for
the card recognition. One solution is to implement the required info
in a small ROM in the ACTEL antifuse. Does somebody has experience
of what a 'byte' costs in the SX-A serie?

By the way actel has some nice FPGA's in the FBGA package. The 256FBGA is
really small and well suited for PCMCIA cards. Does Xilinx or Altera
has this option also?

markus

Article: 38074
Subject: conv_integer problem ???
From: dottavio@ised.it (Antonio)
Date: 3 Jan 2002 23:35:09 -0800
Links: << >>  << T >>  << A >>
I've the problem that with the following code I can't obtain an output
from the ROM when the address is all zeroes, pratically I obtain UUU
instead of a value 49E located in ROM_SRRCx3(0), may be that
conv_integer is not working for this value ?? What is the solution ??



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;  
use ieee.std_logic_arith.all;
use std.textio.all;	
use work.SRRC_coeffs.all; 

entity ROMx3 is 
  port(reset      : in STD_LOGIC   ;
  	   clk		  : in STD_LOGIC   ;
  	   --load		  : in STD_LOGIC   ;
  	   fir_sel    : in STD_LOGIC_VECTOR(2 downto 0);	 
	   addr_6     : in STD_LOGIC   ;
	   addr_5     : in STD_LOGIC   ;
	   addr_4     : in STD_LOGIC   ;
	   addr_3     : in STD_LOGIC   ;
	   addr_2     : in STD_LOGIC   ;
	   addr_1     : in STD_LOGIC   ;
	   addr_0     : in STD_LOGIC   ;
	   
	   SRRC_out   : out STD_LOGIC_VECTOR(11 downto 0));
end; 
 
architecture ROMx3_arch of ROMx3 is 	  
begin 			
  process(clk, reset)
  begin
    if( reset = '1' ) then
    	SRRC_out <= "000000000000";
    elsif falling_edge(clk) then
	    SRRC_out <= ROM_SRRCx3( conv_integer(fir_sel & addr_6 & addr_5 &
addr_4 & addr_3 & addr_2 & addr_1 & addr_0) );
    end if;
  end process;
end ROMx3_arch;



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