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Messages from 38125

Article: 38125
Subject: Re: how do i program a Spartan FPGA
From: "S. Ramirez" <sramirez@cfl.rr.com>
Date: Sun, 06 Jan 2002 12:41:53 GMT
Links: << >>  << T >>  << A >>

"Nachiket Kapre" <nachikap@yahoo.com> wrote in message
news:eadce17c.0201052213.146ca927@posting.google.com...
> Hello,
>  I am currently in a project which uses Spartan FPGA and need to know
> how to program it. Can I make my own version of the Parallel Cable III
> and use it to program via the JTAG pins(i have a schematic from the
> xilinx website). Or if I decide to use a Serial PROM ,how can i get it
> programmed?...is a ciruit schematic avaiable for the same? Or are
> there any other programming options that i havent considered?
>
> Reply soon.

Contact your local, friendly Xilinx FAE.  S(h)e often has the equipment to
do this and could lend it to you, and s(h)e can answer all the questions
above for you.
Simon N. Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA



Article: 38126
Subject: Re: Suitability of Atmel for project?
From: Ashok Mahadevan <ashokm1@earthlink.net>
Date: Sun, 06 Jan 2002 15:29:41 GMT
Links: << >>  << T >>  << A >>
Hmmmm, The Atmel AT90S8515 and AT90S8535 are almost fully pin-compatble
with the 40-pin 8051, so you may want to look at these parts. Note that
these are only micros, not opcode compatible with the 8051, and do not
have any configurable logic in them.

Since they can be clocked at 8MHz and effectively take lot less time to
execute instuctions similar to those on the 8051, you may be able to do
some of the "glue and a couple of other oddball things" that you mention
in the software? You will find it next to impossible to get a drop-in
replacement to do what you want.

-Ashok

Stout wrote:

> My company has a large inventory of boards that have a 40 pin DIP
> socket that was originally meant for another chip.  My new need is to
> run an equivalent (opcode compatable) 8051 @ 5 Mhz plus some glue and
> a couple of other oddball things.  Ideally I would like to use a
> device that is also a 40 pin DIP so that I can use the boards.
>
> I am brand-new to the PLD/FPGA arena but have about 20 years of EE
> experience.
>
> After a quick search around the web I found the Atmel ATV2500, a 40
> pin DIP PLD (data sheet is at
> http://www.atmel.com/atmel/acrobat/doc0249.pdf).  Since I'm so new to
> this I have no idea of how to estimate if this thing is remotely
> capable of meeting my logic requirements.  Any input, URLs, etc. is
> appreciated.  TIA.
>
> - Stout




Article: 38127
Subject: scalling ammulator problem
From: "Daniel Yap" <daniu_yap@hotmail.com>
Date: Mon, 7 Jan 2002 00:51:43 +0800
Links: << >>  << T >>  << A >>
Can anyone give some guideline on how to design a scalling ammulator from 32
Taps Coef. to 10 bits output for a 8-bits 32 taps FIR filter?



Article: 38128
Subject: 4 fpga configuration using 1 EPROM
From: Nahum Abramovitch <nospam@newsranger.com>
Date: Sun, 06 Jan 2002 18:17:00 GMT
Links: << >>  << T >>  << A >>
Hi.
I have 2 questions about fpgas configuration - in particular xilinx.
I design a board with 4 different fpga's.
I do'nt have a processor on the board.
I do have connection to PC parallel port .

1. Is there a possibility that the fpga's will have one shared
EPROM for the configuration or must I have an EPROM per fpga ?

2. Can I use PC parallel port for fpga configuration ?

ThankX,
Nahum.



Article: 38129
Subject: Re: Suitability of Atmel for project?
From: i_never_check_this@hotmail.com (Stout)
Date: 6 Jan 2002 10:44:07 -0800
Links: << >>  << T >>  << A >>
Ashok Mahadevan <ashokm1@earthlink.net> wrote in message news:<3C386D44.D47E1C4B@earthlink.net>...
> Hmmmm, The Atmel AT90S8515 and AT90S8535 are almost fully pin-compatble
> with the 40-pin 8051, so you may want to look at these parts. Note that
> these are only micros, not opcode compatible with the 8051, and do not
> have any configurable logic in them.

OK thanks for the info.  The current boards were laid out for the
AT90S8515 and have functioned just fine within their original design
parameters.  We now have need to glue some extra circuits into the mix
(don't you just love feature creep waaaaaay into the life of the
product?), ergo the desire to include the 8051 core (to do what the
AT90S8515 was doing) along with the PLD features for the new
requirements.  The legacy app for the AT90S8515 only used about 5 of
the I/O pins so we have lots of unused pins; what we need is some PLD
type of functionality to interface with the new outside circuitry that
marketing told the customer we could do with no hassle. :)  Anyway the
AT90S8515 won't handle it by itself (too slow), so it looks like a
daughter board is in our future, or maybe just a complete respin to
include the new peices.  The boards are not terribly expensive but
it's not my decision <sigh>, I will just have to present the
alternatives.

There is also a possibility of using this board to replace a 6805
based board in the future, as we try to consolidate many products into
fewer parts which are hopefully configurable to look like whatever
they are replacing.  We could of course port the 6805 app to the 8051
(or whatever we wind up using), but again it would be really slick if
we could use a part that we could run a 6805 core in and simply
download it's "personality" right before we put the part number
sticker on it.  Maybe I'm just dreaming of making life easier than it
should be. :)

Thanks to everybody for your help!

- Stout

Article: 38130
Subject: Re: Suitability of Atmel for project?
From: i_never_check_this@hotmail.com (Stout)
Date: 6 Jan 2002 10:52:20 -0800
Links: << >>  << T >>  << A >>
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3C3813DE.4B9D@designtools.co.nz>...
 
>  What chip did the 40 pin socket target ?

Atmel AT90S8515.  It worked just fine but now we need to add some
other stuff including some high speed serial interfaces that the
AT90S8515 is too slow to handle by bit-banging but the overall
throughput is slow enough that the AT90S8515 can handle the data, thus
the need for some specialized hardware to handle the interface. 
There's also some other odds and ends but the real requirement that is
pushing me towards new hardware is the interfaces.

>  Do you mean you hope to Implement a 8051 SoftCore+Other things 
> in a ATF2500 ?
> The answer is NO. ( not by a long shot :)

OK that was easy. :)  In the future we may want to implement a 6805
core in order to replace another board (6805 based) and thus only have
to stock 1 part, just download different "personality" to make it look
like whatever legacy board it is replacing.

>  If you don't have the 8051, and these PCBs are 'really expensive', then
> I'd look at a daughter PCB using TQFP44 89S52/53 (& up) + TQFP ATF1502 
> - both are In System Programmable, and low cost.

Since the original AT90S8515 board is not terribly expensive I'm
probably looking at a respin.  I really like the idea of one common
board that we can configure as needed at production time (with 8051 or
6805 core) but I need to learn a whole lot more about costs,
capabilities, etc. in order to get close to making a case for it.

Thanks for the info!

- Stout

Article: 38131
Subject: Re: Suitability of Atmel for project?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 07 Jan 2002 08:28:58 +1300
Links: << >>  << T >>  << A >>
Stout wrote:
> 
> Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3C3813DE.4B9D@designtools.co.nz>...
> 
> >  What chip did the 40 pin socket target ?
> 
> Atmel AT90S8515.  It worked just fine but now we need to add some
> other stuff including some high speed serial interfaces that the
> AT90S8515 is too slow to handle by bit-banging but the overall
> throughput is slow enough that the AT90S8515 can handle the data, thus
> the need for some specialized hardware to handle the interface.
> There's also some other odds and ends but the real requirement that is
> pushing me towards new hardware is the interfaces.

 The move 90S -> 80C51 is not uncommon, esp as the AVR's have a
'thin' offering in code size vs package - so if you are not very
certain how big your project budget is, over life, the 80C51 is
much safer.

 In a 44 pin package, the 80C51 comes in all sizes from 4 thru 96K of
Code.

 Take a look at our Web overview page - you may find an 80C51 variant
with close to what you need already in HW.
 http://www.designtools.co.nz/overview.htm

 Can you detail more on the 'high speed serial interface' ?

> 
> >  Do you mean you hope to Implement a 8051 SoftCore+Other things
> > in a ATF2500 ?
> > The answer is NO. ( not by a long shot :)
> 
> OK that was easy. :)  In the future we may want to implement a 6805
> core in order to replace another board (6805 based) and thus only have
> to stock 1 part, just download different "personality" to make it look
> like whatever legacy board it is replacing.
> 
> >  If you don't have the 8051, and these PCBs are 'really expensive', then
> > I'd look at a daughter PCB using TQFP44 89S52/53 (& up) + TQFP ATF1502
> > - both are In System Programmable, and low cost.
> 
> Since the original AT90S8515 board is not terribly expensive I'm
> probably looking at a respin.  I really like the idea of one common
> board that we can configure as needed at production time (with 8051 or
> 6805 core) but I need to learn a whole lot more about costs,
> capabilities, etc. in order to get close to making a case for it.

 It will ALWAYS be more expensive to do a uC in a SRAM FPGA, than as
a Std core. There is a HUGE silicon ratio between a configurable SRAM
FPGA, and a hard wired uC. FPGAs are more 'shrunk', but don't forget
to add the configuration memory.

 Even the FLASH C51's are edging under $1, with OTP and ROM one well
under $1 (volume)

 Where the uC SoftCore makes sense, is when the uC is a small portion of
the
LOGIC budget, and the FPGA was needed anyway, for other (significant)
tasks.
 Then, 'it was there anyway' bean-counting can apply.
 
 I also have yet to see a WDOG analysis for a soft core device.
It can be hard enough keeping an embedded system 'up' with a std uC,
but when you add the chance a Opcode might no longer be working, how 
do you cover that ?
 As a minimum, a call to a BIST to check 'core ok' would be indicated.

 Soft cores also commit you to a much lower (and moving) Vcc.

- jg

-- 
======= 80x51 Tools & IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 38132
Subject: Re: A Fast counter in VHDL?
From: "Jason Berringer" <jberringer@trace-logic.com>
Date: Sun, 6 Jan 2002 14:58:01 -0500
Links: << >>  << T >>  << A >>
Hello All,

Just wanted to say thanks for the valuabel input. Thanks to the advice, some
tinkering, and a better understanding of "How not to trust what the tools
tell you" I managed to get a new value for my counter speed, now reported at
151 MHz, plenty for what I need.

Thanks again

Jason

"Jason Berringer" <jberringer@trace-logic.com> wrote in message
news:IJ5Z7.12027$A67.3131096@news20.bellglobal.com...
> >    Why don't you post your code so that we can all take a look at it.
It
> > will help us diagnose your problem.
>
> The entire circuit is a frequency counter which is designed to measure
> frequencies in the range of 50 kHz to 350 kHz. I have two identical banks
of
> two counters set up(while one bank is being held with it's counts to be
> output the other bank is counting). One counter to count the frequency to
be
> measured and one counter to count the 100MHz reference pulses. Every 1 kHz
> an interrupt is genereated and both values are spit out to an awaiting
> processor to do the math/filtering/etc on the data. I hope that makes
sense.
> As you can see the 100MHz reference counter is the key to everything so I
> have to make sure this is working at the desired frequency. The code has
> about 6 different blocks in total, here is the code for the counter:
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity counter is
>  generic(width : integer := 32);
>  port(
>   clk   : in  std_logic;
>   cnt_clr  : in  std_logic;
>   cnt_enable : in  std_logic;
>   reset  : in  std_logic;
>   cnt_out  :   out std_logic_vector(width-1 downto 0)
>   );
> end counter;
>
> architecture RTL_counter of counter is
>
> signal countL : std_logic_vector(cnt_out'range);
>
> begin
>
> P1: process (reset, cnt_clr, clk, cnt_enable) begin
>  if (reset = '1' or cnt_clr = '0') then
>   countL <= (others => '0');
>  elsif (rising_edge(clk)) then
>   if (cnt_enable = '1') then
>    countL <= countL + 1;
>   end if;
>  end if;
> end process;
>
> cnt_out <= countL;
>
> end RTL_counter;
>
>
>



Article: 38133
Subject: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
From: Mike Treseler <tres@tc.fluke.com>
Date: Sun, 06 Jan 2002 13:33:34 -0800
Links: << >>  << T >>  << A >>
Orlls wrote:

> after i compile xilinx lib, there is not 
>  simprims_ver/xilinxcorelib_ver /unisims_ver 
> directory. why?

With default options, vcom results go into
the library directory "work" in the current directory.
Read the options on vcom for other names and paths.

       -- Mike Treseler

Article: 38134
Subject: Re: 4 fpga configuration using 1 EPROM
From: Peter Alfke <palfke@earthlink.net>
Date: Sun, 06 Jan 2002 22:32:47 GMT
Links: << >>  << T >>  << A >>
Nahum, in the rare case where all 4 FPGAs are the same type and have
the same configuration, you need only one configuration source. Use one
FPGA as the master, the others as slaves, interconnect all CCLKs and
Din's and that's it.

If the FPGAs differ in type or in configuration content, you can either
configure each independently with its own SPROM, or you can concatenate
the FPGAs and store the combined configurations in one ( or multiple
concatenated) SPROM(s)
The details differ between XC4000 / Spartan on one side, and Virtex /
Spartan-II on the other side.

Also think about whether or not it is mandatory that all four FPGAs
become alive simultaneously.
Reed th app notes!

Peter Alfke, Xilinx Applications
=================================
Nahum Abramovitch wrote:

> Hi.
> I have 2 questions about fpgas configuration - in particular xilinx.
> I design a board with 4 different fpga's.
> I do'nt have a processor on the board.
> I do have connection to PC parallel port .
>
> 1. Is there a possibility that the fpga's will have one shared
> EPROM for the configuration or must I have an EPROM per fpga ?
>
> 2. Can I use PC parallel port for fpga configuration ?
>
> ThankX,
> Nahum.


Article: 38135
Subject: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
From: Przemyslaw Wegrzyn <czajnik@czajsoft.pl>
Date: Mon, 07 Jan 2002 00:15:57 +0100
Links: << >>  << T >>  << A >>
Hello !

Can someone help me ? I can't find that simple information on  Xilinx
website.
I'm looking for some whitepaper describing main differences between
architectures listed in subject.
I'm new to Xilinx FPGA's, and comparing them by myself is a little
confusing to me.

I'm going to buy some Xilinx evaluation board, but at this time I don't
know if I Virtex or Spartan
will suit my needs better. I was looking for some "selector's guide" on
xilinx web page, with no luck..

-=Czaj-nick=-






Article: 38136
Subject: Celoxica DK1 and Handel C
From: johnt246@yahoo.com
Date: Sun, 06 Jan 2002 16:17:12 -0800
Links: << >>  << T >>  << A >>
Halo all,
  Please email me somebody who use Celoxica DK1 and Handel C full 
working version.

Best Regards


Article: 38137
Subject: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
From: Orlls <sf@ikre.oiret>
Date: Sun, 6 Jan 2002 16:39:03 -0800
Links: << >>  << T >>  << A >>
how and where do i change the vcom option?

Article: 38138
Subject: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
From: Peter Alfke <palfke@earthlink.net>
Date: Mon, 07 Jan 2002 02:11:23 GMT
Links: << >>  << T >>  << A >>
Sorry for the confusion, it's really our fault;

There are two basic architectures, XC4000 and Viretex.

XC4000 is the older one, and it also comes under the name Spartan.
The suffix -XL means 3.3 V.
There are subtle differences between XC4000 and Spartan ( Spartan is
cheaper and has fewer package options)
Contemplate only the -XL versions, since 5-V is now a dead-end street.

The newer architecture is Virtex, and it also comes under the name
Spartan-II ( same difference as above).

Virtex-II is a sbstantial enhancement over Virtex, better clock
management, bigger RAM, multipliers, and more versatile I/O.

So, the lowest denominator is Spartan-XL, and the highst is Virtex-II.
And as they say over here:
You get what you pay for.
(The more sophisticated and faster parts are more exepensive)

Hope this helps.
Greetings to Poland. I once spent a week in Krakow...

Peter Alfke, Xilinx Applictions
===========================

Przemyslaw Wegrzyn wrote:

> Hello !
>
> Can someone help me ? I can't find that simple information on  Xilinx
> website.
> I'm looking for some whitepaper describing main differences between
> architectures listed in subject.
> I'm new to Xilinx FPGA's, and comparing them by myself is a little
> confusing to me.
>
>


Article: 38139
Subject: WARNING
From: llossak <maodahrng@sina.com.cn>
Date: Sun, 6 Jan 2002 18:54:02 -0800
Links: << >>  << T >>  << A >>
# WARNING: [TSCALE] - Module 'MEM_BLK' does not have a `timescale directive in effect, but previous modules do
#        Region: /testbench/d/NA_U4/Na_U1/inst/memblk
# Loading work.NA_Message_Generate
# Loading work.glbl

why?

Article: 38140
Subject: WARNING
From: cortyus <saority@hour.edu>
Date: Sun, 6 Jan 2002 18:57:13 -0800
Links: << >>  << T >>  << A >>
# WARNING: Simulation log file vsim.wlf is open by another ModelSim application or was not closed properly.
# WARNING: Could not open log file vsim.wlf, using C:\TEMP\vsimw4.wlf instead.

Article: 38141
Subject: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 07 Jan 2002 08:45:04 +0200
Links: << >>  << T >>  << A >>
Orlls wrote:
> 
> how and where do i change the vcom option?

If you are running "vcom" (Modelsim VHDL compiler) from
the command line, then it is easy. Just type "vcom" and
look at stdout report and try how you can use Mike's
solution. If you are using GUI of Modelsim, then you have
to look at the compiler options in the menus x/+ (and/or)
library settings. Try and see!

Utku

Article: 38142
Subject: Re: WARNING
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 07 Jan 2002 08:47:09 +0200
Links: << >>  << T >>  << A >>

> # WARNING: Simulation log file vsim.wlf is open by another
> # ModelSim application or was not closed properly.
> # WARNING: Could not open log file vsim.wlf, using C:\TEMP\vsimw4.wlf instead.

# WARNING: Don't call same HDL objects more than once on your PC,
# This might result simulation errors. Close one of your Modelsim
# Windows!

Article: 38143
Subject: Re: WARNING
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 07 Jan 2002 08:48:22 +0200
Links: << >>  << T >>  << A >>
llossak wrote:
> 
> # WARNING: [TSCALE] - Module 'MEM_BLK' does not have a `timescale directive in effect, but previous modules do
> #        Region: /testbench/d/NA_U4/Na_U1/inst/memblk
> # Loading work.NA_Message_Generate
> # Loading work.glbl
> 
> why?

# WARNING: Please use `timescale commands in all of your Verilog
# codes. This will drop out the message above coming from the
# Modelsim simulator kernel.

Article: 38144
Subject: Re: WARNING
From: shengyu_shen@hotmail.com (ssy)
Date: 6 Jan 2002 23:26:09 -0800
Links: << >>  << T >>  << A >>
nothing to worry about, I see about 100 such warning, but never happen anything

cortyus <saority@hour.edu> wrote in message news:<ee740d8.-1@WebX.sUN8CHnE>...
> # WARNING: Simulation log file vsim.wlf is open by another ModelSim application or was not closed properly.
> # WARNING: Could not open log file vsim.wlf, using C:\TEMP\vsimw4.wlf instead.

Article: 38145
Subject: Synplify and Xilinx clock discovery
From: dottavio@ised.it (Antonio)
Date: 7 Jan 2002 00:24:26 -0800
Links: << >>  << T >>  << A >>
In my project I've two clocks : 
1) clk 
2) clk_div_4 obtained from clk 

synplify tells me that it inferred clk_div_n clock so he discover it,
but when I send the mapped design to Xilinx 4.1 SP3 after P&R I've the
message that clk_div_n is a clock net that use not dedicated
resources, I'm implementing on Xilinx XCV1000BG560-4, how I can solve
the problem and assign to clk_div_n dedicated resources  ???

Article: 38146
Subject: Re: Suitability of Atmel for project?
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Mon, 7 Jan 2002 10:29:26 +0100
Links: << >>  << T >>  << A >>
I can see several different possibilities.
1) Use the FPSLIC (See Programmable SLI on Atmel's home page)
    This includes an AVR at 25 Mhz (soon faster) and FPGA for
    high speed serial interface.
    You need an Adapter to the 40 pin.
    FPSLIC is 3Volt only.
2) Put an ARM processor there.
    You can mount the AT91F40816 (BGA120) onto a 40 pin DIL adapter.
    This runs at 33-66 Mhz so speed is quite improved.
    There are 5 Volt tolerant ARMs.
3) Wait until the mega8515 which runs 2 x 8515 speed.
4) Use the mega8. This is available now in a 5 x 5 mm package and 32 pins
    and 2 x speed. Would perhaps allow a surface mounted PLD as well.
    The package is MLF (Multi Lead Frame).

It would be interesting to know WHICH serial interfaces you wanted to have.
--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

"Stout" <i_never_check_this@hotmail.com> skrev i meddelandet
news:9fc1b2f5.0201052219.645526c6@posting.google.com...
> My company has a large inventory of boards that have a 40 pin DIP
> socket that was originally meant for another chip.  My new need is to
> run an equivalent (opcode compatable) 8051 @ 5 Mhz plus some glue and
> a couple of other oddball things.  Ideally I would like to use a
> device that is also a 40 pin DIP so that I can use the boards.
>
> I am brand-new to the PLD/FPGA arena but have about 20 years of EE
> experience.
>
> After a quick search around the web I found the Atmel ATV2500, a 40
> pin DIP PLD (data sheet is at
> http://www.atmel.com/atmel/acrobat/doc0249.pdf).  Since I'm so new to
> this I have no idea of how to estimate if this thing is remotely
> capable of meeting my logic requirements.  Any input, URLs, etc. is
> appreciated.  TIA.
>
> - Stout







Article: 38147
Subject: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
From: Przemyslaw Wegrzyn <czajnik@czajsoft.pl>
Date: Mon, 07 Jan 2002 12:07:01 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Sorry for the confusion, it's really our fault;
> 
[cut]
>
> Hope this helps.

Yes, thank you very much. But you must agree - naming scheme is a little 
confusing.

> Greetings to Poland. I once spent a week in Krakow...

Why not to come again ? ;)

Greetings
P.Wegrzyn



Article: 38148
Subject: Re: PCI Solution: LogiCore?
From: johnjakson@earthlink.net (John Jakson)
Date: 7 Jan 2002 04:36:53 -0800
Links: << >>  << T >>  << A >>
"Austin Franklin" <austin@da87rkroom.com> wrote in message news:<u3beltcjrck6b8@corp.supernews.com>...
> > We want to stick to the 32 bit, 33 Mhz bus. Our data is not sustained
> > but consist of bursts that can vary between 16 Kbyte and 64 KByte. We
> > consider using extern memory to avoid time critical situations. Any
> > suggestions regarding this matter?
> 
> Is your data rate really 100M bytes/sec...  If so, I do not believe you will
> be able to sustain this rate.  As you suggest, putting buffer memory on the
> board, so you reduce your PCI bus requirement, may be your only solution if
> you want to be on a 32/33 PCI bus.
> 
> Are you transfering to system memory?  Are you the only activity that will
> be going on?  Is this a dedicated system, or a standard Windows based PC?


So what is your data source?, if it is A/D D/A you could consider
compression, with a simple lossless codec you may easily achieve a 2
fold bandwidth reduction. In extreme cases with wavelet (lossy) type
codecs reduction can get much much higher. Such a small reduction as
even 1.5 or 2 could easily make the difference between a 32/33 cheap
sytem & a 64 or 66MHz expensive system. More compression equals more
codec logic, the other side of the codec though can probably be done
in native asm, both being designed together.

John Jakson

Article: 38149
Subject: Regarding frequency achieving in fpga design
From: satya@iwavesystems.net (satya)
Date: 7 Jan 2002 04:46:02 -0800
Links: << >>  << T >>  << A >>
Hi All,
I have a design that is to be implemented on XILINX Virtex2 FPGA.I
have a design that should work at 155Mhz internally.By using ISE4.1i I
am able to get around 100Mhz without applying timing constraints.My
doubt is that how much change in frequency(approximately) we can
achieve by applying timing constraints?.I am using Synopsis FPGA
Express for synthesis.which synthesis tool will provide better
frequency results in 4.1i?
One more doubt is that,is constraint based implementation is a best
method of core implementation??
Please clear my doubts.Also please point me to some good 4.1itutorials
for various options.
I will be waiting for reply.

Thanks and Regards
- satya



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