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Messages from 38350

Article: 38350
Subject: Re: speech recognition - active noise cancellation
From: Ray Andraka <ray@andraka.com>
Date: Sat, 12 Jan 2002 05:06:05 GMT
Links: << >>  << T >>  << A >>
How about a noise cancelling microphone? They use a differential setup on
the element to cancel noise that is not made by the speaker.

chris wrote:

> i am trying to do a speech recognition application and i need a clean
> input voice signal to a microphone. my problem is that i need to get
> rid of ambient noise in a room without affecting the voice signal at
> all. i have thought about doing an adaptive filter like application,
> but i cannot think of a way to isolate just the ambient noise without
> touching the voice. my main goal would be to come up with some kind of
> active noise control setup that would be able to phase-cancel the
> ambient noise while keeping the voice signal clean. does anyone know
> how this can be done? i have seen something similar from andreas
> electronics, but their product doesn't exactly fit my requirement. any
> help would be appreciated. thanks.
> chris wang

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38351
Subject: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
From: shengyu_shen@hotmail.com (ssy)
Date: 11 Jan 2002 21:10:30 -0800
Links: << >>  << T >>  << A >>
Hi Ray

you idea is excellent

I do as you say, and the shifter actually fit in a Megalab, and the
speed of my design increase to 33.5Mhz easily

thank you very much and Best Regard

Ray Andraka <ray@andraka.com> wrote in message news:<3C3F3F7A.B8B0C67A@andraka.com>...
> Your shifter is apparently not being constructed as a merged tree.  If it were a merged
> tree, a 32 bit shift would be 5 layers, each layer being a 32 bit 2:1 mux.  The first
> layer shifts by either 0 or 16 bits, the next by 0 or 8 bits, the next by 0 or 4 and so
> on.  With this construction you get a composite shift of 0 to 31 bits.  Each layer
> consists of 32 2:1 muxes, each of which occupies an LE.  5 Layers is 160 LEs.  I suspect
> the shifter you are dealing with is instead a set of 32 32:1 muxes.  Each of those is a
> tree containing the logic equivalent of 31 2:1 muxes, or about 6 times the logic.  I
> further suspect that the logic has been reduced using the cascade chains to make 4:1 muxes
> from pairs of LE's, resulting in approximately 3 times the LE's of the merged tree.
> 
> Routing usually is not part of the macro, however if it is a placed macro, then the
> routing can be more or less forced onto certain paths.  You have to know what the
> connection matrix is, however if you are going to congest the routing.  In that respect,
> the xilinx devices are easier to tweak for performance because you have access to the
> routing matrix when doing the floorplanning, and routes are generally more local so there
> is less chance of having other stuff upset the routing in your floorplanned logic.
> 

> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 38352
Subject: Re: Picking an FPGA
From: Ray Andraka <ray@andraka.com>
Date: Sat, 12 Jan 2002 05:25:24 GMT
Links: << >>  << T >>  << A >>
Yeah, only touched the tip of the iceberg there.  If you need a clock enable, that
steals one of those two inputs, leaving you with a one input arithmetic
function....not all that useful.  Also there is the issue of the I/Os having only
one register, which means for high speed bidirectional IO to memroy for example,
you need to use two pads per bit to get the best speed, otherwise, one of the
flip-flops is inside the array instead at the IOB.  You not only incur a speed
penalty for that, but you also get external timing that is dependent on the place
and route solution.  There are other things too, but the arithmetic and lack of
distributed memory are the big ones for DSP.

To be fair, Altera does very well with state machines and the traditional random
logic collection, and usually with less effort to get timing closure than with an
equivalent Xilinx part.  It just isn't a great architecture for data path design.

For a one size fits all, make sure your power supply is beefy enough to handle a
high performance design.  It is pretty easy to get these puppies to disspate
several watts.  I've run into a couple of boards now who's power regulators don't
quite cut it.  One in particular that I am working with right now has a linear
regulator on it that regulates the 1.8v for a pair of virtex 2000E from a 5 v
supply using a TO220 package on a pretty small heatsink (note that that means the
regulator disippates twice the combined power of the FPGAs).  The regulator is
rated for 7A, but with that set up the regulator goes into thermal shutdown with
the design drawing about 2A.  That happens with one Virtex loaded with a moderate
design and the other one empty.

rickman wrote:

> Thanks for the advice Ray. I finally figured out a way to do most of
> what I want. My real problem is that I am trying to design a board that
> can be everything to everyone depending on the chips you add. This means
> low power if that is what you need or high performance if that is what
> you need. And of course, it always has to be low cost.
>
> So I keep running into walls with this approach. The one that I really
> hate is the problems that the Virtex/SpartanII startup current causes.
> But if I only use one chip per voltage, I can get around that. So for
> now I am looking at using a CoolRunner as the PC/104 interface. This is
> not too expensive and it keeps that part of the power down. Then
> everything else will go into an XC2S150E. This has a little room for
> growth if there is future need for a bigger part. Too bad they didn't
> keep the pinout compatible with the Virtex E parts, d..m! The other
> problem this causes me is the lack of reconfiguration for different
> combinations of IO. There is just not room on the board (or power
> supply) to give each IO module its own FPGA like the current board has.
> The new board has 4 IO sites rather than just 2. So I will be looking
> hard at Jbits and various methods of modularizing bitstreams in the
> future.
>
> For now this will get us off the ground and allow us to design a
> workable board. Maybe when the Spartan version of the XC2V parts is
> available I will work with that if I am still working then :)
>
> BTW, I am aware of the limitations of the Altera architecture for doing
> math. The 10K/1K family has other limitations as well since not all of
> the inputs to the LUT can be used when you are using all the inputs to
> the FFs. But the real kicker is the MAX+PLUS II tool. We found that in a
> dense design it will just plain lie about timing. The analyzer says you
> have a good design that meets timing and because of the complex routing
> that can be required, it miscalculates and the chip will fail at
> temperature. At least they have moved most of the 10K/1K family to
> Quartus in the paid versions. The free versions still only support them
> under MAX+PLUS II.
>
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38353
Subject: Re: Picking an FPGA
From: Ray Andraka <ray@andraka.com>
Date: Sat, 12 Jan 2002 05:37:58 GMT
Links: << >>  << T >>  << A >>
The newer Altera families have made improvements for DSP, but IMHO have not caught up to
Xilinx.  The 20 K adds flip-flops in the IO to handle fast bidirectional traffic, adds
direct connect to adjacent LABs, which is critical for data path, and adds a layer of
hierarchy in the row routing which helps in terms of route congestion.  They also separated
the clock enable and clears so that their use doesn't block a LUT pin inthe LE.  The LUT
still gets decomposed into a pair of 3 LUTs for arithmetic, so you still have the problem
for arithmetic with more than 2 inputs (multipliers, adder/subtractors),  At least with the
dedicated CE, and clears you can manage an accumulator with a clear in one level of logic
now.

I have not looked closely at the Mercury yet, so I am not sure what architectural
improvements have been made there.  One thing I can say good for Altera, is that they have
their act together as far as marketing the DSP and they look like they are very serious
about having a good suite of cores available to back up the marketing.



guy wrote:

> Hey Rick,
> I see you are in MD.
> Strong suggestion here - call your local Altera office 410-203-1245
> and ask for Jeff Wills.  He can meet with you and tell you all about
> Altera's DSP capabilities architectually, tools, and IP.  Much more
> significant than 10k.  Do yourself a favor and get this in person or
> on phone.
>
> Guy
> Altera Corp.
>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38354
Subject: Re: multiply (*) 11000000000
From: Ray Andraka <ray@andraka.com>
Date: Sat, 12 Jan 2002 05:41:50 GMT
Links: << >>  << T >>  << A >>
Ken,  last time I looked at what came out with a constant multiply done with the
signal*constant construct, I think it produced a LUT based partial product constant
multiply (see my website's multiplier page for an explanation).  It would have been the
first release with the multiplier inference.  I haven't looked since.

Ken McElvain wrote:

> In Synplify, we have a special multiply by constant
> mode that does some recoding of the constant to
> reduce the number of adders.  I think you will get
> a good result just doing the multiply.  For more
> complex constants we will probably get fewer adders
> than you would expect.  Try multiplying by 7 and see
> what happens.
>
> Ken McElvain
> CTO, Synplicity
>
> Ray Andraka wrote:
>
> > Because the synthesizer may not recognize that it can be done with an adder.
> > Often a template is used which in turn instantiates the vendor core for the
> > multiplier.  I believe if you do this in synplicity, you'll get a LUT based sum
> > of partial products construction based on the Xilinx coregen constant coefficient
> > multiplier.  The synthesis is not smart enough to distill that down to an adder
> > (it would if the multiplier template produced a full array multiplier, but that
> > is usually a very inefficient construct in an FPGA).
> >
> > Jay wrote:
> >
> >
> >>What about just typing a "*" and let your synthesizer turn it into 2
> >>adders?  This way nobody has to try to figure out why you're adding 2
> >>shifted numbers when they're reading the code.
> >>
> >>Kenily <aiurh@iuehr.erug> wrote in message news:<ee74130.-1@WebX.sUN8CHnE>...
> >>
> >>>i want to implement a multiplier.one
> >>>multiply 0x600(Hex).how do i implement?
> >>>
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38355
Subject: Re: Q:Hand placed fast 32 bit barrel shifter for APEX?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 12 Jan 2002 05:51:02 GMT
Links: << >>  << T >>  << A >>
See, and who says those core libraries are the be all and end all.  Frankly, I'm mildly
surprised and amused that the Altera LPM didn't use a merged tree.  I thought their core group
was a little more on top of it than that.  I am assuming you used a barrel shift LPM, not a
bunch of MUX32 LPMs.

ssy wrote:

> Hi Ray
>
> you idea is excellent
>
> I do as you say, and the shifter actually fit in a Megalab, and the
> speed of my design increase to 33.5Mhz easily
>
> thank you very much and Best Regard
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3C3F3F7A.B8B0C67A@andraka.com>...
> > Your shifter is apparently not being constructed as a merged tree.  If it were a merged
> > tree, a 32 bit shift would be 5 layers, each layer being a 32 bit 2:1 mux.  The first
> > layer shifts by either 0 or 16 bits, the next by 0 or 8 bits, the next by 0 or 4 and so
> > on.  With this construction you get a composite shift of 0 to 31 bits.  Each layer
> > consists of 32 2:1 muxes, each of which occupies an LE.  5 Layers is 160 LEs.  I suspect
> > the shifter you are dealing with is instead a set of 32 32:1 muxes.  Each of those is a
> > tree containing the logic equivalent of 31 2:1 muxes, or about 6 times the logic.  I
> > further suspect that the logic has been reduced using the cascade chains to make 4:1 muxes
> > from pairs of LE's, resulting in approximately 3 times the LE's of the merged tree.
> >
> > Routing usually is not part of the macro, however if it is a placed macro, then the
> > routing can be more or less forced onto certain paths.  You have to know what the
> > connection matrix is, however if you are going to congest the routing.  In that respect,
> > the xilinx devices are easier to tweak for performance because you have access to the
> > routing matrix when doing the floorplanning, and routes are generally more local so there
> > is less chance of having other stuff upset the routing in your floorplanned logic.
> >
>
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38356
Subject: FPGA : Configurtion
From: Balakrishnan <kbkrishnan@tataelxsi.co.in>
Date: Fri, 11 Jan 2002 23:15:08 -0800
Links: << >>  << T >>  << A >>
In my design i'm using SPARTAN-II and SPARTAN-XL devices ,For configurtaion i like to use boundary scan(only during Board testing phase ) and slave serial mode.My doubt is only for boundary scan mode,it is possible to do daisy chain  sort of thing (connecting TDO of SPARTAN-II to TDI of SPARTAN-XL device)

Article: 38357
Subject: Re: speech recognition - active noise cancellation
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Sat, 12 Jan 2002 07:24:32 +0000 (UTC)
Links: << >>  << T >>  << A >>

"Jerry Avins" <jya@ieee.org> wrote in message
news:3C3FA303.1B3A019E@ieee.org...
>
> Contact throat microphones were used in fighter planes 50 years ago.
> They discriminate against ambient noise very nicely indeed. 50 dB SNR
> improvements were cited, but I didn't make measurements myself.

I looked into throat microphones when I worked on military radio human
factors.

They deal with ambient noise OK, but the speech quality  is generally very
poor. They are also uncomfortable to wear (especially when they get wet, as
often happens with special services personnel), and generally need to be
pressed against the larynx with a finger to work properly. Users hate them!

Leon
--
Leon Heller, G1HSM leon_heller@hotmail.con
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com





Article: 38358
Subject: Re: [WebPACK or ISE] Mixing Verilog and EDIF?
From: hamish@cloud.net.au
Date: 12 Jan 2002 07:34:35 GMT
Links: << >>  << T >>  << A >>
Santiago de Pablo <sanpab@eis.uva.es> wrote:
>  The WebPACK produces EDIF files (*.edn) properly, and the ISE 4.1 can
> implement them if all the design is in EDIF format. But I want to create
> in verilog a high level design and include those modules in EDIF format
> (I don't want to give to the final users the original source code ;-/).
> All I get is that ISE 4.1 (or my installation of it) cannot do such
> thing.

ISE can do this. When NGDBUILD runs, if it encounters any block boxes
in your top level EDIF (excluding Xilinx primitives), it will look
for a .EDF with the same name as the missing module.

Thus in your top level Verilog design, instantiate the module but
make it a black box for synthesis.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38359
Subject: Re: Avoid routing through a certain area (Xilinx)
From: hamish@cloud.net.au
Date: 12 Jan 2002 07:40:42 GMT
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote:
> logic that do not overlap except at the edges. Oh, yes, I forgot that
> this is another required function that is not currently available in the
> P&R tools, partial routes to defined endpoints. 

I think you can achieve this with the modular flow, to some extent.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38360
Subject: FPGA configuration
From: kbkrishnan@tataelxsi.co.in (balakrishnan)
Date: 11 Jan 2002 23:41:38 -0800
Links: << >>  << T >>  << A >>
Hi,
In my design i'm using SPARTAN-II and SPARTAN-XL devices ,For
configurtaion i like to use boundary scan(only during Board testing
phase ) and slave serial mode.My doubt is only for boundary scan
mode,it is possible to do daisy chain  sort of thing (connecting TDO
of SPARTAN-II to TDI of SPARTAN-XL device)

Regards,
Bala

Article: 38361
Subject: Re: bufg instantiation in ISE 4.1
From: hamish@cloud.net.au
Date: 12 Jan 2002 07:43:02 GMT
Links: << >>  << T >>  << A >>
Andy Peters <andy@exponentmedia.nospam.com> wrote:
> Why are you instantiating these components?  The tool will infer them 
> for you.

Not if you need a DCM/DLL.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38362
Subject: Re: asic vs. fpga
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: Sat, 12 Jan 2002 09:03:04 GMT
Links: << >>  << T >>  << A >>
Matthias Weber <msweber@onlinehome.de> writes:

> i am searching for a link, book, university lessons explaining the
> architecture of asic and fpga and their differences.

One more little thing which I don't think have been mentioned...

Most ASIC vendors require you to supply production test patterns for
your ASIC. To do this you normally use some (expensive) software ATPG
(automatic Test Pattern Generation) and/or provide additional
patterns. In addition you need patterns to test your tristate drivers
etc. Finally you make a pattern file for your vendors tester. This
task can sometimes be a little tedious.

The FPGA vendors have already done this for their devices so there is
no need to make production test patterns for a FPGA.

Petter
-- 
________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.com

Article: 38363
Subject: Re: Xilinx PAR and Editor speed up
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: Sat, 12 Jan 2002 09:03:04 GMT
Links: << >>  << T >>  << A >>
"Bryan" <bryan@srccomp.com> writes:

> Because of a separate project I am doing, I had a Linux box set up to
[snip]

Could you imagine a native Linux version - which includes the
distributed (multinode) PAR option available under Solaris (dream)...

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 38364
Subject: Re: Picking an FPGA
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 12 Jan 2002 04:13:48 -0500
Links: << >>  << T >>  << A >>
Guy,

Thanks for the suggestion, but I spent a year working with Altera parts
in a very intense FPGA group in telecom. The problem I have is not that
the parts are not capable, but rather that Altera only has one low cost
family, ACEX 1K, and that is not very capable. The 20K and other
families are much better than the 10K/1K parts, but they cost much more
than my project can afford. 


guy wrote:
> 
> Hey Rick,
> I see you are in MD.
> Strong suggestion here - call your local Altera office 410-203-1245
> and ask for Jeff Wills.  He can meet with you and tell you all about
> Altera's DSP capabilities architectually, tools, and IP.  Much more
> significant than 10k.  Do yourself a favor and get this in person or
> on phone.
> 
> Guy
> Altera Corp.
> 
> rickman <spamgoeshere4@yahoo.com> wrote in message news:<3C3F3029.5E555144@yahoo.com>...
> > I am finalizing my FPGA selection for a line of DSP boards that we will
> > be making for a number of years. I have always been more familiar with
> > Xilinx but had a chance to work with the Altera 10K parts this past
> > year. They seem ok, but the nearly identical ACEX 1K family is better in
> > most regards. But the gate size is limited if we are looking at having
> > future growth and I am not finding as good a price as with the Xilinx
> > SpartanII parts. The only vendors I can find are Arrow and Newark, and
> > Newark does not show much on their web site. Anyone know how to get good
> > price numbers on the Altera parts without having a handfull of specific
> > parts? If I call the vendors, they always want me to give the a few part
> > numbers and I am window shopping and need pricing on all the parts so I
> > can make my choices.
> >
> > The other problem I have with the Altera FPGAs is the lack of LUT RAM.
> > There are only a small number of RAM (EAB/ESB) in these parts and I need
> > a lot more blocks of it than are available. They don't have to be big,
> > the 16 words available in a bank of Xilinx LUTs is perfect. For example,
> > I will need 64 blocks of RAM if four modules of the 8 channel ADC/DAC
> > are on board. This is not hard using the Xilinx LUTs. Anyone know of a
> > way to do something similar in an Altera FPGA?
> >
> > BTW, just to mention why I like the Altera parts... THEY DON'T HAVE A
> > STARTUP CURRENT SURGE!!! Was I at all unclear about that?  :)

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 38365
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: hamish@cloud.net.au
Date: 12 Jan 2002 13:49:02 GMT
Links: << >>  << T >>  << A >>
Kevin Brace <nospamtomekevinbraceusenet@nospamtomehotmail.com> wrote:
> Hi, I will like to know how the readers of this newsgroup think of
> including clock skew for setup time analysis?

Here's a related problem I'm experiencing a lot at the moment
while working on a Virtex-II design with 4.1i.

I have several different clock domains, and I use FROM:TO
constraints to cover the paths that cross clock domains.
This generally works well but in many cases, PAR and TRCE
include a large amount of "negative clock skew" in the
calculation. Typically the negative clock skew is equal
to the delay through the BUFG for the destination flip-flop's
clock net; it's over 2ns (ie negative clock skew of < -2ns).

Perhaps some readers will disagree, but to me, clock skew has no 
meaning in analysis of cross-clock-domain paths. I'm only
interested in data path delay. If any clock skew is included,
it should only be the real skew on the two clock nets, not
the entire BUFG delay on the destination clock net.

Our local Xilinx rep looked into this for me and told me that
FROM:TO is only intended for use with related clocks, not
unrelated clocks like mine. That's OK, but what should I do
for unrelated clocks? Obviously these paths still need
constraints.

My workaround has been to increase the allowed delay in
the constraints by an amount smaller than the clock skew
numbers I've seen. The skew numbers seem to be systematic,
so this seem to work OK as long as the skew figures don't
change. Looks like they have a little between speed file
versions.

I've got another weird timing analysis bug (with offset out
constraints and DDR) but I'll save it for another time.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38366
Subject: Re: FPGA : Configurtion
From: "C.Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Sat, 12 Jan 2002 16:47:59 +0100
Links: << >>  << T >>  << A >>
Hi,
as Boundary Scan Interface is a serialized structure (TDO -> TDI), that's
the only
way to connect the devices. As I do not work with XILINX devices I can just
rely on
ALTERA experience. In their programmer, You cofigure the tool to match the
external
daisy chain of devices and assign the programming files to the devices.
I think the XILINX tools will work in a similar way.

CU, CS

"Balakrishnan" <kbkrishnan@tataelxsi.co.in> schrieb im Newsbeitrag
news:ee742cc.-1@WebX.sUN8CHnE...
> In my design i'm using SPARTAN-II and SPARTAN-XL devices ,For
configurtaion i like to use boundary scan(only during Board testing phase )
and slave serial mode.My doubt is only for boundary scan mode,it is possible
to do daisy chain  sort of thing (connecting TDO of SPARTAN-II to TDI of
SPARTAN-XL device)



Article: 38367
Subject: Re: speech recognition - active noise cancellation
From: Jerry Avins <jya@ieee.org>
Date: Sat, 12 Jan 2002 12:38:39 -0500
Links: << >>  << T >>  << A >>
Leon Heller wrote:
> 
> "Jerry Avins" <jya@ieee.org> wrote in message
> news:3C3FA303.1B3A019E@ieee.org...
> >
> > Contact throat microphones were used in fighter planes 50 years ago.
> > They discriminate against ambient noise very nicely indeed. 50 dB SNR
> > improvements were cited, but I didn't make measurements myself.
> 
> I looked into throat microphones when I worked on military radio human
> factors.
> 
> They deal with ambient noise OK, but the speech quality  is generally very
> poor. They are also uncomfortable to wear (especially when they get wet, as
> often happens with special services personnel), and generally need to be
> pressed against the larynx with a finger to work properly. Users hate them!
> 
> Leon
> --
> Leon Heller, G1HSM leon_heller@hotmail.con
> http://www.geocities.com/leon_heller
> Low-cost Altera Flex design kit: http://www.leonheller.com

The ones used with the AIC-10 consisted of a pair built into the flight
helmet, along with the ear phones. They were carbon mikes, and the poor
response was due in part to muffling of the sound by the throat tissues.
I designed a compensator filter for a next-generation AIC that sounded
pretty good, but I don't know if it ever got used. The project was put
aside while we built the Mercury capsule audio box, then I left the
company. I didn't need a free hand to talk, nor did I find it
particularly uncomfortable. Maybe the fly boys had better equipment.

What is used on motorcycles nowadays? Rick? Anyone?

Jerry
-- 
Engineering is the art of making what you want from things you can get.
-----------------------------------------------------------------------

Article: 38368
Subject: Re: speech recognition - active noise cancellation
From: "david garnett" <dave.garnett@metapurple.co.uk>
Date: Sat, 12 Jan 2002 18:19:33 -0000
Links: << >>  << T >>  << A >>
Look at www.cortologic.com for noise/echo suppression chips. usual
disclaimer here <>

Dave

"chris" <cjwang_1225@hotmail.com> wrote in message
news:24a13eb0.0201111713.7f9af7b5@posting.google.com...
> i am trying to do a speech recognition application and i need a clean
> input voice signal to a microphone. my problem is that i need to get
> rid of ambient noise in a room without affecting the voice signal at
> all. i have thought about doing an adaptive filter like application,
> but i cannot think of a way to isolate just the ambient noise without
> touching the voice. my main goal would be to come up with some kind of
> active noise control setup that would be able to phase-cancel the
> ambient noise while keeping the voice signal clean. does anyone know
> how this can be done? i have seen something similar from andreas
> electronics, but their product doesn't exactly fit my requirement. any
> help would be appreciated. thanks.
> chris wang



Article: 38369
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 12 Jan 2002 20:19:41 +0100
Links: << >>  << T >>  << A >>
hamish@cloud.net.au writes:

> Our local Xilinx rep looked into this for me and told me that
> FROM:TO is only intended for use with related clocks, not
> unrelated clocks like mine. That's OK, but what should I do
> for unrelated clocks? Obviously these paths still need
> constraints.

Are you sure? Whar kind of signal is it?

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 38370
Subject: Quick question regarding IEEE-TVLSI and IEEE-Computer
From: Adam Elbirt <aelbirt@nac.net>
Date: Sat, 12 Jan 2002 15:12:48 -0500
Links: << >>  << T >>  << A >>
Does anyone know off-hand which issues of TVLSI and Computer were the 
ones that were the special issues on reconfigurable hardware/logic?

Adam


Article: 38371
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sat, 12 Jan 2002 20:26:14 -0000
Links: << >>  << T >>  << A >>

>Perhaps some readers will disagree, but to me, clock skew has no 
>meaning in analysis of cross-clock-domain paths. I'm only
>interested in data path delay. If any clock skew is included,
>it should only be the real skew on the two clock nets, not
>the entire BUFG delay on the destination clock net.

I can't figure out your setup.

Are your clocks derived from the same source, say one running
at X MHz and other running at X/2 MHz?  Then you and/or the tools
need to account for the difference is prop times on the two
different clock paths.  (Note that you have to think about hold
times as well as setup times.)

Are the clocks from two separate sources?  If so, then you need to
be thinking about metastability, not clock skew.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 38372
Subject: Re: speech recognition - active noise cancellation
From: Ray Andraka <ray@andraka.com>
Date: Sat, 12 Jan 2002 21:28:06 GMT
Links: << >>  << T >>  << A >>
Jerry,

I don't know about motorcycles, but aviation headsets for piston powered light
aircraft (which are pretty noisy inside) use a noise cancelling microphone which
does a pretty decent job.  (you can see how bad it gets by covering the backside
ports in the microphone when you talk).  The noise cancelling mike has ports
facing the speaker's mouth and ports on the backside facing away from your
mouth.  The difference in the sound from the two ports is what is amplified.
These are not throat mikes, rather they are on a boom that you position
immediately in front of your lips.  If you can't kiss it, it is too far away.

Jerry Avins wrote:

> Leon Heller wrote:
> >
> > "Jerry Avins" <jya@ieee.org> wrote in message
> > news:3C3FA303.1B3A019E@ieee.org...
> > >
> > > Contact throat microphones were used in fighter planes 50 years ago.
> > > They discriminate against ambient noise very nicely indeed. 50 dB SNR
> > > improvements were cited, but I didn't make measurements myself.
> >
> > I looked into throat microphones when I worked on military radio human
> > factors.
> >
> > They deal with ambient noise OK, but the speech quality  is generally very
> > poor. They are also uncomfortable to wear (especially when they get wet, as
> > often happens with special services personnel), and generally need to be
> > pressed against the larynx with a finger to work properly. Users hate them!
> >
> > Leon
> > --
> > Leon Heller, G1HSM leon_heller@hotmail.con
> > http://www.geocities.com/leon_heller
> > Low-cost Altera Flex design kit: http://www.leonheller.com
>
> The ones used with the AIC-10 consisted of a pair built into the flight
> helmet, along with the ear phones. They were carbon mikes, and the poor
> response was due in part to muffling of the sound by the throat tissues.
> I designed a compensator filter for a next-generation AIC that sounded
> pretty good, but I don't know if it ever got used. The project was put
> aside while we built the Mercury capsule audio box, then I left the
> company. I didn't need a free hand to talk, nor did I find it
> particularly uncomfortable. Maybe the fly boys had better equipment.
>
> What is used on motorcycles nowadays? Rick? Anyone?
>
> Jerry
> --
> Engineering is the art of making what you want from things you can get.
> -----------------------------------------------------------------------

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38373
Subject: Re: speech recognition - active noise cancellation
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Sun, 13 Jan 2002 00:30:45 +0000 (UTC)
Links: << >>  << T >>  << A >>


"Ray Andraka" <ray@andraka.com> wrote in message
news:3C40AAF1.84FC623@andraka.com...
> Jerry,
>
> I don't know about motorcycles, but aviation headsets for piston powered
light
> aircraft (which are pretty noisy inside) use a noise cancelling microphone
which
> does a pretty decent job.  (you can see how bad it gets by covering the
backside
> ports in the microphone when you talk).  The noise cancelling mike has
ports
> facing the speaker's mouth and ports on the backside facing away from your
> mouth.  The difference in the sound from the two ports is what is
amplified.
> These are not throat mikes, rather they are on a boom that you position
> immediately in front of your lips.  If you can't kiss it, it is too far
away.
>

I used to work with Royal Marines, amongst other regiments,  on our radio
system, and was told that some of them chewed their microphones when they
were under a lot of stress. Reverting to infantile behaviour, I suppose. 8-)

Leon
--
Leon Heller, G1HSM leon_heller@hotmail.con
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com




Article: 38374
Subject: modelsim
From: llossak <maodahrng@sina.com>
Date: Sat, 12 Jan 2002 19:03:50 -0800
Links: << >>  << T >>  << A >>
i work use ise4.1 and modelsim,when i replace the old version modelsim.In ise4.1,when i simulate,it says:
# WARNING: Could not open f:\eda_tools\Modeltech_5.5e\modelsim.ini from MODELSIM environment variable setting, using modelsim.ini instead

how do i change?



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