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Messages from 38375

Article: 38375
Subject: the timng of the lpm_fifo
From: shengyu_shen@hotmail.com (ssy)
Date: 12 Jan 2002 19:05:07 -0800
Links: << >>  << T >>  << A >>
Hi everyone

if any one know the timing of lpm_fifo with signal clock

if it is asyn read and syn write?

Article: 38376
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: hamish@cloud.net.au
Date: 13 Jan 2002 04:48:34 GMT
Links: << >>  << T >>  << A >>
Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote:
> hamish@cloud.net.au writes:
>> Our local Xilinx rep looked into this for me and told me that
>> FROM:TO is only intended for use with related clocks, not
>> unrelated clocks like mine. That's OK, but what should I do
>> for unrelated clocks? Obviously these paths still need
>> constraints.

> Are you sure? Whar kind of signal is it?

Am I sure that I need constraints? Most definitely.

Typical example case: I have a high speed clock and a low speed
clock (ratio about 5:1). Let's say the low speed clock is for
CPU access. I need to occasionally get a value from the high
speed clock domain to the low speed clock domain. The value
is changing every clock in the high speed domain, and I need
to get a coherent value into the low speed domain.

So, I generate a pulse in the low speed clock domain. In the
high speed domain, I sample the signal and edge detect it,
and when I see a rising edge, I enable a register which will
hold the value (sample and hold approach). Then a couple
of low speed clock cycles later, I use the held value by
clocking it into flip-flops in the low speed domain.

I need to be able to guarantee that the held value (in the
high speed domain) gets to the low speed flip-flops within
a certain period ie I need a timing constraint for this
path.

Here's a diagram (use a monospaced font to view):

                          FROM:TO needed here
                              <--------->

Changing  HS Signal     HS Sample      LS Sample
every     +-------+     +-------+      +-------+
cycle ----|D     Q|-----|D     Q|------|D     Q|
          |       | +---|CE     | +----|CE     |
       +-->CK     | | +->CK     | | +-->CK     |
       |  +-------+ | | +-------+ | |  +-------+
       |            | |           | |
HSCLK -+--------------+           | |
                    |             | |
LSCLK ------------------------------+
                    |             |
Pulse edge detect --+             |
                                  |
Delayed pulse --------------------+


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38377
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: hamish@cloud.net.au
Date: 13 Jan 2002 04:50:04 GMT
Links: << >>  << T >>  << A >>
Hal Murray <hmurray-nospam@megapathdsl.net> wrote:
> Are your clocks derived from the same source, say one running
> at X MHz and other running at X/2 MHz?  Then you and/or the tools
> need to account for the difference is prop times on the two
> different clock paths.  (Note that you have to think about hold
> times as well as setup times.)

> Are the clocks from two separate sources?  If so, then you need to
> be thinking about metastability, not clock skew.

They're completely unrelated clocks, all sourced off-chip. I
know how to cope with metastability -- but the tools are including
some (AFAICT irrelevant) clock skew in the calculations.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38378
Subject: Re: speech recognition - active noise cancellation
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Sun, 13 Jan 2002 07:08:45 GMT
Links: << >>  << T >>  << A >>
My brother claims that on a recent flight in the first-class section (I have
to take his word for it; it's been a while since I've been in that part of
the plane) he had nice earphones and a channel on the in-flight audio system
called "silent", which, when listened to, silenced the engine noise.  This
sounds like active noise reduction, but I thought ANR required the
noise-sensing mic to be close to the user's ear so the exact phase of the
noise could be detected for cancellation.  It doesn't seem likely that a
single anti-noise channel would work for all listeners in the plane.

I think ANR for helicopter noise works much better than for white noise
sources because helicopter noise is periodic over a decent interval of time
so a predictive filter can predict the noise ahead of time and get the
cancellation signal just right.  I know ANR is much less commonly used in
planes vs. helicopters, but I'm not sure if that's because it's less
effective or less necessary since planes are a little quieter and the ANR
headsets are terribly expensive.

"Ray Andraka" <ray@andraka.com> wrote in message
news:3C40AAF1.84FC623@andraka.com...
> Jerry,
>
> I don't know about motorcycles, but aviation headsets for piston powered
light
> aircraft (which are pretty noisy inside) use a noise cancelling microphone
which
> does a pretty decent job.  (you can see how bad it gets by covering the
backside
> ports in the microphone when you talk).  The noise cancelling mike has
ports
> facing the speaker's mouth and ports on the backside facing away from your
> mouth.  The difference in the sound from the two ports is what is
amplified.
> These are not throat mikes, rather they are on a boom that you position
> immediately in front of your lips.  If you can't kiss it, it is too far
away.
>
> Jerry Avins wrote:
>
> > Leon Heller wrote:
> > >
> > > "Jerry Avins" <jya@ieee.org> wrote in message
> > > news:3C3FA303.1B3A019E@ieee.org...
> > > >
> > > > Contact throat microphones were used in fighter planes 50 years ago.
> > > > They discriminate against ambient noise very nicely indeed. 50 dB
SNR
> > > > improvements were cited, but I didn't make measurements myself.
> > >
> > > I looked into throat microphones when I worked on military radio human
> > > factors.
> > >
> > > They deal with ambient noise OK, but the speech quality  is generally
very
> > > poor. They are also uncomfortable to wear (especially when they get
wet, as
> > > often happens with special services personnel), and generally need to
be
> > > pressed against the larynx with a finger to work properly. Users hate
them!
> > >
> > > Leon
> > > --
> > > Leon Heller, G1HSM leon_heller@hotmail.con
> > > http://www.geocities.com/leon_heller
> > > Low-cost Altera Flex design kit: http://www.leonheller.com
> >
> > The ones used with the AIC-10 consisted of a pair built into the flight
> > helmet, along with the ear phones. They were carbon mikes, and the poor
> > response was due in part to muffling of the sound by the throat tissues.
> > I designed a compensator filter for a next-generation AIC that sounded
> > pretty good, but I don't know if it ever got used. The project was put
> > aside while we built the Mercury capsule audio box, then I left the
> > company. I didn't need a free hand to talk, nor did I find it
> > particularly uncomfortable. Maybe the fly boys had better equipment.
> >
> > What is used on motorcycles nowadays? Rick? Anyone?
> >
> > Jerry
> > --
> > Engineering is the art of making what you want from things you can get.
> > -----------------------------------------------------------------------
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 38379
Subject: Re: How can I relate Virtex2 pin names and Slice XY loc?
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Sun, 13 Jan 2002 07:13:20 GMT
Links: << >>  << T >>  << A >>
Hmmm, this sounds really promising.  I might have to wait for the
documentation though.  So I can use this alternative grid system for
location constraints in the UCF?

-Kevin

"Bret Wade" <bret.wade@xilinx.com> wrote in message
news:3C3CEAB2.50CF73DF@xilinx.com...
> Hi Kevin,
>
> The 4.1i release (SP2 needed) contains a new feature that you may find
useful.
> It supports a new grid system called the RPM Grid. It's a combined grid
system
> that allows you to create heterogeneous relocatable RPMs. With the
standard
> grid, if you created an RPM with BRAMs , Slices and IOBs, the relative
locations
> between the different component types would shift as the macro was moved.
This
> doesn't occur with the RPM Grid.
>
> To use the new grid system, create the RPM  as usual, but using the
alternative
> coordinate system. The RPM needs to also contain the attribute
"RPM_GRID=GRID"
> to identify the coordinate system. This attribute can be placed on any
symbol in
> the macro. The coordinate system can be viewed in FPGA Editor. If you
select a
> Site in FED, note that an RPM_GRID coordinate is printed in the history
window.
>
> Sorry, there's no documentation yet. I'm working on an appnote.
>
> Regards,
> Bret Wade
> Xilinx Product Applications
>
> Kevin Neilson wrote:
>
> > In my opinion, Xilinx messed up when creating their coordinate systems.
> > They could have easily created a system in which the BRAM, slice, and
IOB
> > coordinates were all related, but they refused to do so.  The result
makes
> > the creation of placement scripts extremely difficult.  For example, if
you
> > wish to make a script that places registers next to a BRAM, it is very
> > difficult, because there is no relation between the BRAM at x,y and the
> > coords of the slice that surround it.  In fact, this is even different
for
> > every part.  The same is true for the IOBs that sit next to slices.  A
> > better coordinate system would have helped a lot in the development of
cores
> > which can be placed anywhere in any part.  Instead, if you have a core
that
> > requires IOBs close to core slices, you can't include the IOB relative
> > locations in the core and have to hand-place for each situation.  That's
not
> > how a core is supposed to work.
> >
> > "axilon" <axilon@attbi.com> wrote in message
> > news:3C3BE93D.8050002@attbi.com...
> > > How can I relate the package pin names and Slice XY locations in
Xilinx
> > > Virtex2 device?  I need it to put LOC constraint to IOB.
> > > I looked into the pinout_text_files at DataSource CD-ROM but its
> > > Slice X/Y Location data doesn't match with Physical names appeared at
> > > FPGA editor screen.  For an example, in 2v40cs144.txt file, X15Y14
> > > location has 6 pads (PAD21-PAD26) - that doesn't make sense since
> > > each Slice location can have max 4 pads.  Am I just discovered
> > > documentation error?
> > > Can any Xilinx folks out there answer my question?
> > > TIA
> > > Ax
> > >
>



Article: 38380
Subject: Re: Picking an FPGA
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 13 Jan 2002 02:53:22 -0500
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> To be fair, Altera does very well with state machines and the traditional random
> logic collection, and usually with less effort to get timing closure than with an
> equivalent Xilinx part.  It just isn't a great architecture for data path design.

I don't feel any special need to be "fair". But then I guess I hold a
bit of a grudge over the problem with their tools. It is obvious to me
that they have given up on making the old tool work correctly since all
of the newer parts us the new tool. They directly told me that the old
tool would not be fixed unless we found a class 1 bug (fatal, must be
fixed to keep running the tool) they would not have the manpower to work
on it. Meanwhile, I am stuck using the tool on existing designs that are
still being built and shipped, but need new downloads. 


> For a one size fits all, make sure your power supply is beefy enough to handle a
> high performance design.  It is pretty easy to get these puppies to disspate
> several watts.  I've run into a couple of boards now who's power regulators don't
> quite cut it.  One in particular that I am working with right now has a linear
> regulator on it that regulates the 1.8v for a pair of virtex 2000E from a 5 v
> supply using a TO220 package on a pretty small heatsink (note that that means the
> regulator disippates twice the combined power of the FPGAs).  The regulator is
> rated for 7A, but with that set up the regulator goes into thermal shutdown with
> the design drawing about 2A.  That happens with one Virtex loaded with a moderate
> design and the other one empty.

Thanks again for the advice. Our boards have 2 Amp switching regulators
on VccIO and VccInt to maximize power efficiency and minimize heat
dissipation. The only chips on the 1.8 volt regulator are the DSP at 1.5
Watts and the FPGA. So with a 3.6 Watt rating, we should be in good
shape with the PS. Especially since the FPGA can only get up to an
XC2S300E. Unless you know a way to put an XC2VxxxE part in the same
footprint???

The only thing that concerns me is the power up issue. I should have the
Xilinx POS under control with the 2 Amp rating of the PS. But the TI
DSP, 'C6711 has a warning that it can draw up to 2 Amps from the VccInt
core supply depending on the sequencing of the Vcc's. If this does not
happen at the low voltages that the Xilinx POS happens (<1 volt) then I
should be OK. But I will need to talk to TI about it. 

If it's not one thing it's another!!! 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 38381
Subject: Re: FPGA configuration
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 13 Jan 2002 03:13:04 -0500
Links: << >>  << T >>  << A >>
balakrishnan wrote:
> 
> Hi,
> In my design i'm using SPARTAN-II and SPARTAN-XL devices ,For
> configurtaion i like to use boundary scan(only during Board testing
> phase ) and slave serial mode.My doubt is only for boundary scan
> mode,it is possible to do daisy chain  sort of thing (connecting TDO
> of SPARTAN-II to TDI of SPARTAN-XL device)
> 
> Regards,
> Bala

I am interested in doing the same thing. But I am not clear about some
of the details of using this. I have read various documentation on how
to set up and exercise the chips on the board, but I am not clear on
what to use to drive the JTAG interface and how to talk to that unit. My
board has a TI DSP, an 8 bit uP, an FPGA and a CPLD. I would like to
daisy chain all four of these chips and still be able to use the JTAG
emulator on the DSP. Can I use the TI emulator board for both emulation
and boundry scan? 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 38382
Subject: Re: MSP430 + Xilinx via JTAG
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 13 Jan 2002 03:52:31 -0500
Links: << >>  << T >>  << A >>
DG_1 wrote:
> 
> Hi there,
> Has anybody tried to chain-up a MSP430 with any of JTAG-capable
> Xilinx chips and be able to programm both of them without problem(s)
> (MSP430 via IAR KickStart, Xilinx via JTAG programmer)?
> Or (re-arranged question)::
> Does IAR Kick-Start still recognizes MSP430 and/or allows other
> devices (other than MSP430) to be chained-up via JTAG?
> 
> Thanks in advance,
> -- D.G.


I will be doing exactly this in a month or two. I am building a board
with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL all in
one JTAG chain. Actually, I may leave the MSP430F148/9 out of the chain
depending on the answers to the questions I will be asking the vendors.
But I really want the rest of it in a single chain so that I can do
boundry scan testing on it all. The MSP430F148/9 will not be quite so
integrated into the rest of the board, so it does not have to be tested
that way. It is also important to be able to burn software into it
regarless of the state of the board. This will be used for initial board
test too. I am even considering using the MSP430F148/9 as a JTAG
interface for the JTAG chain. But we will see if I can get it all to
work together. 

If you have any results yourself, please let me know. Thanks!

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 38383
Subject: FS xilinx 963//Data I/O 2900 Programmers
From: tonys2@aol.com (TonyS2)
Date: 13 Jan 2002 08:58:25 GMT
Links: << >>  << T >>  << A >>
View at www.pearlone.com
or contact 
TonyS2@aol.com
Priced for quick turnover

Article: 38384
Subject: Homebrew computers using FPGA?
From: David Findlay <david_j_findlay@yahoo.com.au>
Date: Sun, 13 Jan 2002 10:44:35 GMT
Links: << >>  << T >>  << A >>
Is it possible to build a homebrew computer of some description using FPGA's? I know it won't be
as powerful as a PC, but I'm more interested in designing and building my own. Also does anyone
know of an FPGA simulator for Linux? Thanks,

David

Article: 38385
Subject: Re: Homebrew computers using FPGA?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 13 Jan 2002 11:48:32 +0100
Links: << >>  << T >>  << A >>
"David Findlay" <david_j_findlay@yahoo.com.au> schrieb im Newsbeitrag
news:pan.2002.01.13.20.44.34.131584.2125@yahoo.com.au...
> Is it possible to build a homebrew computer of some description using
FPGA's? I know it won't be
> as powerful as a PC, but I'm more interested in designing and building my
own. Also does anyone
> know of an FPGA simulator for Linux? Thanks,

www.fpgacpu.org

--
MfG
Falk





Article: 38386
Subject: Re: Homebrew computers using FPGA?
From: "cn99" <sailinger@263.net>
Date: Sun, 13 Jan 2002 19:44:43 +0800
Links: << >>  << T >>  << A >>
I'm afraid that kind of computer is only appropriate for special use, e.g. a
webserver with very limited ability. Besides, a FPGA-based computer won't
reach as high frequecy as required by many applications.

"David Findlay" <david_j_findlay@yahoo.com.au> wrote in message
news:pan.2002.01.13.20.44.34.131584.2125@yahoo.com.au...
> Is it possible to build a homebrew computer of some description using
FPGA's? I know it won't be
> as powerful as a PC, but I'm more interested in designing and building my
own. Also does anyone
> know of an FPGA simulator for Linux? Thanks,
>
> David



Article: 38387
(removed)


Article: 38388
Subject: Re: FPGA configuration
From: "z.karim" <z.karim@attbi.com>
Date: Sun, 13 Jan 2002 13:41:20 GMT
Links: << >>  << T >>  << A >>
Absolutely, the Xilinx tools will recognize both devices for you.


"balakrishnan" <kbkrishnan@tataelxsi.co.in> wrote in message
news:de79ba41.0201112341.3adedccd@posting.google.com...
> Hi,
> In my design i'm using SPARTAN-II and SPARTAN-XL devices ,For
> configurtaion i like to use boundary scan(only during Board testing
> phase ) and slave serial mode.My doubt is only for boundary scan
> mode,it is possible to do daisy chain  sort of thing (connecting TDO
> of SPARTAN-II to TDI of SPARTAN-XL device)
>
> Regards,
> Bala



Article: 38389
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 13 Jan 2002 14:46:03 +0000
Links: << >>  << T >>  << A >>


hamish@cloud.net.au wrote:

> Hal Murray <hmurray-nospam@megapathdsl.net> wrote:
> > Are your clocks derived from the same source, say one running
> > at X MHz and other running at X/2 MHz?  Then you and/or the tools
> > need to account for the difference is prop times on the two
> > different clock paths.  (Note that you have to think about hold
> > times as well as setup times.)
>
> > Are the clocks from two separate sources?  If so, then you need to
> > be thinking about metastability, not clock skew.
>
> They're completely unrelated clocks, all sourced off-chip. I
> know how to cope with metastability -- but the tools are including
> some (AFAICT irrelevant) clock skew in the calculations.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

I think I've had similar problems in the past and seen such clock skew
related false errors. From what I remember of the last time it comes
down to the situation where FF A on clock domain X feeds FF B on clock
domain Y and A, B are both placed in the 2 slices of the same CLB.
Because the routing delay is very low the TRACE tool sees a hold time
error due to X,Y clock skew.



Article: 38390
Subject: Re: modelsim
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 13 Jan 2002 14:52:54 +0000
Links: << >>  << T >>  << A >>


llossak wrote:

> i work use ise4.1 and modelsim,when i replace the old version modelsim.In ise4.1,when i simulate,it says:
> # WARNING: Could not open f:\eda_tools\Modeltech_5.5e\modelsim.ini from MODELSIM environment variable setting, using modelsim.ini instead
>
> how do i change?

Read the user manual section on ``ModelSim variables'' or some such. It explains just how & where ModelSim gets its initialisation and which
has priority over what.



Article: 38391
Subject: Re: Homebrew computers using FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Sun, 13 Jan 2002 15:32:04 GMT
Links: << >>  << T >>  << A >>
I beg to differ.  While you are not going to build a pentium class CPU in an
FPGA, the FPGA can support CPUs of reasonable complexity, and if the design
(including instruction set architecture) is done with the FPGA features in mind
you can get very respectable performance.  I did  a microcontroller design
several years ago that was a sort of a cross between a PIC and an RCA 1801 for a
4000XLA device.  That ran at over 60 MHz in a -09 speed grade device (it was
used for some general purpose processing in a digital photo print processor).  I
am aware of 6502, 6800, and 8051clones in FPGAs, and all run at least as fast as
the older technology chip they are cloning.  The Xilinx Microblaze and the
Altera NIOS are also very capable microprocessors implemented in the FPGA
fabric, and are much faster than many of the small microcontrollers available
out there.

Aside from the practical side, doing a processor design can be a tremendous
learning experience and is a very rewarding project.

cn99 wrote:

> I'm afraid that kind of computer is only appropriate for special use, e.g. a
> webserver with very limited ability. Besides, a FPGA-based computer won't
> reach as high frequecy as required by many applications.
>
> "David Findlay" <david_j_findlay@yahoo.com.au> wrote in message
> news:pan.2002.01.13.20.44.34.131584.2125@yahoo.com.au...
> > Is it possible to build a homebrew computer of some description using
> FPGA's? I know it won't be
> > as powerful as a PC, but I'm more interested in designing and building my
> own. Also does anyone
> > know of an FPGA simulator for Linux? Thanks,
> >
> > David

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38392
Subject: Re: speech recognition - active noise cancellation
From: Ray Andraka <ray@andraka.com>
Date: Sun, 13 Jan 2002 15:50:34 GMT
Links: << >>  << T >>  << A >>
I wasn't referring to the ANR headsets.  Virtually all of the aviation headsets
have noise cancelling microphones, which help to reduce background noise
TRANSMITTED into the intercom system as well as out the radio when the radio is
keyed.  This is separate from the ANR circuit (if equipped) which is part of the
earphone circuit, and is intended to augment the audio isolation provided by the
ear muffs between the listener and the environment.

I know several pilots who prefer the ANR headsets.  I personally don't care for
them.  When I use them, I feel an uncomfortable constant sound pressure (sounds
weird, I know) in place of the background noise.  I also worry that they would
mask audible engine noise that may provide early warning to an engine failure.

As for the first class headsets, I suspect that they use ANR headsets and that
the silent channel is the same as the others except that it has no signal so
that all you get is the effect of the ANR circuit.

Kevin Neilson wrote:

> My brother claims that on a recent flight in the first-class section (I have
> to take his word for it; it's been a while since I've been in that part of
> the plane) he had nice earphones and a channel on the in-flight audio system
> called "silent", which, when listened to, silenced the engine noise.  This
> sounds like active noise reduction, but I thought ANR required the
> noise-sensing mic to be close to the user's ear so the exact phase of the
> noise could be detected for cancellation.  It doesn't seem likely that a
> single anti-noise channel would work for all listeners in the plane.
>
> I think ANR for helicopter noise works much better than for white noise
> sources because helicopter noise is periodic over a decent interval of time
> so a predictive filter can predict the noise ahead of time and get the
> cancellation signal just right.  I know ANR is much less commonly used in
> planes vs. helicopters, but I'm not sure if that's because it's less
> effective or less necessary since planes are a little quieter and the ANR
> headsets are terribly expensive.
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3C40AAF1.84FC623@andraka.com...
> > Jerry,
> >
> > I don't know about motorcycles, but aviation headsets for piston powered
> light
> > aircraft (which are pretty noisy inside) use a noise cancelling microphone
> which
> > does a pretty decent job.  (you can see how bad it gets by covering the
> backside
> > ports in the microphone when you talk).  The noise cancelling mike has
> ports
> > facing the speaker's mouth and ports on the backside facing away from your
> > mouth.  The difference in the sound from the two ports is what is
> amplified.
> > These are not throat mikes, rather they are on a boom that you position
> > immediately in front of your lips.  If you can't kiss it, it is too far
> away.
> >
> > Jerry Avins wrote:
> >
> > > Leon Heller wrote:
> > > >
> > > > "Jerry Avins" <jya@ieee.org> wrote in message
> > > > news:3C3FA303.1B3A019E@ieee.org...
> > > > >
> > > > > Contact throat microphones were used in fighter planes 50 years ago.
> > > > > They discriminate against ambient noise very nicely indeed. 50 dB
> SNR
> > > > > improvements were cited, but I didn't make measurements myself.
> > > >
> > > > I looked into throat microphones when I worked on military radio human
> > > > factors.
> > > >
> > > > They deal with ambient noise OK, but the speech quality  is generally
> very
> > > > poor. They are also uncomfortable to wear (especially when they get
> wet, as
> > > > often happens with special services personnel), and generally need to
> be
> > > > pressed against the larynx with a finger to work properly. Users hate
> them!
> > > >
> > > > Leon
> > > > --
> > > > Leon Heller, G1HSM leon_heller@hotmail.con
> > > > http://www.geocities.com/leon_heller
> > > > Low-cost Altera Flex design kit: http://www.leonheller.com
> > >
> > > The ones used with the AIC-10 consisted of a pair built into the flight
> > > helmet, along with the ear phones. They were carbon mikes, and the poor
> > > response was due in part to muffling of the sound by the throat tissues.
> > > I designed a compensator filter for a next-generation AIC that sounded
> > > pretty good, but I don't know if it ever got used. The project was put
> > > aside while we built the Mercury capsule audio box, then I left the
> > > company. I didn't need a free hand to talk, nor did I find it
> > > particularly uncomfortable. Maybe the fly boys had better equipment.
> > >
> > > What is used on motorcycles nowadays? Rick? Anyone?
> > >
> > > Jerry
> > > --
> > > Engineering is the art of making what you want from things you can get.
> > > -----------------------------------------------------------------------
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38393
Subject: Re: Homebrew computers using FPGA?
From: Duane Clark <junkmail@junkmail.com>
Date: Sun, 13 Jan 2002 08:13:08 -0800
Links: << >>  << T >>  << A >>
David Findlay wrote:
 > Is it possible to build a homebrew computer of some description
 > using FPGA's? I know it won't be as powerful as a PC, but I'm more
 > interested in designing and building my own.

Sure. For example, here is a Sparc on an FPGA:
http://www.estec.esa.nl/wsmwww/leon/

A number of other smaller processors have also been ported to FPGAs.

 > Also does anyone know
 > of an FPGA simulator for Linux? Thanks,

Oddly enough, there are many Linux simulators. Take a look at the bottom 
of the page:
http://www.polybus.com/xilinx_on_linux.html



Article: 38394
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sun, 13 Jan 2002 19:03:17 -0000
Links: << >>  << T >>  << A >>
>They're completely unrelated clocks, all sourced off-chip. I
>know how to cope with metastability -- but the tools are including
>some (AFAICT irrelevant) clock skew in the calculations.

My guess is that the tools are setup to process the case
where the clocks are correllated and the skew does matter.

That seems like it will be much more common than your case.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 38395
Subject: Re: Homebrew computers using FPGA?
From: "Peter Ormsby" <faepete.deletethis@mediaone.net>
Date: Sun, 13 Jan 2002 19:20:52 GMT
Links: << >>  << T >>  << A >>
David,

Putting processors in FPGAs is becoming more common all the time.  Actually,
creating the processor is the easy part of making a useable
microprocessor/microcontroller system.  It's creating the 'C'
compilers/linkers and the Debuggers and the OSes and the development
environments that are really the trick.  However, having someone create a
processor in a FPGA has got to be one of the best ways to teach a person
about computer architectures.

Just as an example of how far some of the FPGA-specific processors have
gotten is to look at the Nios processor from Altera and the Microblaze from
Xilinx.  I can't speak to the Microblaze much since I haven't seen anything
other than marketing stuff, but the Nios processor has quite a collection of
the support tools.  In addition to the "free" (comes with the kit) GNU Pro
compiler/linker/debugger, there's a bunch of third-part stuff like the
Arriba (Viosoft) IDE, the Nucleus Plus (ATI) and Kros (Shugyo) RTOS.
There's even a version of Linux (Microtronix's uCLinux distro) that runs on
Nios as well as  TCP/IP stacks and a web server application that come with
Altera's Ethernet Development Kit.

Anyway, if you don't need Pentium/Athlon type performance, FPGAs really are
a viable platform for computing.  Check out the Nios information here...

http://www.altera.com/products/devices/excalibur/exc-nios_index.html

-Pete-

David Findlay <david_j_findlay@yahoo.com.au> wrote in message
news:pan.2002.01.13.20.44.34.131584.2125@yahoo.com.au...
> Is it possible to build a homebrew computer of some description using
FPGA's? I know it won't be
> as powerful as a PC, but I'm more interested in designing and building my
own. Also does anyone
> know of an FPGA simulator for Linux? Thanks,
>
> David



Article: 38396
Subject: Re: Homebrew computers using FPGA?
From: "Jan Gray" <jsgray@acm.org>
Date: Sun, 13 Jan 2002 11:39:23 -0800
Links: << >>  << T >>  << A >>

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:a1s7kv$sgjph$1@ID-84877.news.dfncis.de...
> www.fpgacpu.org

Thanks.

There's also an associated mailing list of ~390 people, see
http://groups.yahoo.com/group/fpga-cpu/ -- "This list is for discussion of
the design and implementation of field-programmable gate array based
processors and integrated systems.   It is also for discussion and community
support of the XSOC Project (see http://www.fpgacpu.org/xsoc). "

Jan Gray
Gray Research LLC




Article: 38397
Subject: Re: Homebrew computers using FPGA?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 14 Jan 2002 09:30:52 +1300
Links: << >>  << T >>  << A >>
David Findlay wrote:
> 
> Is it possible to build a homebrew computer of some description using FPGA's? I know it won't be
> as powerful as a PC, but I'm more interested in designing and building my own. 
>
> Also does anyone know of an FPGA simulator for Linux? Thanks,

 I've been told the Altera NIOS soft core can boot (some flavour of)
linux, 
(from a CD ROM Drive), so browse their info. 
 Xilinx will be chasing the same targets with their MicroBlaze offering.
-jg

Article: 38398
Subject: Re: FPGA configuration
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 13 Jan 2002 16:12:15 -0500
Links: << >>  << T >>  << A >>
I may not have understood the original question correctly, but I think
he is asking about board test rather than loading bit streams. Boundry
scan is used to exercise and read the IOs on each chip, normally to test
the connections of the chips and the board itself. 


"z.karim" wrote:
> 
> Absolutely, the Xilinx tools will recognize both devices for you.
> 
> "balakrishnan" <kbkrishnan@tataelxsi.co.in> wrote in message
> news:de79ba41.0201112341.3adedccd@posting.google.com...
> > Hi,
> > In my design i'm using SPARTAN-II and SPARTAN-XL devices ,For
> > configurtaion i like to use boundary scan(only during Board testing
> > phase ) and slave serial mode.My doubt is only for boundary scan
> > mode,it is possible to do daisy chain  sort of thing (connecting TDO
> > of SPARTAN-II to TDI of SPARTAN-XL device)
> >
> > Regards,
> > Bala

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 38399
Subject: Re: Homebrew computers using FPGA?
From: David Findlay <david_j_findlay@yahoo.com.au>
Date: Sun, 13 Jan 2002 21:54:27 GMT
Links: << >>  << T >>  << A >>
On Sun, 13 Jan 2002 21:44:43 +1000, cn99 wrote:
> I'm afraid that kind of computer is only appropriate for special use, e.g. a webserver with
> very limited ability. Besides, a FPGA-based computer won't reach as high frequecy as required
> by many applications.

Well what I'd hope to be doing is creating a simple computer, but with specialised logic
sections to speed up certain operations that take a while on conventional processors. So I
suppose although it wouldn't be as fast on some functions, it could be much faster on others.
I'm after preformance on complex simulations so physics logic would be useful.

David



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