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Messages from 38475

Article: 38475
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 15 Jan 2002 16:15:56 GMT
Links: << >>  << T >>  << A >>
I often have related clocks, such as 1x and 2x produced by the DLL.
Early in the virtex life history I saw instances where data did not get
passed cleanly between domains, despite the indications that it can be
in the documentation.  It looked like jitter on the DLL outputs was the
culprit.  Anyway, since then I have always treated related clocks
produced by the DLL as coherent asynchronous clocks, which means the
skew analysis is needed.

That said, there ought to be a switch available on a per signal basis to
turn on/off the skew.  AFAIK, there is not one now.

hamish@cloud.net.au wrote:

> Hal Murray <hmurray-nospam@megapathdsl.net> wrote:
> >>They're completely unrelated clocks, all sourced off-chip. I
> >>know how to cope with metastability -- but the tools are including
> >>some (AFAICT irrelevant) clock skew in the calculations.
>
> > My guess is that the tools are setup to process the case
> > where the clocks are correllated and the skew does matter.
>
> > That seems like it will be much more common than your case.
>
> I'd be interested to know if that really is more common (show of
> hands from the other newsgroup readers)?
>
> This is the first design I've worked on (from an admittedly small
> sample) which has any related clocks at all -- and most of them
> still aren't (and there's lots of them).
>
> So I live with FROM:TO's slightly screwy analysis of this
> case because it's certainly better than nothing.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 38476
Subject: Re: RS232 on Atmel ATSTK40 board
From: "Bernd Scheuermann" <scheuermann@aifb.uni-karlsruhe.de>
Date: Tue, 15 Jan 2002 17:38:32 +0100
Links: << >>  << T >>  << A >>
Hi,

As far as I know I need privilege level 0 to get access to the serial port
using Windows 2000. Usual applications only have privilege level 3.
Therefore you need a special driver as an interface. But I'm not sure about
that.
Is there anywhere source code available to access the serial port using
Windows 2000, preferably a sort of C-library? I couldn't find anything.

Thanx a lot!
bye,


Bernd


"Jan Pech" <j.pech@sh.cvut.cz> schrieb im Newsbeitrag
news:a21fj8$15l2$1@ns.felk.cvut.cz...
> >
> > 1) UART circuit to be implented on the FPGA.
>
> Look at http://www.opencores.org
>
> > 2) Interface software running on Windows 2000.
> > 3) Since the serial port cannot be addressed directly, an extra driver
is
> > required.
>
> Serial port can be accessed like a file. No extra driver is required.
>
> Jan
>
>
>



Article: 38477
Subject: Re: MSP430 + Xilinx via JTAG
From: "Geir Atle Ward" <gaward@online.no>
Date: Tue, 15 Jan 2002 16:40:52 GMT
Links: << >>  << T >>  << A >>
Here:
ftp://www.atmel.com/pub/atmel/bsdl.zip
Geir A

"DG_1" <dgacina@san.rr.com_no.spam> wrote in message
news:6YN08.101893$AI.27135658@typhoon.san.rr.com...
> Thanks Damir.
> Where I can get that file?
> (HR: Postovanje! Gdje mogu 'podici' taj filek?)
> -- D.G.
>
> "Damir Danijel Zagar" <dzagar@srce.hr> wrote in message
> news:a1urs3$ub8$1@sunce.iskon.hr...
> > Just to mention... BSDL file for ATmega128 is available.
> >
> > Damir
> >
> > "DG_1" <dgacina@san.rr.com_no.spam> wrote in message
> > news:lbp08.100459$AI.26190323@typhoon.san.rr.com...
> > > Thanks 'rickman'.
> > >   The only problem I 'foresee' is the fact that IAR Kickstart doesn't
> > > have any capability of adding/editing BSDL files (or I missed
> something).
> > > Therefore, I don't see the way how to use debugging features
> > > of IAR Kickstart when  _more_  than one chip is in the same chain.
> > >   I guess, designers of IAR's tool-set didn't (intentionally?)
> > > though-out that possibility. Also, I guess, from Xilinx's perspective,
> > > having MSP430 in the same chain is no big deal, just add BSDL
> > > file for TI's part to Xilinx's 'JTAG programmer' tool.
> > >   In the past I've used JTAG to chain-up devices (Xilinx, Lattice)
> > > but always from the same manufacturer, I've never mixed-up
> > > different chips, from different manufacturers, neither I added MPUs
> > > into the chain.  now I guess the only way to check it up is to make
> > > the actual circuitry and then 'everything is in God's hands'.
> > > (Well, the same problem is applicable to Atmel AVmega128
> > > to be chained-up with other JTAG-capable chips)
> > >
> > >
> > > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > > news:3C414ACF.EA8194EA@yahoo.com...
> > > > DG_1 wrote:
> > > > >
> > > > > Hi there,
> > > > > Has anybody tried to chain-up a MSP430 with any of JTAG-capable
> > > > > Xilinx chips and be able to programm both of them without
problem(s)
> > > > > (MSP430 via IAR KickStart, Xilinx via JTAG programmer)?
> > > > > Or (re-arranged question)::
> > > > > Does IAR Kick-Start still recognizes MSP430 and/or allows other
> > > > > devices (other than MSP430) to be chained-up via JTAG?
> > > > >
> > > > > Thanks in advance,
> > > > > -- D.G.
> > > >
> > > >
> > > > I will be doing exactly this in a month or two. I am building a
board
> > > > with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL
all
> in
> > > > one JTAG chain. Actually, I may leave the MSP430F148/9 out of the
> chain
> > > > depending on the answers to the questions I will be asking the
> vendors.
> > > > But I really want the rest of it in a single chain so that I can do
> > > > boundry scan testing on it all. The MSP430F148/9 will not be quite
so
> > > > integrated into the rest of the board, so it does not have to be
> tested
> > > > that way. It is also important to be able to burn software into it
> > > > regarless of the state of the board. This will be used for initial
> board
> > > > test too. I am even considering using the MSP430F148/9 as a JTAG
> > > > interface for the JTAG chain. But we will see if I can get it all to
> > > > work together.
> > > >
> > > > If you have any results yourself, please let me know. Thanks!
> > > >
> > > > --
> > > >
> > > > Rick "rickman" Collins
> > > >
> > > > rick.collins@XYarius.com
> > > > Ignore the reply address. To email me use the above address with the
> XY
> > > > removed.
> > > >
> > > > Arius - A Signal Processing Solutions Company
> > > > Specializing in DSP and FPGA design      URL http://www.arius.com
> > > > 4 King Ave                               301-682-7772 Voice
> > > > Frederick, MD 21701-3110                 301-682-7666 FAX
> > > >
> > >
> > >
> >
> >
> >
>
>



Article: 38478
Subject: Altera Compiling Error..WHY?????
From: "Daniel Yap" <daniu_yap@hotmail.com>
Date: Wed, 16 Jan 2002 00:48:43 +0800
Links: << >>  << T >>  << A >>
my case is like this, i need to compile the wallace booth mul, the problem
is, when i compile it as .vhd code, the compiler cannot run it, however,
after i use the FPGA Express to synthesis it and export it as .edf format
and do the compiling in Altera MaxPlus2 10, it can compile it and gave me
the right answer.

what is the reason? it said that unsupported feature error: non locally
static bounds are not supported!!

anyone could help me? I can send you the vhdl code and help me to check. I
really need this help as my dateline for the presentation is just next
month. For your information, I am designing a digital filter.



Article: 38479
Subject: Re: Falling edge in PLD
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 15 Jan 2002 18:01:47 +0100
Links: << >>  << T >>  << A >>
"Martin Fischer" <Martin.Fischer@fzi.de> schrieb im Newsbeitrag
news:a211n2$hqq@absalom.fzi.de...
> Thanks to all,
>
> but I changed my logic and added a new process.
> Now I have no faults.
>
> But I don't understand, why I can't toggle signals at the falling edge
:-((

You can. But its a good idea to use some kind of clear design techniques. So
a CLOCK signal is noting but a CLOCK signal and only used to detect its
falling or rising edge. A DATA signal is only a DATA signal and its value
has tho be evaluated inside a pure combinatorical process or inside a
clocked proccess but NEVER. SO something like this is no good practive.

process(x .....,data_signal)
begin
if rising_edge(data_signal)
....


 I know, there are exeptions from this rules, but they should only be used
by people who REALLY know what they are doing. I assume this number is
orders of magnitude smaller than the number of people doing digital design
;-))

--
MfG
Falk




Article: 38480
Subject: Re: SDH Pointer generator and Pointer interpreter
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 15 Jan 2002 18:03:04 +0100
Links: << >>  << T >>  << A >>
"" <dragon@cei.co.kr> schrieb im Newsbeitrag
news:OIN08.10895$Jz1.1216610@news.bora.net...
> I am looking for SDH Pointer generator and interpreter(AU3,AU4) VHDL cores
> and VHDL examples
> Can someone help me, please ?

Xilinx and Altera are providing IP cores for this. But I dont think you will
get a VHDL description from them.

--
MfG
Falk





Article: 38481
Subject: Re: Hard macro for Xilinx FPGA
From: Bret Wade <bret.wade@xilinx.com>
Date: Tue, 15 Jan 2002 10:07:52 -0700
Links: << >>  << T >>  << A >>
Hi Philippe,

I assume that you are deleting the pads, not just unplacing them. When you
remove the pad, the net involved becomes an unrouted net with a single pin. The
green dot is the "rat's nest" display for the net. The net actually needs to be
removed too. Rather than relying on your ability to find the rat's nest dot
visually, I suggest making a note of the pin involved, before deleting the pad
and net. You could then use the "find pin" dialog to select it later when
configuring the external pins.

Regarding automation, there is some scripting functionality built into FPGA
editor that would allow you to automate the macro creation. You can record a
certain function (Tools-->Scripts-->Begin Recording) to get an example of the
editor commands involved, then create a script that performs the same command
for all pads and can be run in FPGA Editor (Tools-->Scripts-->Playback). What I
would do in your position would be to write a perl script that parses the output
of xdl (netlist representation of .ncd)  and writes an FPGA Editor script to
remove all of the pads and IO nets, and then create the external pin definitions
of the macro.

The commands look like this:

select comp "q<3>"
delete
select -k net "N_q<3>"
delete
select pin "CLB_R12C20.YQ"
add extpin
post attr pin CLB_R12C20.YQ
setattr pin CLB_R12C20.YQ  external_name Q<3>
unpost pin "CLB_R12C20.YQ"

Bret


Philippe Robert wrote:

> Hi there,
>
> I am designing functions in VHDL for a Virtex II, that are likely to be
> re-used (FPGAExpress+Xilinx 4.1i). I have seen that it is possible to do
> hard macros with the Xilinx FPGA Editor. The procedure is quite long. It
> consists in 'unplacing' the pads and inserting macro internal pins. Once it
> is all done, then you can reuse it by instantiating a black box in some VHDL
> code. That's the procedure I have found in a Xilinx application note.
>
> When unplacing existing pads, the tool also removes some routing and inserts
> a green dot where the removed routes starts from. The main problem is to
> find the green dot, to replace it by macro internal pins. Sometimes, it is
> almost impossible to find those dots when there are inout pads or when
> Flip-Flops are inserted in pads.
>
> The procedure is really long, especially when there are about 100 I/O on the
> block to be turned into a hard macro.
>
> Does anyone know any alternative way to generate hard macros, or similar
> blocks ?
>
> Thanks.
> Philippe.


Article: 38482
Subject: Re: Virtex-2 Frequency Synhtesis
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 15 Jan 2002 17:12:09 +0000
Links: << >>  << T >>  << A >>


Austin Lesea wrote:

> Andreas,
>
> The values must be modified in the bitstream, and then the DCM must be
> reset.
>
> I suggest that you run two designs that are identical except for the M and D
> values.  Generate the bitstreams (use the option that gives you that ascii
> .rbt file).  Do a diff on the two files.  You will see the different 32 bit
> frames with the two ten bit register values (not all ten bits are used).
>
> You may then generate a bitstream with the CRC turned off (bitgen option) so
> you may generate any bitstream values you wish for M and D by hacking the M
> and D bit locations.
>

Austin,

When I first read the Virtex-2 docs the M & D ranges were supposed to be 0-4095.
I believe that after you got the ES parts back this had to be substantially
reduced,  to 0-31 IIRC? If so has the range increased for the second spin
silicon ?



Article: 38483
Subject: Re: RS232 on Atmel ATSTK40 board
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 15 Jan 2002 12:29:07 -0500
Links: << >>  << T >>  << A >>
Bernd Scheuermann wrote:

> Hi,
>
> As far as I know I need privilege level 0 to get access to the serial port
> using Windows 2000. Usual applications only have privilege level 3.
> Therefore you need a special driver as an interface. But I'm not sure about
> that.
> Is there anywhere source code available to access the serial port using
> Windows 2000, preferably a sort of C-library? I couldn't find anything.

If you know the type of UART used by the serial port of your PC then you could
access the registers of the UART directly in the port address space.  There are
several free packages that let you get to the port addresses in WinNT and
Win2000.

One package is the DriverLINX software and driver.  Check for it at
www.sstnet.com.  We also have an installation file for it (port95nt.exe) at
http://www.xess.com/ho07000.html.

Another option is UNIIO.  The source for this is completely available so you
can compile the parts you need.  Look for it at www.bbdsoft.com.




>
>
> Thanx a lot!
> bye,
>
> Bernd
>
> "Jan Pech" <j.pech@sh.cvut.cz> schrieb im Newsbeitrag
> news:a21fj8$15l2$1@ns.felk.cvut.cz...
> > >
> > > 1) UART circuit to be implented on the FPGA.
> >
> > Look at http://www.opencores.org
> >
> > > 2) Interface software running on Windows 2000.
> > > 3) Since the serial port cannot be addressed directly, an extra driver
> is
> > > required.
> >
> > Serial port can be accessed like a file. No extra driver is required.
> >
> > Jan
> >
> >
> >




--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 38484
Subject: Re: Radiation Resistance
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 15 Jan 2002 18:33:28 +0100
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag
news:3C43254A.CE232376@xilinx.com...
> Falk,
>
> Use "google.com" to search for:
>
> single event upset
> single event error pmos
> single event error cmos
> single event error nmos
>
> Lots of good pdf's to wander through.  Lots of good tests done at Sandia,
NASA,
> ESA, etc.

Thanks a lot.
--
MfG
Falk






Article: 38485
Subject: Flexbus and Altera
From: "Annette Van Benthum" <a.vanbenthum@pandora.be>
Date: Tue, 15 Jan 2002 17:44:14 GMT
Links: << >>  << T >>  << A >>
Hi ,

I am looking for some info concerning the Flexbus core.

Does someone allready used it ?
In wich speed grade and Altera device did you do it.

Kind regards,

Ann



Article: 38486
Subject: Re: Virtex-2 Frequency Synhtesis
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 15 Jan 2002 10:26:40 -0800
Links: << >>  << T >>  << A >>
Rick,

The part was never intended to support M and D values to 4095.  The intent was to
find out just where it did work to.

The measured performance was such that with values > 32, the jitter became too large
as a % of the period, making the feature much less useful.

As well, to verify M and D values for {1,32} requires thousands of patterns to be
run over hundreds of frequencies (over hundreds of parts) to characterize, not to
mention production test.  In keeping with our commitment to the customer to provide
a quality part, we decided to limit the M and D values to less than what the part
was capable of to be sure all values worked in actual designs with other resources
in a production environment.

Future silicon is not intended to operate at any values greater than 32.  The basic
issue is the Q of the oscillator, or resonator used.  In silicon, with devices, this
is limited to a practical value of about 100.  Thus, the oscillator can not for very
long before it accumulates a phase error (jitter) from the desired phase.  Perhaps
with integrated inductors, we could achieve a Q of 200, but even that is beyond the
technology.  Maybe MEMS?  Tuning forks?

I apologize for not catching the 4095 in the original information.  I was
responsible for checking the info, and preventing just that kind of slip.  I missed
it.  The bits are free in the memory, and thus they are there for future use.  It
was never intended that we actually support such values.  It is also true that such
M and D values require a quartz crystal for stability, so I am surprised anyone took
those numbers seriously when they were first published ... (they were impossible to
achieve  -- at least to anyone skilled in the art of frequency synthesis).

In other news, here is an excerpt from an email for supporting partial
reconfiguration:

------snip-----------


Hi,

I did some poking around (thanks), and I have some more info for you.  If you want
to do change your M and D values in a few designs via ICAP, it turns out it's really
pretty simple (in theory, at least).  Here are my basic instructions:

Generate your complete design (initial.ncd) with DCMs including initial M and D
values, and from it generate your design's complete bitstream (called initial.bit,
for instance).  If you're going to configure your M and D values with ICAP, be sure
to put ICAP in your design.  Of course, you can also use other configuration modes
like the config pads or JTAG to partially reconfigure.

Through whatever means you find easiest (I prefer xdl, many prefer fpga_editor) go
in and hand edit your initial.ncd design, changing only the appropriate M and D
values.  Call this new design new.ncd.  Then run bitgen on new.ncd with "-r
initial.bit" and  "-g ActiveReconfig:Yes" as bitgen options.  This will generate
new.bit, a bitstream which addresses and changes only the configuration frame that
is different between new.ncd and initial.ncd.

The ActiveReconfig:Yes switch is used to prevent extra GSR pulses or anything else
with global config signals.

Don't forget you'll need to reset your reconfigured DCMs!

Anyway, if you want you can generate a slew of new bitstreams for a slew of M/D
values. You could then store all those reconfiguration bitstreams in your BRAM and
swap at will.  For a 2v1000, a single new.bit bitstream is under 1.5K bits.

-------snip------------

Austin





Rick Filipkiewicz wrote:

> Austin Lesea wrote:
>
> > Andreas,
> >
> > The values must be modified in the bitstream, and then the DCM must be
> > reset.
> >
> > I suggest that you run two designs that are identical except for the M and D
> > values.  Generate the bitstreams (use the option that gives you that ascii
> > .rbt file).  Do a diff on the two files.  You will see the different 32 bit
> > frames with the two ten bit register values (not all ten bits are used).
> >
> > You may then generate a bitstream with the CRC turned off (bitgen option) so
> > you may generate any bitstream values you wish for M and D by hacking the M
> > and D bit locations.
> >
>
> Austin,
>
> When I first read the Virtex-2 docs the M & D ranges were supposed to be 0-4095.
> I believe that after you got the ES parts back this had to be substantially
> reduced,  to 0-31 IIRC? If so has the range increased for the second spin
> silicon ?


Article: 38487
Subject: Re: Altera Compiling Error..WHY?????
From: Alan Nishioka <alann@accom.com>
Date: Tue, 15 Jan 2002 12:06:38 -0800
Links: << >>  << T >>  << A >>
Since it compiles fine on another compiler, I would suspect that the 
code is fine and the Altera VHDL complier is missing something.  I know 
the Altera Verilog complier doesn't allow arrays, for example.  I would 
not be surprised that the Altera VHDL complier is also not complete.

Alan Nishioka
alann@accom.com

Daniel Yap wrote:

>my case is like this, i need to compile the wallace booth mul, the problem
>is, when i compile it as .vhd code, the compiler cannot run it, however,
>after i use the FPGA Express to synthesis it and export it as .edf format
>and do the compiling in Altera MaxPlus2 10, it can compile it and gave me
>the right answer.
>
>what is the reason? it said that unsupported feature error: non locally
>static bounds are not supported!!
>
>anyone could help me? I can send you the vhdl code and help me to check. I
>really need this help as my dateline for the presentation is just next
>month. For your information, I am designing a digital filter.
>


Article: 38488
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 15 Jan 2002 12:07:26 -0800
Links: << >>  << T >>  << A >>
I have a simple, quick-and-dirty method of transferring data between unrelated
clock domains:
Transfer twice in a row, and then compare the two values. If they are identical,
the data is good. If they differ, discard the data.
This requires that the source is inherently stable for multiple transfers, but
that can always be arranged  with an extra synchronous register
This method can even be implemented in software, and has, for decades, e.g. when
reading count values from the Am9517..

Peter Alfke




Article: 38489
Subject: Re: Leonardo + Xilinx tools help
From: Rodolfo Jardim de Azevedo <rjazevedo@NOSPAM.ic.unicamp.br>
Date: Tue, 15 Jan 2002 18:34:48 -0200
Links: << >>  << T >>  << A >>
Mike,

	First I tried using the .ucf constraints file. After I put the
constraints in the leonardo .tcl script. They didn't work. I tried
without constraints. And then I got another error which I don't
understand. Lots of lines like this
ERROR:NgdBuild:432 - logical block 'tri_data(4)' with type 'TRI' is
unexpanded

	I'm really confused in this project. I got the full flow running using
Xilinx Foundation 3.1i for Windows, but I can't make it work using
leonardo+xilinx tools.

		Thanks for any help.

			Rodolfo

Mike Treseler wrote:
> 
> Rodolfo Jardim de Azevedo wrote:
> 
> >         I'm designing using Leonardo Spectrum (2001d) and passing the EDIF
> > files to Xilinx tools. But I'm having problems using vectors. All the
> > tools are for Solaris.
> >         The synthesis goes right, but when I run the NGD using the constraints
> > file mainly for pinout specification. I get messages like this:
> > ERROR:NgdBuild:397 - Could not find NET 'ram_address1(10)' in design
> 
> Consider leaving the pinout stuff
> out of your code.
> 
> Run the Xilinx place and route and then edit
> the Xilinx pin assignment file directly.
> 
>    --Mike Treseler

Article: 38490
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 15 Jan 2002 21:38:55 +0100
Links: << >>  << T >>  << A >>
hamish@cloud.net.au writes:

> Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote:
> > You have two cross-domain signals here, but I guess you knew that. Do
> > you have a constraint there too?
> 
> Yes I do.
> 
> > It's hard to understand what you are doing. Couldn't you just clock
> > the middle FF with LSCLK? If your Pulse is one LSCLK period long you
> > get metastability problems when CE comes in the metawindow of HSCLK.
> 
> I have a pulse for one cycle of LSCLK. I sample it in HSCLK and
> detect the rising edge; I use the detected edge to clock the
> sampling flip flops with HSCLK.

Ah, more to it. Do you have VHDL to show?
 
> > Swapping HSCLK for LSCLK you instead get metastability problem when D
> > changes in the metawindow of LSCLK.
> 
> > You said coherent, I'm assuming you have a several values
> > (e.g. counter) you want to sample at the same time?
> 
> That's right. I need all the bits from the same sample
> ie I can't tolerate a few bits from one clock and the rest from
> another. Otherwise I could just deal with metastability and
> wouldn't need the sampling step.

I thought you had skew in the pulse to the "middle" FF. You stil can
have problems with metastability in the pulse, but perhaps not as
severe.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 38491
Subject: Re: Leonardo + Xilinx tools help
From: Rodolfo Jardim de Azevedo <rjazevedo@NOSPAM.ic.unicamp.br>
Date: Tue, 15 Jan 2002 18:52:00 -0200
Links: << >>  << T >>  << A >>
Tom Dillon,

  I've noticed this. But it is not the case. I use () in my constraint
file and the edif uses this too. Here is a piece of edif file without
pinout constraints:
  (cell xsv800 (cellType GENERIC)
   (view xsv800_arch  (viewType NETLIST)
    (interface 
     (port resetn (direction INPUT))
     (port clk (direction INPUT))
     (port (array (rename ram_address0 "ram_address0(18:0)") 19
)(direction OUTPUT))
     (port (array (rename ram_address1 "ram_address1(18:0)") 19
)(direction OUTPUT))
     (port (array (rename ram_data "ram_data(31:0)") 32 )(direction
INOUT))
     (port (array (rename ram_ce "ram_ce(1:0)") 2 )(direction OUTPUT))
     (port (array (rename ram_oe "ram_oe(1:0)") 2 )(direction OUTPUT))
     (port (array (rename ram_we "ram_we(1:0)") 2 )(direction INOUT))
     (port RXD1 (direction INOUT))
     (port TXD1 (direction INOUT))
     (port RXD2 (direction INOUT))
     (port TXD2 (direction INOUT))
     (port (array (rename BAR "BAR(8:2)") 7 )(direction INOUT))
     (port error (direction OUTPUT))
     (port flash_ce (direction OUTPUT)))

  If I use the constraints file, I get this edif:

  (cell xsv800 (cellType GENERIC)
   (view xsv800_arch  (viewType NETLIST)
    (interface 
     (port resetn (direction INPUT)
      (property PIN_NUMBER (string "174")))
     (port clk (direction INPUT)
      (property PIN_NUMBER (string "89")))
     (port (array (rename ram_address0 "ram_address0<18:0>") 19
)(direction OUTPUT)
      (property PIN_NUMBER (string "229")))
     (port (array (rename ram_address1 "ram_address1<18:0>") 19
)(direction OUTPUT)
      (property PIN_NUMBER (string "96")))
     (port (array (rename ram_data "ram_data<31:0>") 32 )(direction
INOUT)
      (property PIN_NUMBER (string "94")))
     (port (array (rename ram_ce "ram_ce<1:0>") 2 )(direction OUTPUT)
      (property PIN_NUMBER (string "109")))
     (port (array (rename ram_oe "ram_oe<1:0>") 2 )(direction OUTPUT)
      (property PIN_NUMBER (string "95")))
     (port (array (rename ram_we "ram_we<1:0>") 2 )(direction INOUT)
      (property PIN_NUMBER (string "68")))
     (port RXD1 (direction INOUT)
      (property PIN_NUMBER (string "160")))
     (port TXD1 (direction INOUT)
      (property PIN_NUMBER (string "152")))
     (port RXD2 (direction INOUT))
     (port TXD2 (direction INOUT))
     (port (array (rename BAR "BAR<8:2>") 7 )(direction INOUT))
     (port error (direction OUTPUT)
      (property PIN_NUMBER (string "171")))
     (port flash_ce (direction OUTPUT)
      (property PIN_NUMBER (string "170"))))

and I don't understand why it changes the () by <> and put the
PIN_NUMBER assigning only one pin number to the vector signal. I set the
pinout information for every pin. 

  A piece of the leonardo constraint file (.ncf):
NET ram_address0(18) LOC = 229;
NET ram_address0(17) LOC = 230;
NET ram_address0(16) LOC = 231;
NET ram_address0(15) LOC = 232;
NET ram_address0(14) LOC = 234;
NET ram_address0(13) LOC = 235;
NET ram_address0(12) LOC = 236;
NET ram_address0(11) LOC = 237;
NET ram_address0(10) LOC = 238;
ET ram_address0(3) LOC = 194;
.
.
.
NET ram_address0(2) LOC = 195;
NET ram_address0(1) LOC = 199;
NET ram_address0(0) LOC = 200;
NET ram_address1(11) LOC = 107;
NET ram_address1(10) LOC = 108;
NET ram_address1(9) LOC = 53;
NET ram_address1(8) LOC = 54;
NET ram_address1(7) LOC = 55;
NET ram_address1(6) LOC = 56;
NET ram_address1(5) LOC = 57;


  I have 2 memory banks tied to different pins, each one is 512 x 16. I
want to drive them using the same address to make a 512 x 32. ngdbuild
complains about ram_address1 but not about ram_address0. They are
assigned in VHDL as
	ram_address0 <= address;
	ram_address1 <= address;
so they should have the same values, they are of the same type and
everything equal. 

  I got similar problem in some control signals which should be
duplicated.

  Can anyone help me?

	Thanks in advance,

		Rodolfo


Tom Dillon wrote:
> 
> I would look in the edif file and make sure that your names exactly match.
> Make sure they aren't listed with  NET ram_address1<10> as apposed to  NET
> ram_address1(10).
> 
> Some tools use different brackets for the vector numbers.
> 
> Good luck,
> 
> Tom Dillon
> Dillon Engineering, Inc.
> http://www.dilloneng.com
> 
> >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
> 
> On 1/14/02, 11:10:44 AM, Rodolfo Jardim de Azevedo
> <rjazevedo@N_O_S_P_A_M.ic.uincamp.br> wrote regarding Leonardo + Xilinx
> tools help:
> 
> > Hi,
> 
> >       I'm designing using Leonardo Spectrum (2001d) and passing the EDIF
> > files to Xilinx tools. But I'm having problems using vectors. All the
> > tools are for Solaris.
> >       The synthesis goes right, but when I run the NGD using the
> constraints
> > file mainly for pinout specification. I get messages like this:
> > ERROR:NgdBuild:397 - Could not find NET 'ram_address1(10)' in design
> > 'xsv800'.
> >    NET entry is 'NET ram_address1(10) LOC = 108;
> 
> >       I don't know what is happening. I get this message for all vector
> > signals.
> >       Can anyone help me?
> 
> >               Thanks in advance,
> 
> >                       Rodolfo

-- 
The Xingo Project                         | Rodolfo Jardim de Azevedo
Code Optimization for Embedded Systems    | Computer Science PhD Student
An Open Software Initiative of IC-UNICAMP | rjazevedo@ic.unicamp.br

Article: 38492
Subject: Re: Leonardo + Xilinx tools help
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 15 Jan 2002 12:52:31 -0800
Links: << >>  << T >>  << A >>
Rodolfo Jardim de Azevedo wrote:
> I tried
> without constraints. And then I got another error which I don't
> understand. Lots of lines like this
> ERROR:NgdBuild:432 - logical block 'tri_data(4)' with type 'TRI' is
> unexpanded

Have you made a setting to tell the Xilinx place and route
that the .edf file is of type "Exemplar" ?

   --Mike Treseler

Article: 38493
Subject: Re: Altera Compiling Error..WHY?????
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 15 Jan 2002 13:02:51 -0800
Links: << >>  << T >>  << A >>
Daniel Yap wrote:
> 
> my case is like this, i need to compile the wallace booth mul, the problem
> is, when i compile it as .vhd code, the compiler cannot run it, however,
> after i use the FPGA Express to synthesis it and export it as .edf format
> and do the compiling in Altera MaxPlus2 10, it can compile it and gave me
> the right answer.
> 
> what is the reason? 

The reason is that MaxPlus2 is a place and route program,
not a synthesizer.

FPGA Express, Synplicity and Leonardo are synthesizers.

 --Mike Treseler

Article: 38494
Subject: path for Vital component in assert?
From: david@therogoffs.com (David Rogoff)
Date: 15 Jan 2002 13:42:37 -0800
Links: << >>  << T >>  << A >>
Hi.

I am doing a gate-level/back-annotated simulation of am FGPA. It's a
Xilinx Virtex E, using the simprims library (ISE 4.1).  I'm using
Cadence ncvhdl/ncsim.  I've got a few timing violation messages, but
they don't have the path to the offending component and/or the signal
names involved.  Here's one example:

ASSERT/WARNING (time 8970249 PS) from procedure
@ieee.VITAL_Timing:ReportViolation
*/X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;  Expected :=
0.271 NS; Observed := 0.11 NS; At : 8970.249 NS

I'm used to Verilog, and having the full path shown in the timing
violation.  Is this a problem with the Xilinx library?  Is there some
switch setting I can change?

Thanks,

 David

Article: 38495
Subject: Re: FPGA and CCD : any experience?
From: kayrock66@yahoo.com (Jay)
Date: 15 Jan 2002 14:42:50 -0800
Links: << >>  << T >>  << A >>
I'll post this for everyone, there are of course other vendors of
these logic level interface type CMOS image sensors, the Conexant ones
are just the ones I've used.

Start here, or search yourself on the Conexant web site for "Visual
Imaging"

http://www.conexant.com/default.sph/SaServletEngine.class/Web/products/productfamilies.jsp?ProdFamId=6

Regards


martinb@magma.ca (M.B.) wrote in message news:<3c3efd88.6347672@news.magma.ca>...
> Jay 
> I would be interested im playing with such a design. 
> Could you e-mail me more info, ie schematics parts lists and code.
> 
> Thanks
> mpbrown@magma.ca
> 
> 
> On 10 Jan 2002 15:26:25 -0800, kayrock66@yahoo.com (Jay) wrote:
> 
> >I've used Altera FPGA's with CMOS area sensors.  The nice thing abut
> >using CMOS imagers is that they are essentially digital parts at the
> >I/O's.  The complicated clocking and bias is handled on-chip.  In
> >general, you supply a digital clock, 3.3V supply, and an I2C interface
> >and you get Bayer pattern out on a parallel bus.  Since you have so
> >much signal (outdoor application), the relative insensitivity of CMOS
> >sensors as compared to CCD should not be a problem.  A bunch of people
> >make them; I've used several of Conexant's sensors.
> >
> >Regards
> >
> >
> >Gacquer William <wgacquer@yahoo.fr> wrote in message news:<3C3C5C80.5080702@yahoo.fr>...
> >> Hello
> >> 	has anybody tried to connect a FPGA to several CCDs ( for imaging 
> >> purpose, of course ? )
> >> 	I am new to FPGA programming.
> >> 	Regards,
> >> 	William Gacquer

Article: 38496
Subject: Re: Altera Compiling Error..WHY?????
From: kayrock66@yahoo.com (Jay)
Date: 15 Jan 2002 14:55:24 -0800
Links: << >>  << T >>  << A >>
This may not be the answer you want, but I think the compiler told you
the problem.  It just isn't a very sophisticated sythesizer.  The fact
that Altera GIVES you a vendor specific synthesizer
(Exemplar/Synopsys) is kind of a hint that they realize the weakness
of their own solution.  I've had it make wrong gates without warning
on some very simple code on earlier versions.

BTW, if your ultimate target technology is FPGA, you're probably
better off instantiating or inferring one of Altera's macros (LPM's)
for those multipliers instead of using the generic source code for a
fast multiplier architecture (Wallace-Booth) that you might typically
use in an ASIC.

Regards

"Daniel Yap" <daniu_yap@hotmail.com> wrote in message news:<3c445ce2$1_2@news.tm.net.my>...
> my case is like this, i need to compile the wallace booth mul, the problem
> is, when i compile it as .vhd code, the compiler cannot run it, however,
> after i use the FPGA Express to synthesis it and export it as .edf format
> and do the compiling in Altera MaxPlus2 10, it can compile it and gave me
> the right answer.
> 
> what is the reason? it said that unsupported feature error: non locally
> static bounds are not supported!!
> 
> anyone could help me? I can send you the vhdl code and help me to check. I
> really need this help as my dateline for the presentation is just next
> month. For your information, I am designing a digital filter.

Article: 38497
Subject: Re: Altera Compiling Error..WHY?????
From: "Guy Schlacter" <g.schlact@attbi.com>
Date: Tue, 15 Jan 2002 23:36:25 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Daniel Yap" <daniu_yap@hotmail.com> wrote in message
news:3c445ce2$1_2@news.tm.net.my...

> my case is like this, i need to compile the wallace booth mul, the problem
> is, when i compile it as .vhd code, the compiler cannot run it, however,
> after i use the FPGA Express to synthesis it and export it as .edf format
> and do the compiling in Altera MaxPlus2 10, it can compile it and gave me
> the right answer.
> 
> what is the reason? it said that unsupported feature error: non locally
> static bounds are not supported!!
> 
> anyone could help me? I can send you the vhdl code and help me to check. I
> really need this help as my dateline for the presentation is just next
> month. For your information, I am designing a digital filter.


Daniel:
Some comments for you.  While Altera does provide you with both VHDL and
Verilog synthesis
capabilities, they are not as robust to various syntax and coding styles as the
primary synthesizers for fpga's:  Synplify, Leonardo and FE.

Some recommendations (since you indicated you are building a digital filter):
1.  Try out the Altera FIR Compiler as it can generate filters automatically
based on
user parameters.
2.  If you still want to hand-build your filter, definitely use the LPM_MULT
function
which will give you optimal results.  It enables you to parametarize it too.
Recommendation is to minimally use MAX_SPEED=7 with Signed Inputs for best
all-around results.
Do not forget to set your global synthesis style to FAST to enable the use of
the carry
chains.  
Best coding style for using the lpm_mult is to run the megawizard that creates
a fixed-port
wrapper of the paramterized multiplier.  Simply replace your current multiplier
with
the instantiation of this wrapper.


Your local Altera representative should be able to help you out with any tools
issues implementing
the above recommendations.
good luck.
Guy Schlacter
Altera Corporation


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 38498
Subject: Re: remainder
From: kayrock66@yahoo.com (Jay)
Date: 15 Jan 2002 17:09:03 -0800
Links: << >>  << T >>  << A >>
That is okay but it should be 'b1000000.  But anyway, why use binary,
do the bit positions have significance?  Synopsys Design Compiler will
bark about not allowing variables for modulus "Operands to mod must be
constant" but Synplicity and Exemplar's Leonardo Spectrum will do it
just fine as long as the mod number is 2^n.

You could also do:
a=b&63 or a=b[5:0] and it would synthesize on any of the tools.  And
by the way "a" will only have 6 meaningful bits so why you're
assigning to an 8 bit wire I'm not sure.

Regards

kossyma <fgt@iutg.trg> wrote in message news:<ee7438c.-1@WebX.sUN8CHnE>...
> when one is divided 64,how i do get the remainder?
> wire [7:0] a,b;
> assign a=b%6'b100000;
> Both a and b are variable.
> is it OK?
> or how shoult i implement?

Article: 38499
Subject: Re: SYN_HIER attribute in synplify v7.0
From: kayrock66@yahoo.com (Jay)
Date: 15 Jan 2002 17:15:10 -0800
Links: << >>  << T >>  << A >>
I've used that attribute the same way in 7.0 with success when I'm
trying to debug gate level sims and need to preserve port meaning. 
I've been please with Synplicity's customer support.  If its
reproducible, zip up your files and send it to them.  They made the
product, they get to fix it.  Thats my attitude anyways.

Regards

strut911@hotmail.com (strut911) wrote in message news:<4379d3e0.0201141956.34c19f9e@posting.google.com>...
> i am using synplify v7.0 right now and i am trying to assign
> syn_hier=hard to certain modules. this attribute is going inside the
> sdc file. anyways, i am getting the software to crash on me with some
> kind of mapper error. this only occurs when i am using syn_hier=hard
> in the sdc file.
> by the way, the other options i have checked are: 
> resource sharing, retiming, and pipelining.
> any help would be appreciated. thanks.
> strut911



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