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Messages from 38500

Article: 38500
Subject: Re: variable declare
From: kayrock66@yahoo.com (Jay)
Date: 15 Jan 2002 17:22:04 -0800
Links: << >>  << T >>  << A >>
Whoe there, why don't you start off with some simple stuff before you
jump right into division.  But to answer your question it could be all
3 depending on how you use it.

It's a wire if you're going to "assign" to it. And its a reg or
integer (the same as a 32 bit reg) if you say some thing like
myreg=myfunction(a,b) inside an always block.

Regards


grohss <fgt@iutg.trg> wrote in message news:<ee7432f.-1@WebX.sUN8CHnE>...
> i do a divider,(a/b),the result is c.should i declare the c is wire or reg or integer?

Article: 38501
(removed)


Article: 38502
Subject: Re: FPGA : VHDL netlist for simulation
From: "z.karim" <z.karim@attbi.com>
Date: Wed, 16 Jan 2002 06:41:05 GMT
Links: << >>  << T >>  << A >>
I believe the command is replace_fpga.  You can check fpga commands in
dc_shell with "help *fpga*".

Good luck
"Madhura Bokil" <Ext-Madhura.Bokil@Nokia.com> wrote in message
news:ee7438f.-1@WebX.sUN8CHnE...
> Hello,
> How to generate the VHDL netlist for the design implemented on FPGA?
> I tried synthesizing the design through the dc_shell and written the
netlist in VHDL. But the generic information for the LUT's in missing. If I
try to generate the xnf netlsit then that information is present in the form
of equations. The behaviour of the LUT's is also present in edif netlist. So
while writting the VHDL netlist does dc_shell requires some additional
thing?
> Regards,
> Madhura



Article: 38503
Subject: Re: remainder
From: "z.karim" <z.karim@attbi.com>
Date: Wed, 16 Jan 2002 06:46:49 GMT
Links: << >>  << T >>  << A >>
Take it easy Luigi, this board seems to be full of people learning
how to get things done.  You must be perfect if you are insulting
another for asking a question.

"luigi funes" <fuzzy8888@hotmail.com> wrote in message
news:UZX08.29722$aD.1084655@twister2.libero.it...
>
> kossyma ha scritto nel messaggio ...
> >when one is divided 64,how i do get the remainder?
> >wire [7:0] a,b;
> >assign a=b%6'b100000;
> >Both a and b are variable.
> >is it OK?
> >or how shoult i implement?
>
> Please, search with www.deja.com a thread
> named "Kindergarten Stuff" about one month ago.
> Regards
>
> Luigi
>
>



Article: 38504
Subject: Re: Synthesis in FPGA Express
From: "z.karim" <z.karim@attbi.com>
Date: Wed, 16 Jan 2002 06:54:43 GMT
Links: << >>  << T >>  << A >>
Merge duplicate registers:

If your code has any duplicated functions, be intentional or not, it will
merge
the registers storing duplicate states.  The register will likely have a
higher fanout.

Preserve hierarcy:

If you want your HDL modules to be preserved in structure, use this option.
For a
graphical output of this function, use the schematic viewer after creating a
chip
with and without the option.

Do not insert i/o:

This will prevent I/O cells from being attached to your top level
module/entity's ports.

Hope this helps, good luck.

"H.L" <alphaboran@yahoo.com> wrote in message
news:a1u924$2tr1$1@ulysses.noc.ntua.gr...
> Hello all,
>
> can anyone tell me about the optimization option "merge duplicate
register"
> in FPGA Express. Also I need some more information about the "preserve
> hierarcy" and "do not insert I/O pads" options, I checked Xilinx site but
> more help would be very  welcome.
>
> Best Regards
> Harris
>
>



Article: 38505
Subject: Re: Synthesis: Protel 99SE to XC2S200
From: "z.karim" <z.karim@attbi.com>
Date: Wed, 16 Jan 2002 07:03:44 GMT
Links: << >>  << T >>  << A >>
Contact either the Xilinx technical support people or contact the local
Xilinx FAE
for converting the old library components to the Virtex 2's.  Protel (if
they're still around) may have a utility to do this also.  Bottom line is
you need to create an EDIF file, Verilog, or VHDL code that describes your
circuit in order to use Xilinx ISE 4.1 or Xilinx Webpack (place and route
tools you will need).

Good luck.

"Steven Menk" <steven@metratek.net> wrote in message
news:ee7434e.-1@WebX.sUN8CHnE...
> I've taken over a project mid-stride for another engineer who has taken
ill, and I have a problem.  Basically I have a schematic capture produced in
Protel 99SE which represents the logic which needs to be implimented by a
Xilinx XC2S200 FPGA on the new board we are building.  In previous projects
I believe the schematics were saved from Protel as Xilinx XNF 5.0 files then
implimented using XACT Step 2.1.  XACT Step 2.1. however doesn't seem to
support the chip we are now using, as it does not show up in the "Set Part"
dialog.
>
> Could some one point me in the right direction of what I need to do to
impliment this design?
>
> Thanks in advance!



Article: 38506
Subject: A strange Xilinx 4.1 parser error
From: dottavio@ised.it (Antonio)
Date: 15 Jan 2002 23:26:19 -0800
Links: << >>  << T >>  << A >>
Good Morning,
can you explain me why I've this strange parser error from Xilinx 4.1
, it seems that in the following code there's an error on this line :
             "    OTHERS => coeff'(X"000")   ); "
but the same code is accepted by Synplify 7.02 and Aldec 5.1 , you
know what's the problem and how I can solve it ?? (... other than to
use Synplify naturally)


library	ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use work.SRRC_coeffs.all;

entity coeffs_selector is
		port( 
	 	  	  coeffs_SRRC	:	out coeffs
		 );
end coeffs_selector;


architecture coeffs_selector_arch of coeffs_selector is

    -- calcolati con campionamento in frequenza e scalati
	Constant coeffs_SRRCx3 : coeffs := coeffs'(			   
  
                          -- coefficienti del FIR 1

    coeff'(X"FE0")  , -- 1 
    coeff'(X"020")  , -- 1 inverted 
    coeff'(X"03D")  , -- 2 
    coeff'(X"FC3")  , -- 2 inverted 
    coeff'(X"F94")  , -- 3 
    coeff'(X"06C")  , -- 3 inverted 
    coeff'(X"59E")  , -- 4 
    coeff'(X"A62")  , -- 4 inverted 
    coeff'(X"F94")  , -- 5 
    coeff'(X"06C")  , -- 5 inverted 
    coeff'(X"03D")  , -- 6 
    coeff'(X"FC3")  , -- 6 inverted 
    coeff'(X"FE0")  , -- 7 
    coeff'(X"020")  , -- 7 inverted 
 
                          -- coefficienti del FIR 2

    coeff'(X"00A")  , -- 8 
    coeff'(X"FF6")  , -- 8 inverted 
    coeff'(X"FB0")  , -- 9 
    coeff'(X"050")  , -- 9 inverted 
    coeff'(X"1B1")  , -- 10 
    coeff'(X"E4F")  , -- 10 inverted 
    coeff'(X"461")  , -- 11 
    coeff'(X"B9F")  , -- 11 inverted 
    coeff'(X"F19")  , -- 12 
    coeff'(X"0E7")  , -- 12 inverted 
    coeff'(X"046")  , -- 13 
    coeff'(X"FBA")  , -- 13 inverted 
    coeff'(X"000")  , -- 14 
    coeff'(X"000")  , -- 14 inverted 
 
                          -- coefficienti del FIR 3

    coeff'(X"046")  , -- 15 
    coeff'(X"FBA")  , -- 15 inverted 
    coeff'(X"F19")  , -- 16 
    coeff'(X"0E7")  , -- 16 inverted 
    coeff'(X"461")  , -- 17 
    coeff'(X"B9F")  , -- 17 inverted 
    coeff'(X"1B1")  , -- 18 
    coeff'(X"E4F")  , -- 18 inverted 
    coeff'(X"FB0")  , -- 19 
    coeff'(X"050")  , -- 19 inverted 
    coeff'(X"00A")  , -- 20 
    coeff'(X"FF6")  , -- 20 inverted 
    coeff'(X"000")  , -- 21 
    coeff'(X"000")  , -- 21 inverted 
 
    OTHERS => coeff'(X"000")   );
					
begin	
			coeffs_SRRC <= coeffs_SRRCx3 ;
end coeffs_selector_arch;

Article: 38507
Subject: Xilinx 4.1 Implementation report questions
From: dottavio@ised.it (Antonio)
Date: 15 Jan 2002 23:34:03 -0800
Links: << >>  << T >>  << A >>
Good Morning,
Following there's the code of the implementation of my project using
clock enable structure, about this I don't know what to do regarding
the following points, can you help me in this ??

a) Anno:197 - NGDAnno found 12 physical component(s) for which 100
percent
   back-annotation is not possible. Simulation models for these
components will
   be constructed from the NCD. 

b)Ngd:333 - NOTE: This design contains the undriven net "GSR" which
you
   could drive during simulation to get valid results.
  Ngd:333 - NOTE: This design contains the undriven net "GTS" which
you
   could drive during simulation to get valid results.

c)NetListWriters:306 - Signal bus U1/to_add_a( 6 downto 0 ) on block
   Polyphase_x4 is not reconstructed, because there are some missing
bus
   signals.
  NetListWriters:306 - Signal bus U1/U1/to_add_g( 9 downto 5 ) on
block
   Polyphase_x4 is not reconstructed, because there are some missing
bus
   signals.



Loading device for application ngdanno from file 'v1000.nph' in
environment
C:/Xilinx.
Building NGA image...
Annotating NGA image...
Distributing delays...
Anno:197 - NGDAnno found 12 physical component(s) for which 100
percent
   back-annotation is not possible. Simulation models for these
components will
   be constructed from the NCD. Rerun NGDAnno with the -report option
for
   additional details, including any net and instance names which are
lost in
   this process.
Creating Guaranteed setup and hold checks...
Guaranteed Setup and Hold Checks were created for 1 input IOB(s).
Resolving logical and physical hierarchies...
Anno:178 - 2 hierarchical blocks were flattened during
back-annotation.
   Rerun NGDAnno with the -report option to see a list of these
blocks, as well
   as additional information about nets and instances that may not
have their
   original names.
Running NGD DRC...
Ngd:333 - NOTE: This design contains the undriven net "GSR" which you
   could drive during simulation to get valid results.
Ngd:333 - NOTE: This design contains the undriven net "GTS" which you
   could drive during simulation to get valid results.
Writing .nga file "Polyphase_x4.nga"...
   172 logical models annotated
   12 physical models annotated
Executing C:\Xilinx\bin\nt\ngd2vhdl.exe -w "Polyphase_x4.nga"
"C:\Tesi\Aggiunte_dal_6_1_2002\Aldec\SRRCx4_Implementations\SRRCx4_newCoeffs_ClkEnable_13_01_2002\implement\ver1\rev1\time_sim.vhd"
-xon true

C:\Tesi\Aggiunte_dal_6_1_2002\Aldec\SRRCx4_Implementations\SRRCx4_newCoeffs_ClkEnable_13_01_2002\implement\ver1\rev1>set
XILINX=C:\Xilinx

C:\Tesi\Aggiunte_dal_6_1_2002\Aldec\SRRCx4_Implementations\SRRCx4_newCoeffs_ClkEnable_13_01_2002\implement\ver1\rev1>set
PATH=C:\Xilinx\bin\nt
Release 4.1.03i - ngd2vhdl E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
ngd2vhdl: Reading design Polyphase_x4.nga ...
ngd2vhdl: Specializing design ...
ngd2vhdl:   Flattening design ...
ngd2vhdl:   Flattening design completed.
ngd2vhdl: Specializing design completed.

ngd2vhdl: Processing design ...
ngd2vhdl:   Preping physical only global signals ...
ngd2vhdl:   Preping design's networks ...
ngd2vhdl:   Preping design's macros ...
NetListWriters:306 - Signal bus U1/to_add_a( 6 downto 0 ) on block
   Polyphase_x4 is not reconstructed, because there are some missing
bus
   signals.
NetListWriters:306 - Signal bus U1/U1/to_add_g( 9 downto 5 ) on block
   Polyphase_x4 is not reconstructed, because there are some missing
bus
   signals.
ngd2vhdl: Preping design completed.


Thanks

                Antonio

Article: 38508
Subject: Xilinx Timing report question
From: dottavio@ised.it (Antonio)
Date: 15 Jan 2002 23:38:56 -0800
Links: << >>  << T >>  << A >>
In a project using Gated Clock implemented with Synplify I've the
following Xilinx Timing Report, but I control in Synplify, there's a
BUFG on clk_div_n line, so my question is what else it needs ??

WARNING:Timing - Clock nets using non-dedicated resources were found
in this
   design. Clock skew on these resources will not be automatically
addressed
   during path analysis. To create a timing report that analyzes clock
skew for
   these paths, run trce with the '-skew' option.

   The following clock nets use non-dedicated resources:
      clk_div_n  

                    


                        Antonio

Article: 38509
Subject: Re: Leonardo + Xilinx tools help
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Wed, 16 Jan 2002 09:50:46 +0100
Links: << >>  << T >>  << A >>
Rodolfo Jardim de Azevedo a écrit :
> 
[...]
>   I have 2 memory banks tied to different pins, each one is 512
> x 16. I want to drive them using the same address to make a 512
> x 32. ngdbuild complains about ram_address1 but not about
> ram_address0. They are assigned in VHDL as
>         ram_address0 <= address;
>         ram_address1 <= address;
> so they should have the same values, they are of the same type
> and everything equal.
> 
>   I got similar problem in some control signals which should be
> duplicated.
> 
>   Can anyone help me?

Hi
I know this problem. Leonardo gives only one name to these signals (in your case
it will be ram_address0) so that in the EDIF you won't find any address1. You
likely won't find "address" either.
What's strabge is that they're pins in your design, not internal signals...

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 38510
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Wed, 16 Jan 2002 08:58:06 +0000
Links: << >>  << T >>  << A >>
In article <3C448BFE.F708ABEA@xilinx.com>, Peter Alfke
<peter.alfke@xilinx.com> writes
>I have a simple, quick-and-dirty method of transferring data between unrelated
>clock domains:
>Transfer twice in a row, and then compare the two values. If they are identical,
>the data is good. If they differ, discard the data.

...and read it a third time, checking that the third copy 
agrees with the second if you are paranoid.

>This requires that the source is inherently stable for multiple transfers, but
>that can always be arranged  with an extra synchronous register
>This method can even be implemented in software, and has, for decades, e.g. when
>reading count values from the Am9517..

A nice example of the way we build "Chinese walls" in our heads:
I've used this countless times for reading multi-byte counters reliably
in software, but it never occurred to me to use it in hardware!

However, I fear it has a significant limitation:  If the
destination domain clock is very much faster than the source,
is it not possible that two identical erroneous values
might be read?

In other situations (destination clock is similar frequency
or slower than source) you still need some kind of handshake 
from destination to source, to give the source permission to 
change its data.

So I'm afraid I will stick with tried and trusted handshaking
techniques.  While we're on the subject, I hope everyone
knows about the rather cute toggling handshake scheme
described by Weinstein, who endearingly named it the "Flancter":

  www.memecdesign.com/resources/guides/Flancter_App_Note.pdf
  www.xilinx.com/xcell/xl37/xcell37_54.pdf
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 38511
Subject: Re: Synthesis in FPGA Express
From: "H.L" <alphaboran@yahoo.com>
Date: Wed, 16 Jan 2002 11:04:53 +0200
Links: << >>  << T >>  << A >>
Hello z.rakim.
Thanks a lot.
In my design I have some paths with big path delay. In these paths there are
some registers with high fanout so I will check them again, this time with
the merge duplicate registers disabled.

Harris


"z.karim" <z.karim@attbi.com> wrote in message
news:Ts918.35817$JF.377746@rwcrnsc52.ops.asp.att.net...
> Merge duplicate registers:
>
> If your code has any duplicated functions, be intentional or not, it will
> merge
> the registers storing duplicate states.  The register will likely have a
> higher fanout.
>
> Preserve hierarcy:
>
> If you want your HDL modules to be preserved in structure, use this
option.
> For a
> graphical output of this function, use the schematic viewer after creating
a
> chip
> with and without the option.
>
> Do not insert i/o:
>
> This will prevent I/O cells from being attached to your top level
> module/entity's ports.
>
> Hope this helps, good luck.
>
> "H.L" <alphaboran@yahoo.com> wrote in message
> news:a1u924$2tr1$1@ulysses.noc.ntua.gr...
> > Hello all,
> >
> > can anyone tell me about the optimization option "merge duplicate
> register"
> > in FPGA Express. Also I need some more information about the "preserve
> > hierarcy" and "do not insert I/O pads" options, I checked Xilinx site
but
> > more help would be very  welcome.
> >
> > Best Regards
> > Harris
> >
> >
>
>



Article: 38512
Subject: info about NIOS softcore processor
From: christian.lehmann@de.bosch.com (Christian Lehmann)
Date: 16 Jan 2002 01:23:33 -0800
Links: << >>  << T >>  << A >>
Hi everyone,

I'm using a NIOS development board with an APEX EP20K200 FPGA and 
need more and deeper information about it. I already scanned 
through the Altera homepage, but didn't find the info I was looking 
for.

What I'm looking for is detailed information about the shipped 
demo-programs (in C and Assembler) or any other demo-programs 
that help me understand the functionality of the NIOS processor.

Also useful would be a detailed description of the NIOS Core 
design and how to program it with GNU-as (Assembler).

(At the moment, I'm working with NIOS Core 1.0, using the bash with 
nios-build and nios-run)

Thanks a lot,

chris

Article: 38513
Subject: Re: info about NIOS softcore processor
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Wed, 16 Jan 2002 12:06:46 +0100
Links: << >>  << T >>  << A >>
Hi,

meanwhile the current NIOS verison is 1.1 with version 2.0 just around the
corner. All NIOS customer should have received the 1.1 update automatically
and free of charge. You can register your NIOS kit at:
http://www.altera.com/cgi-bin/ex_nios.pl

NIOS version 1.1 includes additional documentation that should answer most
of your questions. Especially there are the following documents that were
not part of the 1.0 version:
Nios_Programmers_Reference.pdf
Nios_Software_Development_Reference.pdf

Let me know if you don't have these documents and I'll mail them to you
directly.

Best regards
Wolfgang

"Christian Lehmann" <christian.lehmann@de.bosch.com> schrieb im Newsbeitrag
news:c5f8af23.0201160123.5e4b85fe@posting.google.com...
> Hi everyone,
>
> I'm using a NIOS development board with an APEX EP20K200 FPGA and
> need more and deeper information about it. I already scanned
> through the Altera homepage, but didn't find the info I was looking
> for.
>
> What I'm looking for is detailed information about the shipped
> demo-programs (in C and Assembler) or any other demo-programs
> that help me understand the functionality of the NIOS processor.
>
> Also useful would be a detailed description of the NIOS Core
> design and how to program it with GNU-as (Assembler).
>
> (At the moment, I'm working with NIOS Core 1.0, using the bash with
> nios-build and nios-run)
>
> Thanks a lot,
>
> chris



Article: 38514
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 16 Jan 2002 11:58:11 GMT
Links: << >>  << T >>  << A >>
On Wed, 16 Jan 2002 08:58:06 +0000, Jonathan Bromley
<Jonathan.Bromley@doulos.com> wrote:

>In article <3C448BFE.F708ABEA@xilinx.com>, Peter Alfke
><peter.alfke@xilinx.com> writes
>>I have a simple, quick-and-dirty method of transferring data between unrelated
>>clock domains:
>>Transfer twice in a row, and then compare the two values. If they are identical,
>>the data is good. If they differ, discard the data.
>
>...and read it a third time, checking that the third copy 
>agrees with the second if you are paranoid.
>
>>This requires that the source is inherently stable for multiple transfers, but
>>that can always be arranged  with an extra synchronous register
>>This method can even be implemented in software, and has, for decades, e.g. when
>>reading count values from the Am9517..
>
>A nice example of the way we build "Chinese walls" in our heads:
>I've used this countless times for reading multi-byte counters reliably
>in software, but it never occurred to me to use it in hardware!
>
>However, I fear it has a significant limitation:  If the
>destination domain clock is very much faster than the source,
>is it not possible that two identical erroneous values
>might be read?
>
>In other situations (destination clock is similar frequency
>or slower than source) you still need some kind of handshake 
>from destination to source, to give the source permission to 
>change its data.
>
>So I'm afraid I will stick with tried and trusted handshaking
>techniques.  While we're on the subject, I hope everyone
>knows about the rather cute toggling handshake scheme
>described by Weinstein, who endearingly named it the "Flancter":
>
>  www.memecdesign.com/resources/guides/Flancter_App_Note.pdf
>  www.xilinx.com/xcell/xl37/xcell37_54.pdf

I believe this circuit only works for a single signal.
If you have a vector, and you need to make sure that all elements of
that vector can cross the clock domain boundary within a certain time,
then you still need some way of expressing the timing constaint in the
UCF (or whatever).

No circuit trick can avoid the need for appropriate timing constraints
in this case.

Regards,
Allan.

>Jonathan Bromley
>DOULOS Ltd.
>Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
>Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
>Fax: +44 1425 471573                             Web: http://www.doulos.com
>
>                   **********************************
>                   **  Developing design know-how  **
>                   **********************************
>
>This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
>all rights of privilege in  respect thereof. It is intended for the  use of
>the addressee only. If you are not the intended  recipient please delete it
>from  your  system, any  use, disclosure, or copying  of this  document  is
>unauthorised. The contents of this message may contain personal views which
>are not the views of Doulos Ltd., unless specifically stated.
>
>
>


Article: 38515
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Wed, 16 Jan 2002 12:06:08 +0000
Links: << >>  << T >>  << A >>
In article <3c45693a.205540711@netnews.agilent.com>, Allan Herriman
<allan_herriman.hates.spam@agilent.com> writes
>On Wed, 16 Jan 2002 08:58:06 +0000, Jonathan Bromley
><Jonathan.Bromley@doulos.com> wrote:

["flancter" circuit]
>>  www.memecdesign.com/resources/guides/Flancter_App_Note.pdf
>>  www.xilinx.com/xcell/xl37/xcell37_54.pdf
>
>I believe this circuit only works for a single signal.
>If you have a vector, and you need to make sure that all elements of
>that vector can cross the clock domain boundary within a certain time,
>then you still need some way of expressing the timing constaint in the
>UCF (or whatever).
>
>No circuit trick can avoid the need for appropriate timing constraints
>in this case.

No dispute.  But for situations where your clock domains have
entirely incoherent clocks, it makes a neat handshake circuit for
passing "ready/accepted" to and fro.  Even then, you still need
constraints within each clock domain to get things right.

Sorry, I had let myself digress away from the original topic
which (I think!) was about clock domains with closely related,
but skewed, clocks.
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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Article: 38516
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: hamish@cloud.net.au
Date: 16 Jan 2002 12:28:42 GMT
Links: << >>  << T >>  << A >>
Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote:
> Ah, more to it. Do you have VHDL to show?

I've have to cook up an example like the diagram I drew -
I can't post the existing code (confidentiality etc).

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38517
Subject: Re: Repost: Should clock skew be included for setup time analysis?
From: hamish@cloud.net.au
Date: 16 Jan 2002 12:33:09 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <peter.alfke@xilinx.com> wrote:
> I have a simple, quick-and-dirty method of transferring data between unrelated
> clock domains:
> Transfer twice in a row, and then compare the two values. If they are identical,
> the data is good. If they differ, discard the data.

A robust solution but it has quite a bit of overhead (duplicate signal,
comparison logic etc). Especially since I can guarantee that my
circuit works as long as I don't violate any setup times -- for
which I need the timing constraints.


cheers,
Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38518
Subject: Re: Leonardo + Xilinx tools help
From: Rodolfo Jardim de Azevedo <rjazevedo@NOSPAM.ic.unicamp.br>
Date: Wed, 16 Jan 2002 10:35:54 -0200
Links: << >>  << T >>  << A >>
Do you know how to solve this?

	Thanks,

		Rodolfo

Nicolas Matringe wrote:
> 
> Rodolfo Jardim de Azevedo a écrit :
> >
> [...]
> >   I have 2 memory banks tied to different pins, each one is 512
> > x 16. I want to drive them using the same address to make a 512
> > x 32. ngdbuild complains about ram_address1 but not about
> > ram_address0. They are assigned in VHDL as
> >         ram_address0 <= address;
> >         ram_address1 <= address;
> > so they should have the same values, they are of the same type
> > and everything equal.
> >
> >   I got similar problem in some control signals which should be
> > duplicated.
> >
> >   Can anyone help me?
> 
> Hi
> I know this problem. Leonardo gives only one name to these signals (in your case
> it will be ram_address0) so that in the EDIF you won't find any address1. You
> likely won't find "address" either.
> What's strabge is that they're pins in your design, not internal signals...

-- 
The Xingo Project                         | Rodolfo Jardim de Azevedo
Code Optimization for Embedded Systems    | Computer Science PhD Student
An Open Software Initiative of IC-UNICAMP | rjazevedo@ic.unicamp.br

Article: 38519
Subject: Re: Synthesis: Protel 99SE to XC2S200
From: hamish@cloud.net.au
Date: 16 Jan 2002 12:37:25 GMT
Links: << >>  << T >>  << A >>
z.karim <z.karim@attbi.com> wrote:
> they're still around) may have a utility to do this also.  Bottom line is
> you need to create an EDIF file, Verilog, or VHDL code that describes your
> circuit in order to use Xilinx ISE 4.1 or Xilinx Webpack (place and route
> tools you will need).

NGDBUILD appears to read XNF files still (ie XNF2NGD still exists
in 4.1 SP3).


hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 38520
Subject: Re: Leonardo + Xilinx tools help
From: Rodolfo Jardim de Azevedo <rjazevedo@NOSPAM.ic.unicamp.br>
Date: Wed, 16 Jan 2002 13:23:12 -0200
Links: << >>  << T >>  << A >>
Hi,

	I used the following script (caught from leonardo Save Command File) to
do the place and route inside the Leonardo develpoment environment:

set part v800hq240
set process 4
set wire_table xcv800-4_avg
set chip TRUE
set macro FALSE
load_library xcv
sc files.tcl
elaborate xsv800 -architecture xsv800_arch 
set output_file /home/lsc/rodolfo/leon1/leon1_noopt.edf
auto_write /home/lsc/rodolfo/leon1/leon1_noopt.edf
place_and_route /home/lsc/rodolfo/leon1/leon1_noopt.edf -target xcv
-part v800hq240 -speed_grade 4  -exe_path /home/lsc/Xilinx/bin/sol
-m1_pr_high -ba_format VHDL -m1_no_bits
pre_optimize .work.xsv800.xsv800_arch -common_logic -unused_logic
-boundary -xor_comparator_optimize 
pre_optimize .work.xsv800.xsv800_arch -extract 
set output_file /home/lsc/rodolfo/leon1/leon1_preopt.edf
auto_write /home/lsc/rodolfo/leon1/leon1_preopt.edf
place_and_route /home/lsc/rodolfo/leon1/leon1_preopt.edf -target xcv
-part v800hq240 -speed_grade 4  -exe_path /home/lsc/Xilinx/bin/sol
-m1_pr_standard -ba_format VHDL

	As you could see, I tried to build two output edif files: one without
optimization and another with pre-optimization. In the first one, I got
lots of that message:
	  ERROR:NgdBuild:432 - logical block 'tri_data(4)' with type 'TRI' is
unexpanded.

and in the pre-optimized version, I got the message:
ERROR:NgdBuild:201 - An EDIF value has exceeded the maximum string limit
of 500
   characters, or a closing double-quote was never found for this
string, which
   starts on line 2190 in file "leon1_preopt.edf".  This likely means
that the
   EDIF netlist was improperly written.  Please contact the vendor of
the
   program that produced this EDIF.

which ocurred in a line that defines the internal rom. This line has
more than 500 characters. Is it possible to bypass this limit?

	Since the place and route command is lauched automatically by Leonardo,
I didn't tried anything to tell Xilinx it is "Exemplar" .edf. What do
you mean by doing so? Is there a specific option?
	The first edif lines are:
(edif xsv800 
 (edifVersion 2 0 0)
 (edifLevel 0)
 (keywordMap (keywordLevel 0))
 (status 
  (written 
   (timestamp 2002 01 16 12 58 10)
   (program "LeonardoSpectrum Level 3" (version "v2001_1d.46"))
   (author "Exemplar Logic Inc")))
...

	Thanks in advance,

		Rodolfo

Mike Treseler wrote:
> 
> Rodolfo Jardim de Azevedo wrote:
> > I tried
> > without constraints. And then I got another error which I don't
> > understand. Lots of lines like this
> > ERROR:NgdBuild:432 - logical block 'tri_data(4)' with type 'TRI' is
> > unexpanded
> 
> Have you made a setting to tell the Xilinx place and route
> that the .edf file is of type "Exemplar" ?
> 
>    --Mike Treseler

-- 
The Xingo Project                         | Rodolfo Jardim de Azevedo
Code Optimization for Embedded Systems    | Computer Science PhD Student
An Open Software Initiative of IC-UNICAMP | rjazevedo@ic.unicamp.br

Article: 38521
Subject: Re: Leonardo + Xilinx tools help
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Wed, 16 Jan 2002 16:30:44 +0100
Links: << >>  << T >>  << A >>
Rodolfo Jardim de Azevedo a écrit :
> 
> Do you know how to solve this?

Since the problem happens with external signals, I'm not sure.
You might try to put some preserve attributes on your signals.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 38522
Subject: Audio time delay circuit
From: Simon.Fisher@hitachi-eu.com (Simon Fisher)
Date: 16 Jan 2002 09:40:36 -0800
Links: << >>  << T >>  << A >>
Hi, I'm new to all this, so please bear with me.

I need to implement a variable time delay for digital audio signals of
several hundred milliseconds. The data comes in and out of an I2S
interface using 32khz sample rate, stereo 16 bit samples. The device
also needs to be controlled (ie precise time delay selected) via an
I2C slave interface.

Any ideas please? 

Cheers
Simon Fisher

Article: 38523
Subject: Re: Synthesis in FPGA Express
From: kayrock66@yahoo.com (Jay)
Date: 16 Jan 2002 10:18:52 -0800
Links: << >>  << T >>  << A >>
Read below...
"H.L" <alphaboran@yahoo.com> wrote in message news:<a1u924$2tr1$1@ulysses.noc.ntua.gr>...
> Hello all,
> 
> can anyone tell me about the optimization option "merge duplicate register"

If the synthizer sees that the combinational logic feeding a F/F is
the same for 2 F/F's, it discards one of them, and drives both F/F's
outputs from a single flop.  Small potatoes in savings but can screw
you up if you really wanted that flop there.

> in FPGA Express. Also I need some more information about the "preserve
> hierarcy" 

You do that if you want to do gate level debug and want the modules
and port definitions to look like something you recognize.  Also
allows hybrid RTL/gate sims for isolating synth problems, or sim
speedup.

and "do not insert I/O pads" options, 

You do this if you're going to instatiate the sythesized netlist as
part of a larger design- you can't stick I/O drivers in the middle of
your chip right?

I checked Xilinx site but
> more help would be very  welcome.
> 
> Best Regards
> Harris

Article: 38524
Subject: Re: Leonardo + Xilinx tools help
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Wed, 16 Jan 2002 10:29:54 -0800
Links: << >>  << T >>  << A >>
Rodolfo Jardim de Azevedo wrote:
> 
> Hi,
> 
>         I used the following script (caught from leonardo Save Command File) to
> do the place and route inside the Leonardo develpoment environment:

I would suggest you run the tools separately and manually until
you work out the EDIF file problem.

> - An EDIF value has exceeded the maximum string limit of 500
>    characters, or a closing double-quote was never found for this string, which
>    starts on line 2190 in file "leon1_preopt.edf".  This likely means that the
>    EDIF netlist was improperly written.

Xilinx edif settings are wrong.
Check the Xilinx GUI for EDIF writer settings.
There should be options for different EDIF versions and 
for different synthesizers.
 
> Since the place and route command is lauched automatically by Leonardo,
> I didn't tried anything to tell Xilinx it is "Exemplar" .edf. 

I would skip the automation until you know what's going on.

> What do
> you mean by doing so? Is there a specific option?

You've go the program and the manuals. I don't.


     --Mike Treseler



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