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Messages from 38600

Article: 38600
Subject: Re: Audio time delay circuit
From: acher@in.tum.de (Georg Acher)
Date: 18 Jan 2002 20:23:44 GMT
Links: << >>  << T >>  << A >>
In article <3C486EF6.69A05003@andraka.com>,
 Ray Andraka <ray@andraka.com> writes:

|> > There was a time before Nixie tubes?
|> 
|> Yes, I had a frequency counter years ago that had bars with numbered windows.
|> Behind each was a neon bulb which would light up the correct digit.  An
|> additional neon bulb lit up behind the range (Hz, kHz), and there was one
|> between each column to act as a decimal point.  The display for a 59.703 Hz
|> input would look something like this:

These funny tubes were decatrons, a huge neon bulb with 10 electrodes and a
sophisticated "shift"-mechanism for the discharge.

A nice description can be found here:

http://mypage.bluewin.ch/sagnell/id14.htm

-- 
         Georg Acher, acher@in.tum.de         
         http://www.in.tum.de/~acher/
          "Oh no, not again !" The bowl of petunias          

Article: 38601
Subject: VirtexII ES configuration
From: "rs" <remi-seglie@infonie.fr>
Date: Fri, 18 Jan 2002 21:38:21 +0100
Links: << >>  << T >>  << A >>
Does anybody succeed in configuring an Virtex II ES with slave select map
mode ?
It's working with JTAG but not with this mode and INIT never go low.
I apply the modifications concerning the ES Errata sheet (timing of RW and
CS with CCLK).
Does anybody has an idea ?




Article: 38602
Subject: Re: service pack8 can't use
From: "rs" <remi-seglie@infonie.fr>
Date: Fri, 18 Jan 2002 21:41:52 +0100
Links: << >>  << T >>  << A >>
For me, you can't use Fundation 3.3 with Windows Me (only Windows 98 or
others : read the installation guide). the 4i works with Windows Me but I
have not test it, Windows NT2000 is better

"dotty1319" <dotty1319@hotmail.com> wrote in message
news:ac44422f.0201172155.36117cb0@posting.google.com...
> i use xilinx foundation 3.1i
> when i download service pack8
> 3_3_08i_pc.exe
> Aldec_2001_3.exe
> FPGAExp35.exe
> i'm use OS windows Me
> it's can't implement
> it's show this error
> FATAL_ERROR:StaticFileParsers:Xml_Node.c:358:1.12.8.2 - Corrupt or
> > missing Xml



Article: 38603
Subject: Re: Audio time delay circuit
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sat, 19 Jan 2002 10:10:26 +1300
Links: << >>  << T >>  << A >>
Georg Acher wrote:
> 
> In article <3C486EF6.69A05003@andraka.com>,
>  Ray Andraka <ray@andraka.com> writes:
> 
> |> > There was a time before Nixie tubes?
> |>
> |> Yes, I had a frequency counter years ago that had bars with numbered windows.
> |> Behind each was a neon bulb which would light up the correct digit.  An
> |> additional neon bulb lit up behind the range (Hz, kHz), and there was one
> |> between each column to act as a decimal point.  The display for a 59.703 Hz
> |> input would look something like this:
> 
> These funny tubes were decatrons, a huge neon bulb with 10 electrodes and a
> sophisticated "shift"-mechanism for the discharge.
> 
> A nice description can be found here:
> 
> http://mypage.bluewin.ch/sagnell/id14.htm

 Impressive - these things could count and display at the same time,
with _one_ element :-)

 Be a good student exercise, get them to make a similar thing in todays 
devices. Some license would have to be given on the charge-push detail
that ensured it 'hopped' in only one direction.
 
 Ray - To display 59.703Hz did this use a 1000 second gate, ( 16.6
minutes )
or did they have reciprocal freqency counting solved :-)

-jg

Article: 38604
Subject: Re: VirtexII ES configuration
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Fri, 18 Jan 2002 13:30:48 -0800
Links: << >>  << T >>  << A >>
RS,

Since all devices are tested on the tester in select map slave mode (fastest
and easiest mode to use on the tester), I am surprised.

Since it works with JTAG, the part is good.......

Have you read all of the technical answers on the web concerning Virtex II
configuration?  There were some bug fixes in the service packs, and you may
need one of these (for example, daisy chanining devices had a bug fix).

What part are you playing with?

Austin

rs wrote:

> Does anybody succeed in configuring an Virtex II ES with slave select map
> mode ?
> It's working with JTAG but not with this mode and INIT never go low.
> I apply the modifications concerning the ES Errata sheet (timing of RW and
> CS with CCLK).
> Does anybody has an idea ?


Article: 38605
Subject: Re: VirtexII ES configuration
From: "Randy Bolling" <rbolling@tampabay.rr.com>
Date: Fri, 18 Jan 2002 21:58:23 GMT
Links: << >>  << T >>  << A >>
Sad to say, I've had this problem before...

Slave select map mode is a different bitstream, slightly, but different
startup clock.  You might need to review the bitstream generation in bitgen
to see you have turned JTAG bitstream off and this on.  Reason?  Startup
clock, something must bring the part from download into startup after the
last bit is loaded.

Randy Bolling
rbolling@tampabay.rr.com

"rs" <remi-seglie@infonie.fr> wrote in message
news:1011386254.164134@remus.infonie.fr...
> Does anybody succeed in configuring an Virtex II ES with slave select map
> mode ?
> It's working with JTAG but not with this mode and INIT never go low.
> I apply the modifications concerning the ES Errata sheet (timing of RW and
> CS with CCLK).
> Does anybody has an idea ?
>
>
>
>



Article: 38606
Subject: Re: I2C multiplexer
From: "Randy Bolling" <rbolling@tampabay.rr.com>
Date: Fri, 18 Jan 2002 22:00:43 GMT
Links: << >>  << T >>  << A >>
Andy,

I2C is a multi-drop bus, why multiplex a multi-drop bus?

Randy Bolling

"Andrew Ha" <akha@cisco.com> wrote in message
news:3C45D59A.F7C0B6CE@cisco.com...
> Is there verilog code available in public domain that will multiplex an
> I2C bus among multiple I2C busses?
>
> Thanks,
>
> Andy
>
>
>
>



Article: 38607
Subject: Simple shift register not working
From: goodsell@bridgernet.com (Kevin Goodsell)
Date: 18 Jan 2002 14:14:31 -0800
Links: << >>  << T >>  << A >>
Hi. I know very little about FPGAs or using HDLs, so please bare with
me. I'm trying to get the following module (in Verilog) to work with a
Spartan 2 FPGA using the Xilinx Webpack software:

module shift_reg(in, clk, out);
input in, clk;
output [0:8] out;

reg [0:8] data;

assign out = data;

always @(posedge clk)
begin
	data <= #1 {data[1:8], in};
/*	data[0] <= #1 data[1];
	data[1] <= #1 data[2];
	data[2] <= #1 data[3];
	data[3] <= #1 data[4];
	data[4] <= #1 data[5];
	data[5] <= #1 data[6];
	data[6] <= #1 data[7];
	data[7] <= #1 data[8];
	data[8] <= #1 in; */
end
endmodule

The part that is commented out is another thing that I've tried. I've
also tried many variations on the assignments (blocking, non-blocking,
with/without delays inside and outside the assignments, and so on). I
am nearly convinced that the problem is not the code, but has
something to do with the way the software is handling the clk signal.

First, let me explain what I'm seeing when I test it. It seems that on
the rising edge of clk, the "in" signal is read into every bit of
data, rather than only data[8]. Occasionally, the lower bits seem to
fail to register a change, though.

In my user constraints file, if I try to assign clk to a normal I/O
pin, I get the following error:

ERROR:MapLib:93 - Illegal LOC on symbol "clk" (pad signal=clk) or
BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should
only be LOCed to GCLKIOB site.

I don't know what this means, or whether it has anything to do with
the module not working. For the record, here's my .ucf file:

#NET "clk" LOC = "P112"; # this line causes the error
NET "in" LOC = "P110";
NET "out<0>" LOC = "P3";
NET "out<1>" LOC = "P5";
NET "out<2>" LOC = "P7";
NET "out<3>" LOC = "P9";
NET "out<4>" LOC = "P14";
NET "out<5>" LOC = "P16";
NET "out<6>" LOC = "P18";
NET "out<7>" LOC = "P21";
NET "out<8>" LOC = "P23";

Thanks ahead of time for any help.

-Kevin

Article: 38608
Subject: Shift Register question
From: Joe <ja.gallegos@boeing.com>
Date: Fri, 18 Jan 2002 23:06:43 GMT
Links: << >>  << T >>  << A >>
I have a simple 77 bit parallel to serial shift register w/ an
asynchronous reset_n and a synchronous load:
---------------
p2s: process(CLK, RESET_N)
begin

if RESET_N = '0' then
 SHIFT_REG <= (others => '0');
elsif (CLK'event and CLK = '1') then
   if LOAD = '1' then
   SHIFT_REG <= SHIFT_REG_IN;
   elsif SHIFT_EN = '1' then
    SHIFT_REG(76 downto 1) <= SHIFT_REG(75 downto 0);
    SHIFT_REG(0) <= '0';
   end if;
end if;
end process;

SOUT <= SHIFT_REG(76);

-----------------

The p2s register works fine; however, I will only be receiving across
the interface 77 clocks! So how do I load the register initially? Is it
permissable simply to gate in an extra clock(from the on board free
running clock) for loading purposes?

Such as :

CLK <= CLK_77 or (CLK_1MHZ and ONE_PERIOD);

Where ONE_PERIOD is high asserting pulse at the appropriate LOAD time.

The reason I ask is this -- I do not like to put anything in front of
the clock of a long shift register in order to limit any problems with
clock skew between registers. The incoming 77 clocks(named CLK_77) are
1MHz clock periods.

Thanks in advance....


Article: 38609
Subject: microcontroller manager question
From: bburnett01@hotmail.com (Burnett)
Date: 18 Jan 2002 15:57:42 -0800
Links: << >>  << T >>  << A >>
I'm working on a hobby project involving a Cirrus EP7312
microprocessor.  The design is also gointo contain an fpga with plenty
of extra gates.  My problem is that on powerup the microprocessor will
enter standby mode until a few signals are triggered (following
ceratin timings) to enter normal execution and executing
instrucations.

I'm new to programmable logic and I'm wondering if managing these
signals and their timings might be a good use for some of the extra
gates in my fpga.  I'm envisioning a state machine that would wait a
few usec in a state and then transition to another state, each state
changing the logic levels on pins that are attached to the
microprocessor.  Is this posible with an fpga?  From my meager
understanding it sounds like this problem is better suited for a cpld,
but I don't have one of those on my design board...

Article: 38610
Subject: Re: Simple shift register not working
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Fri, 18 Jan 2002 17:08:27 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------E4158C9E3C2FEEF68D31E452
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit


Some comments below about the code and error message.

Kevin Goodsell wrote:

> Hi. I know very little about FPGAs or using HDLs, so please bare with
> me. I'm trying to get the following module (in Verilog) to work with a
> Spartan 2 FPGA using the Xilinx Webpack software:
>
> module shift_reg(in, clk, out);
> input in, clk;
> output [0:8] out;

"in" and "out" are key words in VHDL.  As a general rule of thumb, do not
use VHDL key words in Verilog.  Although this is most likely not the cause
of your problems, it could save you grief later.

I also suggest if you have the flexibility to generally use little-endian
notation, [8:0] not [0:8].  For most cases, it works fine either way but
there are some legacy issues with using this notation and because of that,
when I have the choice, I use little endian.  Sometimes processors or
other IP lock you into one notation and in that case, I would not swim
upstream.


> reg [0:8] data;
>
> assign out = data;
>
> always @(posedge clk)
> begin
>         data <= #1 {data[1:8], in};

In general, do not put delays in synthesizable code.  Synthesizers ignore
the delays and could lead to mis-match between synthesis and simulation.




>
> /*      data[0] <= #1 data[1];
>         data[1] <= #1 data[2];
>         data[2] <= #1 data[3];
>         data[3] <= #1 data[4];
>         data[4] <= #1 data[5];
>         data[5] <= #1 data[6];
>         data[6] <= #1 data[7];
>         data[7] <= #1 data[8];
>         data[8] <= #1 in; */
> end
> endmodule
>
> The part that is commented out is another thing that I've tried. I've
> also tried many variations on the assignments (blocking, non-blocking,
> with/without delays inside and outside the assignments, and so on). I
> am nearly convinced that the problem is not the code, but has
> something to do with the way the software is handling the clk signal.

As a general rule, I usually use blocking for combinatorial functions and
non-blocking for registered signals.  To be honest, if you don't specify
delays, it usually does not make a big difference which you use.



> First, let me explain what I'm seeing when I test it. It seems that on
> the rising edge of clk, the "in" signal is read into every bit of
> data, rather than only data[8]. Occasionally, the lower bits seem to
> fail to register a change, though.

Not sure about that.  Code looks OK to me.  Where do you see this behavior
(simulator or on the board)?  Did you perform any timing analysis or
timing simulation?



> In my user constraints file, if I try to assign clk to a normal I/O
> pin, I get the following error:
>
> ERROR:MapLib:93 - Illegal LOC on symbol "clk" (pad signal=clk) or
> BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP), IPAD-IBUFG should
> only be LOCed to GCLKIOB site.

The synthesis tool will defaultly put you on an IBUFG which locks you to
certain I/O clock pins.  This is the best thing to do if you have this
flexibility.  If your board is made and you no longer have the flexibility
to use the dedicated clock pins, I suggest you instantiatite a BUFG
between your clock port and clock signal in your code.  This will result
in a slightly longer clock delay than you would have if you use the
dedicated pin however still get you on the global clock network and thus
minimze clock skew, which is one of your greatest eminmies in synchronous
design.

--  Brian


> I don't know what this means, or whether it has anything to do with
> the module not working. For the record, here's my .ucf file:
>
> #NET "clk" LOC = "P112"; # this line causes the error

> NET "in" LOC = "P110";

> NET "out<0>" LOC = "P3";
> NET "out<1>" LOC = "P5";
> NET "out<2>" LOC = "P7";
> NET "out<3>" LOC = "P9";
> NET "out<4>" LOC = "P14";
> NET "out<5>" LOC = "P16";
> NET "out<6>" LOC = "P18";
> NET "out<7>" LOC = "P21";
> NET "out<8>" LOC = "P23";
>
> Thanks ahead of time for any help.
>
> -Kevin



Article: 38611
Subject: Re: Shift Register question
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Sat, 19 Jan 2002 00:37:05 GMT
Links: << >>  << T >>  << A >>
It seems like 77 clocks are enough.  On cycle 0, you enable LOAD so after
that cycle SOUT is SHIFT_REG_IN(76).  On the next 76 cycles, the other 76
bits are shifted into SOUT.

"Joe" <ja.gallegos@boeing.com> wrote in message
news:3C48AA83.35FDF91@boeing.com...
> I have a simple 77 bit parallel to serial shift register w/ an
> asynchronous reset_n and a synchronous load:
> ---------------
> p2s: process(CLK, RESET_N)
> begin
>
> if RESET_N = '0' then
>  SHIFT_REG <= (others => '0');
> elsif (CLK'event and CLK = '1') then
>    if LOAD = '1' then
>    SHIFT_REG <= SHIFT_REG_IN;
>    elsif SHIFT_EN = '1' then
>     SHIFT_REG(76 downto 1) <= SHIFT_REG(75 downto 0);
>     SHIFT_REG(0) <= '0';
>    end if;
> end if;
> end process;
>
> SOUT <= SHIFT_REG(76);
>
> -----------------
>
> The p2s register works fine; however, I will only be receiving across
> the interface 77 clocks! So how do I load the register initially? Is it
> permissable simply to gate in an extra clock(from the on board free
> running clock) for loading purposes?
>
> Such as :
>
> CLK <= CLK_77 or (CLK_1MHZ and ONE_PERIOD);
>
> Where ONE_PERIOD is high asserting pulse at the appropriate LOAD time.
>
> The reason I ask is this -- I do not like to put anything in front of
> the clock of a long shift register in order to limit any problems with
> clock skew between registers. The incoming 77 clocks(named CLK_77) are
> 1MHz clock periods.
>
> Thanks in advance....
>



Article: 38612
(removed)


Article: 38613
Subject: Re: I2C multiplexer
From: "AH" <akha@attbi.com>
Date: Sat, 19 Jan 2002 02:21:41 GMT
Links: << >>  << T >>  << A >>
Because the SFP modules I want to connect to are all internally hardwired to
the same addresses.  Also I need to connect much more than the maximum
specified 400pf loading.  My cpld works now anyways :)  It had me worried
for awhile because of some bugs and the new debug code was not fitting.  Now
I can enjoy the weekend.

Hope you have a great weekend too!

Andy


"Randy Bolling" <rbolling@tampabay.rr.com> wrote in message
news:fW028.364844$oj3.71179533@typhoon.tampabay.rr.com...
> Andy,
>
> I2C is a multi-drop bus, why multiplex a multi-drop bus?
>
> Randy Bolling
>
> "Andrew Ha" <akha@cisco.com> wrote in message
> news:3C45D59A.F7C0B6CE@cisco.com...
> > Is there verilog code available in public domain that will multiplex an
> > I2C bus among multiple I2C busses?
> >
> > Thanks,
> >
> > Andy
> >
> >
> >
> >
>
>



Article: 38614
Subject: Re: Shift Register question
From: JoeG <jgalle@pacbell.net>
Date: Sat, 19 Jan 2002 04:27:45 GMT
Links: << >>  << T >>  << A >>
I need one more clock -- the interface spec requires that the msb(bit 76) be
available before the first clock at SOUT -- hence the first clock will make
shift bit75 to SOUT.

Thanks for any insight ....

Kevin Neilson wrote:

> It seems like 77 clocks are enough.  On cycle 0, you enable LOAD so after
> that cycle SOUT is SHIFT_REG_IN(76).  On the next 76 cycles, the other 76
> bits are shifted into SOUT.
>
> "Joe" <ja.gallegos@boeing.com> wrote in message
> news:3C48AA83.35FDF91@boeing.com...
> > I have a simple 77 bit parallel to serial shift register w/ an
> > asynchronous reset_n and a synchronous load:
> > ---------------
> > p2s: process(CLK, RESET_N)
> > begin
> >
> > if RESET_N = '0' then
> >  SHIFT_REG <= (others => '0');
> > elsif (CLK'event and CLK = '1') then
> >    if LOAD = '1' then
> >    SHIFT_REG <= SHIFT_REG_IN;
> >    elsif SHIFT_EN = '1' then
> >     SHIFT_REG(76 downto 1) <= SHIFT_REG(75 downto 0);
> >     SHIFT_REG(0) <= '0';
> >    end if;
> > end if;
> > end process;
> >
> > SOUT <= SHIFT_REG(76);
> >
> > -----------------
> >
> > The p2s register works fine; however, I will only be receiving across
> > the interface 77 clocks! So how do I load the register initially? Is it
> > permissable simply to gate in an extra clock(from the on board free
> > running clock) for loading purposes?
> >
> > Such as :
> >
> > CLK <= CLK_77 or (CLK_1MHZ and ONE_PERIOD);
> >
> > Where ONE_PERIOD is high asserting pulse at the appropriate LOAD time.
> >
> > The reason I ask is this -- I do not like to put anything in front of
> > the clock of a long shift register in order to limit any problems with
> > clock skew between registers. The incoming 77 clocks(named CLK_77) are
> > 1MHz clock periods.
> >
> > Thanks in advance....
> >


Article: 38615
Subject: Re: Should clock skew be included for setup time analysis?
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 19 Jan 2002 12:08:59 GMT
Links: << >>  << T >>  << A >>
On Wed, 16 Jan 2002 22:29:20 GMT, Ray Andraka <ray@andraka.com> wrote:
>The other case, where clocks are async to each other, it is still a good idea to
>constrain the path because you want to minimize the transport time from the
>flip-flop in one domain to the flip-flop in the other domain

Up to here, I agree.

>so as to maximize the metastability settle time.

But not to this.

Since the clocks are async to each other, constraining the delay between
the source ff Q and the dest ff D (the data path) will in no way affect
the metastability of the system. The dest FF is the one that can go
metastable, and the delay to its D pin does not affect the situation
that the source FF can change at arbitrary times relative to the dest
FFs clock time. Playing with resolution time occurs between the dest FF,
and the logic that it drives, which should also be in the dest FFs
clock domain.


>A from:to constraint is needed here so that the
>tools do this.  So even though intuition might indicate that a timing constraint
>is not needed here since you *will* go metastable at some time, the truth is a
>constraint is vital here to keep from eating up your metastability resolution
>time with propagation delay.

Sorry, disagree as explained above, and in gory detail below.

>In this case, the skew doesn't matter much, so it
>probably doesn't hurt to include it (it is meaningless anyway).  I usually
>floorplan the flops on each side of a crossing like this so that they are in
>adjacent slices within a CLB.  That alone doesn't guarantee use of the fast
>connect, but it at least makes it possible.

If you divide up the cycle time of the dest FF in to an arbitrary number
of small time slices (N), the probability of any transition event occuring
in any specific time slice is 1/N. Of these time slices, some meet the
setup and hold requirements, and some violate setup or hold. When you
change the delay from the source FF to the dest FF, you change which
time slice a specific transition will occur in, but the probabilities
don't change, it is still 1/N for each slice, and therefore, metastability
is not affected.

Given the above, time specs for these inter-clock domain signals is still
useful. What you are constraining is the worst case arrival time for the
synchronizer (starting at the dest FF) to start resolving a transition,
but the granularity is dest clock period.

Here's a contrived example:

Src clock 20MHz  (50ns)
Dest clock 25MHz (40ns)

Src FF clk-to-out 1ns
Dest FF setup time 2ns
Dest FF hold time 0ns

Assume 2 stage synchronizer

Path delay 30ns

Scenario 1: just in time

Src changes, 31ns later arrives at dest, 1.1 ns before dest clock
Dest FF sees the transition OK
40 ns later the second stage dest ff outputs the changed data

time to get the transition cleanly into the dest domain is
31+1.1+40 ns = 72.1 ns

Scenario 2: just missed it

Src changes, 31ns later arrives at dest, 2 ns after dest clock
Dest FF does not see the transition
40 ns later, Dest FF sees the transition OK
40 ns later the second stage dest ff outputs the changed data

time to get the transition cleanly into the dest domain is
31+38+40 nS = 109 ns

Scenario 3: resolved metastable

Src changes, 31ns later arrives at dest, 0.5 ns before dest clock
Dest FF goes metastable
10 ns later dest FF resolves metastable
30 ns later the second stage dest ff outputs the changed data

time to get the transition cleanly into the dest domain is
31+.5+40 ns = 71.5 ns

If we assume that the 40 ns is sufficient to resolve all the
metastables we care about ( :-) ) , then in the limit, for the
above example we know we can get the signal from src to dest
in somewhere between 71 and 111 nS.

Positive and negative skew on the clock to the source FF has
NO affect on these calculations. (the 50nS cycle time does
not appear in any of the calculations)

Positive skew on the dest FF clock (late arrival of the clock)
will detract from the resolution time within the synchronizer,
but this is not the path we are talking about. It will also
add to to effective delay, increasing the 71 and 111 lower
and upper bounds. Negative skew has the opposite effect.

If we didn't constrain the the src to dest path, and the
router made it a 60 ns path, we would still have lower and
upper bounds ( 101 and 141 ), but the probability of
metastability would be the same.

So ....... I do put constraints on these paths, but is to
bound the time it takes the signal to get to the
synchronizer.

Philip Freidin



Philip Freidin
Fliptronics

Article: 38616
Subject: initial value
From: Benni <rt@wrt.ag>
Date: Sat, 19 Jan 2002 04:35:28 -0800
Links: << >>  << T >>  << A >>
I am verilog freshman.Now ,i am doing a training.
There is a variable.i need give it a initial value(variable).when one condition is meet,it will subtract 1 itself,otherwise kept.The following is my code.
************************************
reg [5:0] k;
integer   n;

always @(posedge Clock or negedge Rst_N )
begin
 if  (~Rst_N)
    k<=0;
 else 
  begin
   k<=A;//(initial value (variable))
   if(n==8) //meet one condition
          k<=k-1;//subtract  1
   else
          k<=k;  //keep
  end
end             
when i simulate with modelsim,it was wrong.where do i error?
can you advise me?
************an urgent heart*********

Article: 38617
Subject: Re: initial value
From: Benn <sreg@ir.iyt>
Date: Sat, 19 Jan 2002 05:20:11 -0800
Links: << >>  << T >>  << A >>
afterward,i change:
always @(posedge Clock or negedge Rst_N ) 
begin 
if (~Rst_N) 
k<=A; 
else 
begin 
k<=A; //(initial value [variable]) 
if(n==8) //meet one condition 
k<=k-1;//subtract 1 
else 
k<=k; //keep 
end 
end 
when i simulate with modelsim,k is always 0.
A is variable too.when one condition is meet.A value will change too.that is: 
********************************************* 
assign A=(Remainder32==0)?Quotient32:(Quotient32+1); 
Both Quotient and Remainder is read out from a 32bit register.they are variable. 
when i simulate with modelsim,k is always 0 .Your advice is important for me! 
************an urgent heart*********

Article: 38618
Subject: Re: initial value
From: Benny <stiurh@reih.irg>
Date: Sat, 19 Jan 2002 05:52:04 -0800
Links: << >>  << T >>  << A >>
i want to do other by K value change.when k equal 0,the 32bit register value maybe only change.other process will proceed by K value change.
or can you tell me how to implement?
***********an urgent heart*********

Article: 38619
Subject: Re: VirtexII ES configuration
From: "rs" <remi-seglie@infonie.fr>
Date: Sat, 19 Jan 2002 17:16:26 +0100
Links: << >>  << T >>  << A >>
Thanks for your response.
I use X2CV-1000BG575. Concerning software, I use ISE4 with Service Pack 3. I
don't use daisy and my timing seems to be correct. Of course I use CCLK for
clock startup.
Just one thing : I use "Non-Contiguous Data Strobe", i.e. "Controlled CCLK"
: one pulse of CCLK during CS and WRITE are low, witch seems to be ok with
the ES part.
If any other idea... I continue to search on the Xilinx web site and verify
my board...


"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3C489408.E432C4C6@xilinx.com...
> RS,
>
> Since all devices are tested on the tester in select map slave mode
(fastest
> and easiest mode to use on the tester), I am surprised.
>
> Since it works with JTAG, the part is good.......
>
> Have you read all of the technical answers on the web concerning Virtex II
> configuration?  There were some bug fixes in the service packs, and you
may
> need one of these (for example, daisy chanining devices had a bug fix).
>
> What part are you playing with?
>
> Austin
>
> rs wrote:
>
> > Does anybody succeed in configuring an Virtex II ES with slave select
map
> > mode ?
> > It's working with JTAG but not with this mode and INIT never go low.
> > I apply the modifications concerning the ES Errata sheet (timing of RW
and
> > CS with CCLK).
> > Does anybody has an idea ?
>



Article: 38620
Subject: Re: initial value
From: vhdlcohen@aol.com (VhdlCohen)
Date: 19 Jan 2002 18:26:28 GMT
Links: << >>  << T >>  << A >>
Benn sreg@ir.iyt wrote
>afterward,i change:
>always @(posedge Clock or negedge Rst_N ) 
>  begin 
>    if (~Rst_N)  k<=A; 
>    else begin 
>      k<=A; //(initial value [variable]) 
>      if(n==8) //meet one condition 
>         k<=k-1;//subtract 1 
>      else k<=k; //keep 
>    end 
>  end 
>when i simulate with modelsim,k is always 0.
>A is variable too.when one condition is meet.A value will change too.that is:
>
>********************************************* 
>assign A=(Remainder32==0)?Quotient32:(Quotient32+1); 
>Both Quotient and Remainder is read out from a 32bit register.they are
>variable. 
>when i simulate with modelsim,k is always 0 .Your advice is important for me!
>
Several comments about your style: 
You do NOT need the
    k<=A; //(initial value [variable])
    else k<=k; //keep    
because k is a FF.  Thus, code should look like: 

 always @(posedge Clock or negedge Rst_N ) 
   begin 
     if ( !Rst_N)  k<=A;  // use ! istead of ~
     else if(n==8) //meet one condition 
          k<=k-1;//subtract 1 
   end 
If "n" is modified somewhere else and == 8, the k FF will decremenet. 
--------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8 
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------


Article: 38621
Subject: Re: verilog/vhdl codeing style
From: vhdlcohen@aol.com (VhdlCohen)
Date: 19 Jan 2002 18:31:06 GMT
Links: << >>  << T >>  << A >>
>who can introduce the some  books,link,resource about verilog/vhdl codeing
>style ,experience?
>
You'll find that my latest book " Real Chip Design and Verification Using
Verilog and VHDL, 2002 isbn 0-9705394-2-8" (available at my site) provides
practical examples and guidelines for synthesis and verification.  
You'll find this book very interesting and applicable to current users and as a
training book.  This is a book that I wished I had when I was doing designs and
training.  I found during my consulting and training experiences that students
of HDLs had more trouble with design concepts than with the HDLs.  That book is
targeted for current design engineers because it addresses design issues, with
HDL as a vehicle for implementation.  Book is also intended for users who want
to transition into the "other" HDL,  and for students of HDLs.  

>From foreword: "Ben bridges the gaps in a designer's knowledge, he covers the
gaps left by other texts ... bridges simulation and synthesis, and this
acknowledges that implementation and verification must both be done in design"
Synplicity.  
"This book is one of the best investments that a logic designer can make"
Cadence. 

See my site for TOC. 
Ben
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8 
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------


Article: 38622
Subject: Dev tools needed
From: mechanic_mike@hotmail.com (Mechanic Mike)
Date: 19 Jan 2002 10:51:45 -0800
Links: << >>  << T >>  << A >>
I just got small stock of xc4036xla. But those are useles as far i
don't have development tools for those. So if you can help me to get
working development tools for that chip i will send 5 of those to you.
Thanks.

Mike

Article: 38623
Subject: Re: initial value
From: "AMID GUBTA" <none@mediaone.net>
Date: Sat, 19 Jan 2002 21:07:07 GMT
Links: << >>  << T >>  << A >>
your code looks funny, but it will be better if you supply with it , the
testbench u used and the proper variable definations. just seeing you code ,
my guess is , youare getting some problem by using the non-block assign..u
are using the last cycle-value of k.
try changing non-block(<=) to (=) and see if it helps.
--amit
"Benni" <rt@wrt.ag> wrote in message news:ee74507.-1@WebX.sUN8CHnE...
> I am verilog freshman.Now ,i am doing a training.
> There is a variable.i need give it a initial value(variable).when one
condition is meet,it will subtract 1 itself,otherwise kept.The following is
my code.
> ************************************
> reg [5:0] k;
> integer   n;
>
> always @(posedge Clock or negedge Rst_N )
> begin
>  if  (~Rst_N)
>     k<=0;
>  else
>   begin
>    k<=A;//(initial value (variable))
>    if(n==8) //meet one condition
>           k<=k-1;//subtract  1
>    else
>           k<=k;  //keep
>   end
> end
> when i simulate with modelsim,it was wrong.where do i error?
> can you advise me?
> ************an urgent heart*********



Article: 38624
Subject: Re: Shift Register question
From: Ray Andraka <ray@andraka.com>
Date: Sat, 19 Jan 2002 22:43:15 GMT
Links: << >>  << T >>  << A >>
I assume your local clock (the free running one you mention) is quite a bit
higher than your shift clock.  That being the case, a better solution is to
transfer the incoming clock and data to your master clock domain, then detect
edges on your incoming clock.  Usually on a sync serial line, the data
transitons are arranged to fall halfway between the active edges on the
clocks.   That buys some resistance to slop.

To do this, I like to use a toggle register clocked by your incoming clock.
Delay the data by a register to match the delay on the clock to keep it more or
less centered.  The output from the toggle register goes through a synchronizing
flip-flop clocked by the master clock, then to a simple state machine that
generates a 1 clock wide pulse each time the synchronized toggle signal changes
state.  That becomes pulse becomes the shift pulse for your shift register,
which is now in the master clock domain.


Joe wrote:

> I have a simple 77 bit parallel to serial shift register w/ an
> asynchronous reset_n and a synchronous load:
> ---------------
> p2s: process(CLK, RESET_N)
> begin
>
> if RESET_N = '0' then
>  SHIFT_REG <= (others => '0');
> elsif (CLK'event and CLK = '1') then
>    if LOAD = '1' then
>    SHIFT_REG <= SHIFT_REG_IN;
>    elsif SHIFT_EN = '1' then
>     SHIFT_REG(76 downto 1) <= SHIFT_REG(75 downto 0);
>     SHIFT_REG(0) <= '0';
>    end if;
> end if;
> end process;
>
> SOUT <= SHIFT_REG(76);
>
> -----------------
>
> The p2s register works fine; however, I will only be receiving across
> the interface 77 clocks! So how do I load the register initially? Is it
> permissable simply to gate in an extra clock(from the on board free
> running clock) for loading purposes?
>
> Such as :
>
> CLK <= CLK_77 or (CLK_1MHZ and ONE_PERIOD);
>
> Where ONE_PERIOD is high asserting pulse at the appropriate LOAD time.
>
> The reason I ask is this -- I do not like to put anything in front of
> the clock of a long shift register in order to limit any problems with
> clock skew between registers. The incoming 77 clocks(named CLK_77) are
> 1MHz clock periods.
>
> Thanks in advance....

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759





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