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Messages from 39050

Article: 39050
Subject: Re: Spartan II power-up current - again and again, and again, and .....
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 30 Jan 2002 11:35:49 -0800
Links: << >>  << T >>  << A >>
David,

That is in the data sheet, and also easy to calculate with the power estimator
tool (on the web).

Depending on clock frequencies, anywhere from 50 mA to 2 or so amperes in a
larger devices (may need a heatsink if you have that much current).

The current at 0C is 500 mA, even for an I grade part, so this only appies to
temperatures below 0C for startup.

An interesting side note:  a customer was unable to supply 2 amperes, but was
able to supply 500 mA.  So they power ON, wait 200 ms for DONE, and then power
off for a few ms, and power ON again.  The cycle is repeated until it powers
ON.  It always powers ON after a few cycles, as the die warms up nicely to >
0C (2.5V * 0.5 A = 1.25 Watts).

No issues with reliability, so, it works fine.  Now, if you had a -40C wind
blowing, you would never warm up, so I would prefer customers provide the 2
amperes at -40C, where it is specified to work.

Austin



"Deli Geng (David)" wrote:

> >
> > I'm not a Xilinx rep, but I have had a couple of conversations with Kim
> > Goldblatt about this. Basically, they are very confident that they will
> > be able to reduce the curve somewhat, but I seem to recall that the
> > improvement was not large. But that may be due to the chip I was asking
> > about, the XC2S50, IIRC. This device was said to be expected to pass 1.5
> > Amp at industrial temps vs. 2 Amps in the data sheet. Better for sure,
> > but not a large improvement.
> >
>
> Wow!!! So big current. How about its working current?


Article: 39051
Subject: Re: Signal assignment mismatch with Aldec 5.1 problem
From: Ray Andraka <ray@andraka.com>
Date: Wed, 30 Jan 2002 19:49:24 GMT
Links: << >>  << T >>  << A >>
romx3<=out_0(8 downto 0);  ?

Antonio wrote:

> with Aldec 5.1 schematic I'm assigning
>
> out_0 : out STD_LOGIC_VECTOR(9 downto 0);
>
> to the bus
>
> signal to_romx3 : STD_LOGIC_VECTOR (8 downto 0);
>
> the result is
>
>        out_0(0) => DANGLING_U2_out_0_0,
>        out_0(1) => to_romx3(0),
>        out_0(2) => to_romx3(1),
>        out_0(3) => to_romx3(2),
>        out_0(4) => to_romx3(3),
>        out_0(5) => to_romx3(4),
>        out_0(6) => to_romx3(5),
>        out_0(7) => to_romx3(6),
>        out_0(8) => to_romx3(7),
>        out_0(9) => to_romx3(8),
>
> while I would want
>
>        out_0(0) => to_romx3(0),
>        out_0(1) => to_romx3(1),
>        out_0(2) => to_romx3(2),
>        out_0(3) => to_romx3(3),
>        out_0(4) => to_romx3(4),
>        out_0(5) => to_romx3(5),
>        out_0(6) => to_romx3(6),
>        out_0(7) => to_romx3(7),
>        out_0(8) => to_romx3(8),
>        out_0(9) => DANGLING_U2_out_0_0,
>
> How I could do this ??

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 39052
Subject: Re: 9 or 8 bits for image processing ?
From: "Hristo Stevic" <hristostev@yahoo.com>
Date: Wed, 30 Jan 2002 19:51:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> wrote in message
news:3C58468A.4FDC5E99@andraka.com...

> Your grey scale never goes negative, so that 9th bit is always 0. 
I know

> Use unsigned arithmetic instead.  Note that if your processing can produce
> negative values, you'll probably want to clamp it so that it doesn't
> over/underflow the 8 bits.

Well if i expect to get negative values, and i use UNSIGNED arithmetic,
how could differentiate between positive and negative values?

 



-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 39053
Subject: Re: 9 or 8 bits for image processing ?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 30 Jan 2002 19:52:51 GMT
Links: << >>  << T >>  << A >>
You can look at the carry out and the top bit of your arithmetic to determine
overflow.  Often it is jsut as easy to expand to 9 bit arithmetic internally to
get a sign bit which you then use to clamp the result.

Hristo Stevic wrote:

> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3C58468A.4FDC5E99@andraka.com...
>
> > Your grey scale never goes negative, so that 9th bit is always 0.
> I know
>
> > Use unsigned arithmetic instead.  Note that if your processing can produce
> > negative values, you'll probably want to clamp it so that it doesn't
> > over/underflow the 8 bits.
>
> Well if i expect to get negative values, and i use UNSIGNED arithmetic,
> how could differentiate between positive and negative values?
>
>
>
> --
> Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39054
Subject: Re: FPGA or Micro-controller in Lowpower designs?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 31 Jan 2002 09:10:45 +1300
Links: << >>  << T >>  << A >>
Arash Salarian wrote:
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3C575644.364D6C8F@yahoo.com...
> > Arash Salarian wrote:
> > >
> > > First of all, thank you all for your answers and help.
> > >
> > > "Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message
> > > news:CYu58.6963$O5.17299@nntpserver.swip.net...
> > > > > > I'm starting a new design in which I'm using a multi-channel A/D
> with
> > > a
> > > > low
> > > > > > sampling-rate and Flash memory for the storage and the system is
> going
> > > > to be
> > > > > > powered by battery. In this stage, I'm not yet sure if using a
> FPGA
> > > > would be
> > > > > > wise, as I'm very concerned with the power consumption. The gate
> count
> > > > of
> > > >
> > > > You need to tighter specify what your requirements
> > > > How much data?
> > > I'm going to use 4 channels of A/D at 200Hz, but only to store 3 of them
> > > (one is used to monitor the battery). Data is stored on a Flash,
> MultiMedia
> > > Card (i.e. SPI interface...) with 64+Mbytes. That means the the system
> > > should be able to function over 15 hours by using a small Litium-Ion
> > > battery.
> >
> > I don't remember the output voltage of a Li-ion battery. Is it higher
> > than 3.3 volts so that a simple LDO regulator is sufficient? I seem to
> > recall that the MSP430 will operate down to 1.8 volts but needs more
> > like 2.7 volts to program it's internal flash. BTW, the high end
> > MSP430F148/9 have 48/60 KB of Flash on chip. If your program only takes
> > 1 or 2 kBytes, you might be able to use the internal Flash for your
> > data. But I assume you need it to be removable.
> >
> > Just for my own benifit, how many mAHours can you get from a Li-ion cell
> > running a device at 2.7 or 3.3 volts? You might also consider using a
> > small switcher to optimize your efficiency and make the unit run when
> > the cell drops below (or starts below) the operating voltage of your
> > chips. They can be very small, but of course they cost a bit more than
> > an LDO.
> 
> I'm considering using a Li-ion battery from Renata (ICP633027) wich is small
> is size (27x30x6.3 mm) and has a 300mAh capacity. The voltage is between 4.1
> to 2.75 over the dicharge period and I guess although the 4.1v is more than
> the recommened value for the MCU, yet as it's within the absolute maximum
> range, would be OK. Well I'm not sure if this is a good practice, an have to
> investigate more as omitting the LDO is so nice but the effect of running
> the device out if it's recomended rating for a long period is not that
> beautiful...
> 
> Anyway, I'm going to use one channel of the A/D to monitor the battery
> level, so switching the LDO on a certian point of the discharge curve is an
> option but all this means area and weight and I'm too conservative about
> them in this design..

 You need to check battery voltage on charge, as well.
( DC Rise, as well as spikes on charger attach after on, if possible )

 The Cygnal C8051F3xx family is very small (3mmx3mm), and 
has a 5.8V MAX rating on the 5V tolerant IO's, and a 4.2V MAX 
Vcc - so you  could maybe use an IO pin to shunt a series diode.

-jg

Article: 39055
Subject: Re: The LUT puzzle, Iam on the way
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 30 Jan 2002 21:14:19 +0100
Links: << >>  << T >>  << A >>
"Peter Alfke" <peter.alfke@xilinx.com> schrieb im Newsbeitrag
news:3C575471.7916DF9@xilinx.com...

> Whether it is 65,000 or only a few thousand, a LUT is a very versatile
tool. I
> still remember my enthusiasm when, arriving here at Xilinx, I could draw a
> circle around any piece of logic with 4 inputs + one output ( and no
flip-flop
> inside) and I could say: "Fits into one LUT, I don't care how, let's go
on".
> Gets your mind off the nitty-gritty :-)

Yes. But isnt a good understanding of the theory a driving force, an
important factor for developing better circuits? What would have happend to
the digital logic if there was no Boolean, Karnaugth etc.??
Yes, the "has 4 inputs, one output, fits in a LUT " is a enineering approach
that is OK, especially when you are in a tight schedule. But what would you
say if a new job candidate tells you "Hmm, with 8 bit I can store a two
digit decimal from 00..99, maybe a little bit more. I dont care, my new P4
has plenty of bytes" ??

By the way, It seems I was a little bit tired yesterday. The number of  24
permution codes is 43008, not 40008 as stated in my last posting (43008 is
written on my sheet of paper, but there was no CRC on the paper-email Xfer
;-). My programm had also a minor bug. But now I also get the value of 3984
distinct functions for a 4I-LUT as stated in the FAQ ;-)))

--
MfG
Falk

P.S. Maybe I should try to compute the number of possible functions with a
5I-LUT. But then the number of codes increase to 2^32, also the number of
permutations to 120, giving an overall factor of 5x2^16=327680. Since it
take ~1min. for the 4I-LUT, this would mean ~227 days of computing. Hmm, is
it worth a trial?




Article: 39056
Subject: Re: Dynamic Reconfiguration of single Xilinx FPGA
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 30 Jan 2002 12:18:13 -0800
Links: << >>  << T >>  << A >>
Steve, you are, of course, right.
But nobody should get the impression that the CPLD-based controller is a
necessity. The FPGA can also start its own Master Serial configuration "without
any external help".

Peter Alfke
===============================
Steve Casselman wrote:

> The Hot 2 system works this way. You just route a I/O to the program pin
> (make sure you pull it up and come up tristated). 300ns after you drive the
> pin low you force the internal state machine into the "clear memory" state
> and then your device will be reset. You have to have some way to reprogram
> it from there. I have a little xc9500 that looks at all the signals and
> starts to feed the fpga a configuration when it want to reboot (either from
> a flash or a static ram).
>
> Steve
>
> "Fong Chii Biao" <ericfcb@tm.net.my> wrote in message
> news:3c50130f_1@news.tm.net.my...
> > Hi, i really need help bout this, as i worked for this for a week, no
> result
> > turns out.
> > first, any one ever try reconfigure Xilinx FPGA using the chip itself?
> (i'm
> > using a single XC4010XL)
> >
> > the problem is.. when i connect the user I/O to the /program pin, the
> > configuration can't even complete at power start up..
> > when i disconnect the I/O .. the configuration working pretty well.. whats
> > the solution for this?
> >
> > anyone, anyone at all, who has any idea, ple reply to me, thnaks
> >
> > chiibiao
> >
> >


Article: 39057
Subject: Re: RLOCS with combinatorial logic
From: Ray Andraka <ray@andraka.com>
Date: Wed, 30 Jan 2002 20:21:39 GMT
Links: << >>  << T >>  << A >>
In order to put the RLOCs in the vhdl code, it has to be coded into
primitives.  One way is to instantiate LUTs, which will accept RLOCs.  The
difficulty there is the LUT needs the contents described both in an init
generic (for simulation, format is a bit vector) and in an init attribute
(for place and route, format is an ascii hex string).  Direct
implementation makes for code that is very hard to read, maintain and
debug.  It is also error prone.  If you are using synplicity you can
separate the function for each LUT off into a separate component and put
an xc_map attribute in the component's architecture declarations.  That
lets you write the contents of the lut in readable VHDL and forces the
synthesis to create a LUT with those contents.  You can put RLOCs on the
fmapped logic where it is instantiated.  This is awkward, but it works. An
example fmapped component is:

--FMAP'd or2
library IEEE;
use IEEE.std_logic_1164.all;

entity fmap_or2 is
  port ( a, b : in std_logic;
  z : out std_logic);
end fmap_or2;
architecture rtl of fmap_or2 is
attribute xc_map : STRING;
attribute xc_map of rtl : architecture is "lut";
attribute syn_hier: string;
attribute syn_hier of rtl:architecture is "hard";
begin
  z <=  a or b;
end rtl;

Another option is to use a function to parse a boolean string and convert
that to the init attribute for LUTs.  There is a link to a function
someone wrote to do this on the bottom of the links page on my website.
To use it, you instantate a LUT, and put a function call containing the
boolean string of the function you want in the LUT in the Init.  Note that
you need to also convert that string to a hex value and put it in an init
attribute for it to pass the value through the synthesis.


newman wrote:

> I've got a module that has a bunch of combinatorial logic that is
> instantiated via generate statements, and also has two synchronization
> registers.  For various reasons, that I cannot go into, I don't want
> the synthesizer to optimize out redundant logic, so I put a dont_touch
> attribute on the module ... so far so good.  When I look in the FPGA
> editor, it looks like the combinatorial logic has been compacted into
> the LUT's, so there does not appear to be a 1:1 correspondence between
> the instantiated combinatorial logic and the LUT's.
> What I want to do, but don't know how best to proceed, is to be able
> to locate this module to a specific area of the FPGA.
>
> My first preference would be to put attributes or something in the
> VHDL to do this.
> My second preference would be to use the UCF if possible.
> My third preference is to use the floorplanner or whatever.
>
> I currently am using FPGA Express, but would be willing to go through
> the hassle of sharing a dongle with my co-workers if Synplicity gets
> me there via the VHDL approach.
>
> Thanks for taking the time to read about my dilemma.
>
> Newman

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39058
Subject: Re: The LUT puzzle, Iam on the way
From: Ray Andraka <ray@andraka.com>
Date: Wed, 30 Jan 2002 20:39:50 GMT
Links: << >>  << T >>  << A >>
Perhaps a quick visit to the permutations and combinations chapter in the front
of your probability and statistics book would give you the info you need to
directly calculate the unique logic functions?  I'd do it, but I am feeling
exceptionally lazy today, and like peter inferred, it falls more or less in the
trivia bin.  You don't need to know the number or even how to arrive at it to be
a successful FPGA designer, no more than you need to know the details of the
transistors used to make up the LUTs.

Falk Brunner wrote:

> By the way, It seems I was a little bit tired yesterday. The number of  24
> permution codes is 43008, not 40008 as stated in my last posting (43008 is
> written on my sheet of paper, but there was no CRC on the paper-email Xfer
> ;-). My programm had also a minor bug. But now I also get the value of 3984
> distinct functions for a 4I-LUT as stated in the FAQ ;-)))
>
> --
> MfG
> Falk
>
> P.S. Maybe I should try to compute the number of possible functions with a
> 5I-LUT. But then the number of codes increase to 2^32, also the number of
> permutations to 120, giving an overall factor of 5x2^16=327680. Since it
> take ~1min. for the 4I-LUT, this would mean ~227 days of computing. Hmm, is
> it worth a trial?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39059
Subject: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
From: Ray Andraka <ray@andraka.com>
Date: Wed, 30 Jan 2002 20:53:03 GMT
Links: << >>  << T >>  << A >>
An IDE controller that just does sector reads and sector writes is pretty
straightforward in the FPGA.  For what you are doing, I suspect that is all you
need.  The hardest part is digesting the ATA-5 spec.

Iwo Mergler wrote:

> Steven Derrien wrote:
> >
> > Hello,
> >
> > This post is just for submitting an idea to those who are familiar with
> > embedded system design, in order to get some feed-back (with respect to
> > feasibility, cost, usefulness and so on?).
> >
> > The basic idea is the following :
> >
> > We want to design a reconfigurable SoC, which will be connected to an
> > IDE hard-drive,  used by the application running on the SoC. One of the
> > key point, is that we need to perform dynamic reconfiguration of the
> > FPGA.
> >
> > Our idea is to use the Hard-drive memory to store the various FPGA
> > configurations, and to use a small 32 I/O MCU (8051) to perform the FPGA
> > reconfiguration from the HDD. (the 8051 would share the IDE bus with the
> > FPGA, but they would have a mutual  exclusive use of the HDD, since the
> > MCU would only be used during reconfiguration)
> >
> > Since the FPGA should be a relatively big Virtex/Spartan-II, and since a
> > large density configuration EEPROMs (several Mbits) are quite expensive
> > compared to a small MCU, we feel that this could be a nice way to reduce
> > the total system cost.
> >
> > Now we are wondering whether this idea is good or not :), we are
> > specifically concerned with :
> >
> > - PCB layout and signal integrity problems due to the fact that the IDE
> > connection is shared between the MCU and the FPGA. For ex. would it be
> > possible to use high-speed IDE (50Mhz clock) protocols from the FPGA ?
>
> A standard IDE interface supports 2 devices on the cable, that is, 2 cmos
> inputs per signal. I have the PCB of an old IDE drive in front of me and
> it looks like they use a series termination of 330 Ohm between the cable
> and the ASIC.
>
> My suggestion is to have a close look at a modern harddrive and mime that
> circuitry for your microcontroller. Then you connect the controller instead
> of the second disk. This way, the micro will load the signals like a slave
> disk does. For the transfer speeds you are going to achieve with the micro,
> the weird cable shape shouldn't matter.
>
>     #============#=====#
> IDE PORT       HDD1  HDD0
>
>     #============#=====#
>   FPGA          uC    HDD
>
> >
> > - Reliability   : since the hard-drive will be used for both read and
> > write operation during the application, we must ensure that some part of
> > the HDD storage is locked (to guarantee that the configurations are not
> > overwritten by mistake)
>
> I don't think there is an easy way to 'lock' part of the disk without changing
> the disk's firmware. If you can control the IDE IP in your FPGA, you could
> ignore write requests for a certain block range...
>
> >
> > - Feasibility  : How difficult would it be to design and debug such a
> > system ?
>
> Not having done it myself - it shouldn't be too hard, as long as you have a
> good logic analyser... ;^)
>
> Have a nice day,
>
> Iwo

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39060
Subject: Re: Flex10KA vs MAX7000S
From: Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com>
Date: Wed, 30 Jan 2002 15:07:46 -0600
Links: << >>  << T >>  << A >>
Chris Cowdery wrote:
> 
> Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com> wrote in message news:<a3809f$aau$1@newsreader.mailgate.org>...
> > Chris Cowdery wrote:
> > >
> > > I've got a cut down PCI design which works nicely in a
> > > MAX7256SQC208-7. I have changed device to a FLEX10KA30-1 to port it to
> > > CardBus.
> > >
> >
> >         Why use FLEX 10KA?
> > If you want to stick with Altera parts, why not use FLEX 10KE or ACEX
> > 1K?
> 
> Mostly because I've got a drawer full, and on paper they look like
> they will support a PCI core. Also, 10KE won't drive a 5V TTL part,
> and I suspect ACEX is the same.
> 

        If you already have abundance of FLEX 10KA, that makes sense why
you are using FLEX 10KA.
According to FLEX 10KE or ACEX 1K datasheet, they both state that both
parts can drive or take in 5V TTL signals directly without external
resistors.
I still think FLEX 10KE-1 or ACEX 1K-1 (-1 means speed grade -1) will be
a better choice because they are faster, but since FLEX 10K30A-1 4-input
LUT delay is 0.8ns, that should be okay assuming that the you can keep
the unregistered input path to a FF within 3 levels of LUT for a long
routing path (FRAME# or IRDY# to AD[31:0] output FF or tri-state control
FF) or 4 to 5 levels if the routing distance is short.




> >         It looks like for Altera FLEX FPGAs (Altera ridiculously calls
> > it CPLDs), a device with a smaller speed grade number is a faster part.
> > You may want to download FLEX 10KA datasheet to verify that.
> > PCI compliance means that it is electrically compatible with PCI, but it
> > doesn't in any way guarantee that your design (your PCI IP core) will
> > meet 33MHz PCI timings.
> >         It sounds like you didn't buy your PCI IP core from Altera, so
> > you can make modifications to it.
> 
> I can.
> 

        That is good because vendor supplied PCI IP cores are typically
supplied in a netlist, and that makes it virtually impossible to modify
it.
Plus the licensing agreement of the PCI IP core bans the licensee from
modifying it most of the time.
However, the downside of a synthesizable PCI IP core is that the timings
will not be guaranteed, so you will have to manually floorplan the
timing critical parts of the PCI IP core.



> >         If your PCI IP core's parity generator was designed for a CPLD
> > (a wide product term-based device) in mind, you may need to redesign it
> > a little bit with a 4-input LUT-based FPGA's architecture in mind.
> > I am not an expert in arithmetic, but I heard that a parity of 36-bit
> > can be computed with carry chain logic or with combinational logic
> > (LUT).
> 
> Parity isn't a problem hopefully - I will ignore incoming parity,
> and for outgoing parity, I pregenerate it and store it along with
> the registers, effectively a 33bit register. You get a clock period
> to calculate it whilst the address is being latched.
> 

        Again, I believe CardBus requires data parity checking, so your
approach will violate the specification like so many other PCI devices
do.
I honestly didn't enjoy implementing a state machine checking for data
parity error, but I wanted to follow the PCI specification strictly so I
implemented a state machine to signal data parity error.
Of course, I really felt wasting time knowing that so many PCI devices
don't bother to implement it (i.e., most Intel chipsets.).
       Regarding generating parity during a target read, if your PCI IP
core supports no-wait state burst transfer, then you won't be use the
registered version of C/BE#[3:0] for parity generation.
You will have to XOR the raw (non-registered) version of C/BE#[3:0] with
the contents of the read data being the output of AD[31:0].
Because the read data will come from FFs internally, the read data can
tolerate longer LUT delays (more levels of LUT) than the unregistered
C/BE#[3:0].
In 33MHz PCI, internal FF to FF signals have 30ns to reach the
destination FF whereas PCI input signals have to read the destination FF
within 7ns.
The parity generator I described last time takes advantage of this fact,
but again I didn't come up with the original idea.



> I am using the Quartus fitter - free license at the moment, which
> doesn't support timing driven fitting. If I get the full version,
> is it smart enough to give me a working design if I tell it about
> Tsu for example?
> 
> Thanks,
> 
> Chris.


        In my opinion having synthesized my PCI IP core with ISE WebPACK
4.1 for Spartan-II XC2S150-5CPQ208 and with Quartus II 1.1 Web Edition
for FLEX 10KE100K-1 is that P&R tool won't do much good.
I have more experiences with ISE WebPACK, so I will talk about my
experience there with Spartan-II, but in that case, the P&R tool simply
couldn't meet my Tsu requirement simply with full automatic P&R (no
partial manual floorplanning) with only a Tsu <= 7ns requirement.
Looking at how the design was placed automatically, I saw that some LUTs
for several signal paths violating Tsu were being placed far away from
the destination FF.
So, I simply placed such LUTs near or in a straight path towards the
destination FF.
I had to repeat that about 10 to 12 times, each time starting over with
a new layout, but at each iteration, I will have more LUTs placed
manually, so the timing violations were gradually decreasing.
I haven't tried this approach with Quartus II 1.1 Web Edition yet, but
after I get through Quartus II 1.1's fir_filter tutorial, I will try to
do some manual placement.
Regarding how MAX+PLUS II-BASELINE's (free version of MAX+PLUS II)
non-timing driven fitter will fare is a question I don't know because
ever since I discovered that MAX+PLUS II-BASELINE doesn't support timing
driven fitting, I stopped putting any effort into getting my design to
meet 33MHz PCI timings with ACEX 1K.
My guess is that you may have to do more manual floorplanning than you
will have to do if timing driven fitting was supported.
        So, summarizing what I wrote, P&R tool is not a magical tool
that will P&R an FPGA and meet Tsu requirement if the user supplies the
timing requirement.
Actually, P&R tool is a pretty dumb tool which doesn't know where to
place a LUT even if a LUT is on a critical timing path (Like a path
starting from FRAME# or IRDY# going towards AD[31:0] output FF and
tri-state control FF.).
Assuming the user has some understanding of the target architecture,
humans can do a far better job than software placing critical timing
LUTs in the right location.
Therefore, I will not recommend spending US $2,000 for a paid version
(subscribed version) of MAX+PLUS-II, at least initially, although you
will get Quartus II 1.1/2.0 and ModelSim-AE with it, but you won't be
eligible for upgrades after a year.
Just to see how a timing driven fitter will fare, you can try out
Quartus II 1.1 Web Edition for free, and target FLEX 10KE-1 as a test
vehicle.
You can use FLEX 10KE PCI development board's pin out for the test
vehicle (That is what I do.).




Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)

Article: 39061
Subject: Re: The LUT puzzle, Iam on the way
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 30 Jan 2002 22:11:19 +0100
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
news:3C585B63.266464D2@andraka.com...

> Perhaps a quick visit to the permutations and combinations chapter in the
front
> of your probability and statistics book would give you the info you need
to
> directly calculate the unique logic functions?  I'd do it, but I am
feeling

Hmm, Iam not a a math-guy. But from the "complexity" of all these coding and
permutation it will be VERY hard to find a direct formula. As you can see
from my statistic from my last posting, the permutation are not evenly
distributed. But for the really tough math guys, a real challenge.

> exceptionally lazy today, and like peter inferred, it falls more or less
in the
> trivia bin.  You don't need to know the number or even how to arrive at it
to be

?? Trivia? So why is this 3984 number such a secret?? Everyone knows that 8
bit can represent 256 different patterns, 16 bit 65536 patterns etc. So why
does almost nobody know how much distinct functions can be implemented into
a 4I-LUT?? It is used million times a day.

> a successful FPGA designer, no more than you need to know the details of
the
> transistors used to make up the LUTs.

Yes, but again I will state that it is always usefull to see over the fence
of your main business. I had a look at the archiv, its very funny, we had
this thread in summer 2000 before ;-))
It was then renamed to "I cant stand it anymore" and, again, it ended with a
comment from Peter

 . . .no practical significance.
Get back to engineering. . . .

;-)))

And agian, I must say "Engineering needs good theory" (Yes, Iam getting
pedantic)

--
MfG
Falk





Article: 39062
Subject: Re: MapLab:30 Error in ISE 4.1i
From: "Mark van de Belt" <mark@nospam.nijenrode.demon.nl>
Date: Wed, 30 Jan 2002 22:57:32 +0100
Links: << >>  << T >>  << A >>
Check the pin locations in the .UCF file. and check the UCF file the mapper
is looking at (often another file). It is also usefull to delete the
implementation data (option in project menu)


"Marceli Firlej" <marceli.firlej@instech.com.au> schreef in bericht
news:87afde58.0201291521.52772239@posting.google.com...
> I am looking for answer to ERROR: MapLab:30 Bad format for LOC
> constraint <output> ... in ISE 4.1i. To bypass this error set the
> environment variable to 'XIL_MAP_LOCWARN'. What is a solution to this
> error?



Article: 39063
Subject: Re: glitchless clock enable/disable in spartanII
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 30 Jan 2002 14:50:30 -0800
Links: << >>  << T >>  << A >>
As usual, I agree with Phil in principle.
His statements are 100% correct, but we disagree on the seriousness of the
problem.
Metastability "usually" resolves itself in a small fraction of the 10 ns period (
100 MHz clock rate).
So the issue is: How often does it not resolve itself, and would you ever see
oscillations ?
Phil thinks it can happen more often than I think it might happen.
In the deplorable absence of quantitative data, the argument must remain
unresolved.

Every time you enable or disable CE asynchronously, you are playing Russian
Roulette. But how many chambers are empty in the revolver ? A million, a trillion,
or a gazillion?
And where is it pointed, at your brains or at your shoes? ( How serious is a
failure?)

Peter Alfke
==========
Philip Freidin wrote:

> The asynchronous CE signal is just as bad to a FF as an asynchronous D
> signal. The FF can go metastable, and you can get runt low or high
> pulses from the FF. Since this feeds your follow on counter as its
> clock, the results will be sub-optimal.
>
> The only safe way to use the CE is with a synchronous signal, so the
> asynchronous control signal should be passed through a multi stage
> synchronizer, before being presented to the CE pin.
>
> Philip Freidin
>
> Philip Freidin
> Fliptronics


Article: 39064
Subject: Re: The LUT puzzle, Iam on the way
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 30 Jan 2002 14:53:54 -0800
Links: << >>  << T >>  << A >>


Falk Brunner wrote:

>
> Yes. But isnt a good understanding of the theory a driving force, an
> important factor for developing better circuits? What would have happend to
> the digital logic if there was no Boolean, Karnaugth etc.??
> Yes, the "has 4 inputs, one output, fits in a LUT " is a enineering approach
> that is OK,

Well, as they say: "I is an engineer..."

Peter Alfke


Article: 39065
Subject: Re: The LUT puzzle, Iam on the way
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 31 Jan 2002 12:05:30 +1300
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
<snip
> > exceptionally lazy today, and like peter inferred, it falls more or less
> in the
> > trivia bin.  You don't need to know the number or even how to arrive at it
> to be
> 
> ?? Trivia? So why is this 3984 number such a secret?? Everyone knows that 8
> bit can represent 256 different patterns, 16 bit 65536 patterns etc. So why
> does almost nobody know how much distinct functions can be implemented into
> a 4I-LUT?? It is used million times a day.

> Yes, but again I will state that it is always usefull to see over the fence
> of your main business. I had a look at the archiv, its very funny, we had
> this thread in summer 2000 before ;-))
> It was then renamed to "I cant stand it anymore" and, again, it ended with a
> comment from Peter
> 
>  . . .no practical significance.
> Get back to engineering. . . .
> 
> ;-)))
> 
> And agian, I must say "Engineering needs good theory" (Yes, Iam getting
> pedantic)

 All is not wasted :- now Peter has TWO (maybe three) questions so 
ask prospective employees, about the possible LUT functions.. :-)))

-jg

Article: 39066
Subject: Re: glitchless clock enable/disable in spartanII
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 30 Jan 2002 15:25:40 -0800
Links: << >>  << T >>  << A >>
Peter Alfke <peter.alfke@xilinx.com> writes:
> As usual, I agree with Phil in principle.
> His statements are 100% correct, but we disagree on the seriousness of the
> problem.
> Metastability "usually" resolves itself in a small fraction of the 10 ns period (
> 100 MHz clock rate).
> So the issue is: How often does it not resolve itself, and would you ever see
> oscillations ?
> Phil thinks it can happen more often than I think it might happen.
> In the deplorable absence of quantitative data, the argument must remain
> unresolved.
> 
> Every time you enable or disable CE asynchronously, you are playing Russian
> Roulette. But how many chambers are empty in the revolver ? A million, a trillion,
> or a gazillion?
> And where is it pointed, at your brains or at your shoes? ( How serious is a
> failure?)

By your argument, it should be fine to feed async data directly into
the D input, since the probablity of failure will be the same (or very
close) to the probability of failure with an async CE input.

If it's a problem for the D input, it's also a problem for the CE input.

Unless there's some other reason why the window of vulnerability for the
D and CE inputs are significantly different?

Article: 39067
Subject: Re: glitchless clock enable/disable in spartanII
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 30 Jan 2002 16:45:29 -0800
Links: << >>  << T >>  << A >>

--------------7AC5AFAD48903FB8B63B142A
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Eric Smith wrote:

> Peter Alfke <peter.alfke@xilinx.com> writes:
> > As usual, I agree with Phil in principle.
> > His statements are 100% correct, but we disagree on the seriousness of the
> > problem.
> > Metastability "usually" resolves itself in a small fraction of the 10 ns period (
> > 100 MHz clock rate).
> > So the issue is: How often does it not resolve itself, and would you ever see
> > oscillations ?
> > Phil thinks it can happen more often than I think it might happen.
> > In the deplorable absence of quantitative data, the argument must remain
> > unresolved.
> >
> > Every time you enable or disable CE asynchronously, you are playing Russian
> > Roulette. But how many chambers are empty in the revolver ? A million, a trillion,
> > or a gazillion?
> > And where is it pointed, at your brains or at your shoes? ( How serious is a
> > failure?)
>
> By your argument, it should be fine to feed async data directly into
> the D input, since the probablity of failure will be the same (or very
> close) to the probability of failure with an async CE input.
>

There is no reason to assume that they are any different.
But there are mitigating circumstances:
The clock rate is modest, only 100 MHz, which allows for an extra 5 ns of metastable
delay.
The CE changes are most likely less than 1 MHz (I assume)
The Q output only clocks one flip-flop.(Note that I shift my position a bit, now
assuming a 2-bit ripple prescaler, not just one bit).  ;-)

What is the likelyhood ( expressed as MTBF) for an extra 5 ns of metastable delay when
the clock is 100 MHz and the asynchronous input changes about 1 million times per
second?

The 1997 Xilinx app note XAPP094 documents the archaic XC4005-3 at an MTBF of 100 000
years for metastable delay of 2 ns, ( really 1 million years at 10 MHz clock and 1 MHz
data, but that translates to 100 000 years at the ten times higher clock rate) and the
MTBF increases ten decimal orders of magnitude for every additional ns. That's three
additional ns in this case.
That means an MTBF of 10exp35, which is many times the age of the universe.

I am willing to take that risk. Walking across the parking lot tonight is a much bigger
risk...

Peter Alfke, Xilinx Applications



Article: 39068
Subject: Re: ROM dimension question
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Thu, 31 Jan 2002 00:52:37 -0000
Links: << >>  << T >>  << A >>
Yep.  You will often have to do a little structural coding
if you want to use insights such as 384=256+128.

Look in the documentation for XST.

"Antonio" wrote
> XST infer this ROM always like a 512x12 bit while with the subtype
> addr_reduced I mean to
> reduce the dimension of the ROM, what's wrong and what I can do to
> obtain the right result ??
> Or simply XST round the dimension of the ROM to the next power of two
> ??
>
>
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity ROMx3 is
>   port(address    : in STD_LOGIC_vector(9 downto 0);
>        SRRC_out   : out STD_LOGIC_VECTOR(11 downto 0)
>   );
> end;
>
> architecture ROMx3_arch of ROMx3 is
> begin
> process(address)
> subtype addr_reduced is integer range 0 to 383;
> variable addr : addr_reduced ;
> begin
> addr  := conv_integer(address) ;
> case addr is
>
>         -- somme per il FIR 0
>            when   0    => SRRC_out <= X"52B";
>            when   1    => SRRC_out <= X"52B";
>            when   2    => SRRC_out <= X"517";
>
> ........................
>
>            when 382    => SRRC_out <= X"ABF";
>            when 383    => SRRC_out <= X"B00";
>            when OTHERS => SRRC_out <= X"000";
>    end case;
> end process;
> end ROMx3_arch;



Article: 39069
Subject: Re: Intel vs. AMD
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Thu, 31 Jan 2002 03:32:10 GMT
Links: << >>  << T >>  << A >>
Maybe you should read:

  http://homepage.ntlworld.com/thorin92/resource/pentium.txt

Mark Kinsley wrote:
> 
> Has anybody done any benchmarking of EDA software under different hardware
> platforms...  I'm a brand-name sucker and tend to buy Intel - but how does
> AMD compare.  And how does a Celeron compare to a similar speed P3.  I'm
> using ModelSim, Leonardo Spectrum & Quartus (all under Windows).
> 
>  I've seen loads of benchmarks on the web which talk about games, office
> apps and perhaps DTP - which of these applications is most simliar to EDA
> software ?
> 
> Mark

Article: 39070
Subject: Re: Intel vs. AMD
From: VR <invalid@invalid.invalid>
Date: Thu, 31 Jan 2002 04:05:21 +0000 (UTC)
Links: << >>  << T >>  << A >>
Russell Shaw <rjshaw@ipru> wrote:
> Maybe you should read:

>   http://homepage.ntlworld.com/thorin92/resource/pentium.txt

That's a very poorly written article with few technical arguments.
However, Intel is very guilty of what he points out in the article. Final
result is that the P4 IS a crippled processor.

I have a new AMD "XP 1700+" (1.6GHz) with 512MB 2CAS PC2100 DDR RAM & UW
SCSI. If someone has a design they want me to try P&R on or synthesis or
something, let me know, I'm curious myself.

Thanks,
VR.

Article: 39071
Subject: Re: random
From: piiszo <sdkfjh@oiwergy.ksdjf>
Date: Wed, 30 Jan 2002 21:23:22 -0800
Links: << >>  << T >>  << A >>
but ,i want to get source code.

Article: 39072
Subject: JTAG Emulator Tutorial
From: satya@iwavesystems.net (satya)
Date: 30 Jan 2002 23:01:36 -0800
Links: << >>  << T >>  << A >>
Hi all,
Can any body please point me to tutorials on JTAG Emulator.Please help
me by sharing "how-to's" on JTAG Emulator.

Thanks and Regards,
- satya

Article: 39073
Subject: Re: glitchless clock enable/disable in spartanII
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 31 Jan 2002 07:04:51 +0000
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

>
> Phil thinks it can happen more often than I think it might happen.
> In the deplorable absence of quantitative data, the argument must remain
> unresolved.
>
>

Peter,

I seem to remember you saying on this very NG that when the Virtex-2 arrived you'd be
able to play games with the DCM to get some hard data on the metastability parameters
?




Article: 39074
Subject: Re: The LUT puzzle, Iam on the way
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 31 Jan 2002 07:24:16 +0000
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> Falk Brunner wrote:
>
> >
> > Yes. But isnt a good understanding of the theory a driving force, an
> > important factor for developing better circuits? What would have happend to
> > the digital logic if there was no Boolean, Karnaugth etc.??
> > Yes, the "has 4 inputs, one output, fits in a LUT " is a enineering approach
> > that is OK,
>
> Well, as they say: "I is an engineer..."
>
> Peter Alfke

Karnaugh - what's that ? :-).

I got into digital design with the PAL/ABEL generation &, since those nice people
at Berkley supplied Expresso and Presto reduction for me, I've never done a K-map
in my life [no self-timed design]  and have rarely had to DeMorganise by hand.





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