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Messages from 39225

Article: 39225
Subject: Re: Destroying a CPLD by JTAG
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 04 Feb 2002 11:55:07 -0800
Links: << >>  << T >>  << A >>
Tim,

I doubt that shorting two outputs kills anything at all.  We have left outputs
shorted to Vcc and Ground for months with no ill effects.

Maybe ESD is to blame?  Who knows.

Austin

Tim wrote:

> Assaf wrote
>
> > Hi,
> > We have a board with a Xilinx Virtex-2 FPGA and a 9500XL CPLD on it; they are
> > chained on JTAG for programming (V-2 first, 9500 second).
> >
> > We've been happily working with this board, downloading V-2 and programming
> > the 9500, using the iMpact tool from ISE 4.1 (SP3).
> >
> > We were synthesizing the CPLD with Synplicity, fitting it with ISE and
> > programming as needed. One day, we've tried synthesizing the CPLD with XST.
> > When we've downloaded it (no errors during synthesis or fitting), the CPLD
> > didn't work.
> >
> > Since that download, we can't access the V-2 OR the CPLD with iMpact. When
> > connecting, it recognizes (correctly) only the CPLD; if we try any operation
> > on the CPLD (erasing, programming or whatever), we get a message "invalid
> > device ID".
>
> In my experience, Xilinx FPGA buffers will win most fights; I would
> guess that the PAL is toast.
>
> If you got to XST wia the WebPack Project Navigator, IMHO this tool
> is far too obscure when it ignores the UCF.  I much prefer the
> certainty of a MAKE file : "ngdbuild -uc foo.ucf ......"


Article: 39226
Subject: Re: par and carry chains not allowing manual floorplanning
From: Ray Andraka <ray@andraka.com>
Date: Mon, 04 Feb 2002 20:16:05 GMT
Links: << >>  << T >>  << A >>
carry chains have been a persistent problem in the floorplanner.  You can move
them by doing an unbind and then put them where you want.  Next time you come
into the floorplanner though, you might have to do it again as the floorplanner
seems to do weird things with the carry chains.  I've found the best way to deal
with them is to either place them completely in your code (completely includes
putting BEL constraints on them) or don't floorplan them but instead just
floorplan the registers that are presumably in the same slices and let the
mapper take care of zippering the carry logic with the FF's.

Falk Brunner wrote:

> "Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag
> news:a3mesc$2nln$1@msunews.cl.msu.edu...
> > Help!!,
> >     I am having a continuing problem with manual placing of carry chain
> > parts via floorplanner.  If I take an already placed design and try to
> move
> > parts via floorplanner, the carry chains are not allowed to be moved as
> they
> > are RPM's.  The placement is _absolutely_ horrible in some cases.  If I
> > delete the particular chain and bring it back in I get an even worse
> > placement.  I can not find a way to unbind the chains.  Xilinx support has
> a
>
> "UNBIND" is the magic word. Click the carry chain,then click right, you will
> find UNBIND in the menu (or maybe in the menu bar, not sure)
>
> --
> MfG
> Falk

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39227
Subject: Re: par and carry chains not allowing manual floorplanning
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Mon, 4 Feb 2002 15:20:15 -0500
Links: << >>  << T >>  << A >>
Falk,
Thanks, unfortunately, it doesn't work.  (That's the problem.)  Any other
ideas?
Theron


"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:a3motc$17d1vs$2@ID-84877.news.dfncis.de...
> "Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag
> news:a3mesc$2nln$1@msunews.cl.msu.edu...
> > Help!!,
> >     I am having a continuing problem with manual placing of carry chain
> > parts via floorplanner.  If I take an already placed design and try to
> move
> > parts via floorplanner, the carry chains are not allowed to be moved as
> they
> > are RPM's.  The placement is _absolutely_ horrible in some cases.  If I
> > delete the particular chain and bring it back in I get an even worse
> > placement.  I can not find a way to unbind the chains.  Xilinx support
has
> a
>
> "UNBIND" is the magic word. Click the carry chain,then click right, you
will
> find UNBIND in the menu (or maybe in the menu bar, not sure)
>
> --
> MfG
> Falk
>
>
>
>



Article: 39228
Subject: Re: JTAG Boundary Scan with the XDS510
From: Par Ligander <pali@enea.se>
Date: Mon, 04 Feb 2002 13:11:13 -0800
Links: << >>  << T >>  << A >>


rickman wrote:

> I spoke with TI support and the initial answer was the DSP porting kit.
> But I was told this was for writing your own special emulator, not for
> boundary scan. I don't know if this would help, but the DPK costs
> $10,000. Not too good for this application since I am trying to cheap
> out and reuse my existing XDS510 boards and pods.
>

It is not usefull for boundary scan anyway.


>
> I was looking back through my email I received from a post in the Yahoo!
> message boards where he forwards an email he received from TI support
> excerpted here.
>
> "For boundary scan testing, TI uses another tool. It is called Advanced
> Support System for Emulation and Test (ASSET). It is PC-Based, needs
> Windows and INCLUDES a XDS 510 card. The EMULATION in the ASSET name
> does NOT refer to DSP emulation but to emulating devices and clusters in
> general using JTAG capabilities (e.g. EXTEST). "
>
> This sounds just like what I need except for the part about including an
> XDS510. I am trying to avoid buying yet another expensive piece of
> hardware.

The software probably costs more than $10K anyway.


>
> But I will call TI about this Monday and post what I find out.
>
> I am trying hard not to become a JTAG expert, but that may be what I
> need to do.

You will probably have to become a JTAG expert. One good thing is that the
boundary usage of JTAG is standardised so there are information on how to do
that. The debug/emulation part of JTAG is proprieatary and different for each
vendor.

If you want to use the XDS510 for boundary scan you would have to:

1. Get the specs for the TBC ACT8990 chip on the XDS510 board, you can find it on
TIs website if you dig.

2. Write a driver for the XDS510 board for your host operating system. Since there
are no interrupts involed, only a few IO ports it will most likely be a very
simple driver. The drivers that TI supply have no public interfaces that can be
used for this.

3. Make an application that parses the BDSL descriptions of the chips on your
boards and execises the JTAG chain through your driver.


Someone have tried to do something similar but not with a XDS510:

http://www.rsn-tech.demon.co.uk/pjtag/pjtag.html


Good luck !

/Regards, Pär Ligander


Article: 39229
Subject: Re: Destroying a CPLD by JTAG
From: Marcin E. Hamerla <mehamerla@pro.onet.pl>
Date: Mon, 04 Feb 2002 22:15:09 +0100
Links: << >>  << T >>  << A >>
Austin Lesea napisal(a):

>I doubt that shorting two outputs kills anything at all.  We have left outputs
>shorted to Vcc and Ground for months with no ill effects.

In case of Altera shorting output to power did not kil the chip,
although it became hot. In case of Lattice shorting output to gnd
killed the chip immediatelly.

-- 
Pozdrowienia, Marcin E. Hamerla

"Nienawidze turystow."

Article: 39230
Subject: Re: Destroying a CPLD by JTAG
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 05 Feb 2002 10:17:44 +1300
Links: << >>  << T >>  << A >>
Assaf Sarfati wrote:
> 
> Hi,
> We have a board with a Xilinx Virtex-2 FPGA and a 9500XL CPLD on it; they are
> chained on JTAG for programming (V-2 first, 9500 second).
> 
> We've been happily working with this board, downloading V-2 and programming
> the 9500, using the iMpact tool from ISE 4.1 (SP3).
> 
> We were synthesizing the CPLD with Synplicity, fitting it with ISE and
> programming as needed. One day, we've tried synthesizing the CPLD with XST.
> When we've downloaded it (no errors during synthesis or fitting), the CPLD
> didn't work.
> 
> Since that download, we can't access the V-2 OR the CPLD with iMpact. When
> connecting, it recognizes (correctly) only the CPLD; if we try any operation
> on the CPLD (erasing, programming or whatever), we get a message "invalid
> device ID".
> 
> Had anyone encountered this problem? is there any solution except removing the
> CPLD and soldering a new one? (get a bigger hammer...)

 You will need a new device ... 

 Don't forget CPLD's ( unlike FPGA ), have a finite cycle count on
PGM/Erase, 
so it's possible it's simply worn out.

 Also, it is common to have the Device ID strings also in EE cells, 
but 'undocumented' in the access method. This allows vendors to 
make algortihm changes.

 We have seen this effect with Microcontrollers, where the device ID is 
accidently made invalid.

 - jg

Article: 39231
Subject: Re: Destroying a CPLD by JTAG
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 05 Feb 2002 10:29:00 +1300
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Tim,
> 
> I doubt that shorting two outputs kills anything at all.  We have left outputs
> shorted to Vcc and Ground for months with no ill effects.

 Sounds hard to believe..

 Is this CPLD outputs, that limit at ~150mA+, or less capable 
FPGA pin drivers ? ( or low Vcc tests.. )

 Do 'no ill effects' mean it still works  digitally, or do you check 
for Rds(ON) degrade, and even metal migration ?

-jg

Article: 39232
Subject: Re: RAM question
From: kayrock66@yahoo.com (Jay)
Date: 4 Feb 2002 15:08:28 -0800
Links: << >>  << T >>  << A >>
Your disappointment is not uncommon when engineers hear about the
great numbers often touted by the marketing types.  The hundreds of
megahertz numbers are acheived by careful placement and highly
pipelines designs.  Your numbers on pretty typical.

Some things you might try for speed up are to use a 4096x 12 deep
memory structure so that Coregen doesn't just replicate those muxes
you built manually in the first place hen it tries to build a non
modula 2 length structure.  It would hopefully use 3 4096x4 bit
memories.  Register everything you can.

Regards


dottavio@ised.it (Antonio) wrote in message news:<fb35ea96.0202032329.565fd310@posting.google.com>...



> In my project I'm using 3 set of values with different dimension, I
> mean 384x12 bits , 512x12 bits and 768x12 bits , to choose between
> them I could use a demux-BLOCKRAM-mux chain or to fit each of these
> block in a zero padded 1024x12 bits and use the addressing
> capabilities of a Virtex BLOCKRAM 3072x16. with very disappoint I
> found that this last solution (implemented with the CORE blockRAM
> single port) may run at a maximum of 60MHZ on a VIRTEX1000BG560-4 and
> 90MHz on
> VirtexE600-6 so my question is :
> 1) is this normal ??
> 2) when I read 300 MHz on FPGA are we talking of a flip flop ??
> 3) this is the most important question :  how can I obtain more to
> solve the same problem with
> 	the VIRTEXE600-6  ??
> 
> Thanks
> 
>    Antonio

Article: 39233
Subject: Re: solutions manuals, and no they are not for school
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 04 Feb 2002 23:13:21 +0000
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> For some, understanding of the material is bolstered by working the problems and making sure the results are
> the same as the solution.  Many times, all that is needed is to work through one or two problems to make sure
> your understanding of the material is correct.
>
>

I think its also true that when you really and truely get stuck on a text-book problem working backwards from the
answer also increases understanding at the same time as it diminishes the ego.




Article: 39234
Subject: Re: FPGA or Micro-controller in Lowpower designs?
From: kayrock66@yahoo.com (Jay)
Date: 4 Feb 2002 15:35:37 -0800
Links: << >>  << T >>  << A >>
Hi Arash,

Your design in all likelyhood could be implemented with either
technology and since so few people are competent in both disciplines,
I'd suggest you select the one fo the 2 approaches that you are most
familiar with.  Fundmentally switching CMOS transistors uses mAh's,
the less you do the better.  So if you have a small uC going fast, or
a big general FPGA going slow, you'll use acheive similar computation
and current with the advantage probably going to the uC because of its
purpose built design and lower internal capacitance.  The FPGA has the
capability of much higher computational throughput, but since your
requirements are so slow, this is no advantage to you.

Regards,
Jay

"Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:<3c5535a1$1@epflnews.epfl.ch>...
> Hi,
> 
> I'm starting a new design in which I'm using a multi-channel A/D with a low
> sampling-rate and Flash memory for the storage and the system is going to be
> powered by battery. In this stage, I'm not yet sure if using a FPGA would be
> wise, as I'm very concerned with the power consumption. The gate count of
> the circuit will be 3k~4k in my opinion so basically any medium Spartan
> family or even maybe XPLA would do. I've seen a device from ATmel (T87C5111)
> that consumes only 5mA and I guess is a good candidate too. This makes me
> hesitate to choose any FPGA over these types of micro-controller in designs
> were every bit of current matters..
> 
> Does anyone has experience in using FPGAs in low power applications and is
> there any suggestion in selection FPGAs over micros in these types of
> designs?
> 
> Regards
> Arash

Article: 39235
Subject: Re: RAM question
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 04 Feb 2002 15:44:50 -0800
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

>  the setup for ena and we are
> double the set-up times for the address and data inputs to the BRAM, and very long
> compared to other timing on the chip.  In A virtex E-6 they are 2.5 and 2.2 ns
> respectively.

Sorry, Ray, but I just looked at the data sheet on the web:
Virtex-E BlockRAM set-up times for address and data are 1.1 ns for -6, the slowest
speed grade, ( yes, Enable and WE are longer, 2.5 and 2.0 ns respectively)
For the fastest speed grade the numbers are 0.9 ns, 2.0 ns and 1.7 ns respectively.

These are data sheet numbers from  www.xilinx.com, I used nothing special...

Peter Alfke, Xilinx Applications



Article: 39236
Subject: Re: LARGE ultra low power FPGA/CPLD recommendation
From: kayrock66@yahoo.com (Jay)
Date: 4 Feb 2002 15:46:16 -0800
Links: << >>  << T >>  << A >>
As far as that standby consumption, anything except a conventional
CPLD will be in the ball park, you need something that is pure leakage
in standby.  The other thing is that your standby current consumption
will vary dramatically over temperature since CMOS leakage follows the
Einstein relationship (exponential with temperature) and to a lesser
degree over process.

Since your processing requirements are so mild, what about a uC?  You
get to use less transistors (thus less leakage) to achive the same
variety of functionality albeit at a slower rate.

Regards

p.s. Please excuse the obvious suggestion, but if you like that cool
runner part so much, could you just use 2 of them?  I know it isn't as
cute, but you'd be up and running at least.


"Dr. Michael D. Foegelle" <NOSPAM_mfoegelle@austin.rr.com> wrote in message news:<M4%68.90808$XZ1.4073857@typhoon.austin.rr.com>...
> I have a VHDL design that I need to run off of parasitic power (standby
> current draw less than 300 microamps @ 3.3V).  I had intended to use
> the Xilinx Coolrunner XPLA3, but I need the largest part (XCR3512XL)
> which Xilinx had chosen not to manufacture in the XPLA3, but will have
> samples on the Coolrunner II 512 part next August.  That's a bit late for
> my needs!  I've been looking around, but haven't found much else that
> looks like it's going to meet my standby current requirements.  I'm also
> concerned about some of these SRAM/Flash FPGAs I've looked at
> being able to handle the slow startup necessary for a parasitic power
> application.  I don't need speed (max clock speed will be 1 MHz at
> most), but I need LOW power!  And of course low active power is good
> too!  =)  Any suggestions are greatly appreciated.  Please copy any
> responses
> to my e-mail.  Remove the NOSPAM_ header to reply.
> 
> Sincerely,
> 
> Dr. Michael D. Foegelle

Article: 39237
Subject: Re: Dual ported RAM in SpartanII, output = ?????
From: kayrock66@yahoo.com (Jay)
Date: 4 Feb 2002 15:54:39 -0800
Links: << >>  << T >>  << A >>
Sometimes people add extra logic to detect when the two address are
the same and provide a deterministic result.

Something like:
if WriteAddress==ReadAddress
then ReadData<=WriteData
else
ReadData<=memory[ReadAddress]

... you get the idea

Regards
Jay


"Harjo Otten" <h.otten@rohill.geen.spam.nl> wrote in message news:<8bqd3a.j61.ln@svr004.rohill.nl>...
> A question I cannot seem to find a consistent answer for in the xilinx docs:
> 
> What's the value of an output port (e.g. port A) on a dual ported RAM block,
> when  data is written to this location through port B. Device = SpartanII
> 
> IMO it can be either the data from port B, the data that was stored at that
> location or undefined data.
> 
> In my design it doesn't really matter if it's the data from port B or the
> stored data, as long as it's not undefined. Does anybody know if the output
> goes really undefined or not ???
> 
> Thanx,
> 
> H.

Article: 39238
Subject: Re: Pin assignment on ACEX1K
From: kayrock66@yahoo.com (Jay)
Date: 4 Feb 2002 16:07:34 -0800
Links: << >>  << T >>  << A >>
With the obvious excpetion of stuff like clocks and reset, just let
your board guy pick the I/O's.  Unless you're doing something REALLY
exotic, the software will do a fine job of getting the required single
to the designated pin.  The schedule benefits will be higher that the
potential performance increase by being on a row instead of a column
I/O.

I once did a PC board from the pinout in the Altera databook.  After I
got the board back I realized that the pinout of the FPGA (10K) had
changed drastically.  With only a few cuts, I was able to make use of
that board by following a few rules:

1) I/O's connected to power traces get driven to that logic level
2) Power pins connected to the wrong polarity got cut.  You don't need
all those power pins unless you are going fast or driving high loads.
Etc...

Wasn't pretty but it worked...

Regards


"Jeroen Van den Keybus" <vdkeybus@esat.kuleuven.ac.be> wrote in message news:<1011993874.881445@seven.kulnet.kuleuven.ac.be>...
> Hello,
> 
> I want to connect an EP1K100 ACEX to a 32-bit host which will access it
> asynchronously. So there is a 32 bit data bus and a 16 bit address bus and
> some control signals (nWE, nRD, nCS). A colleague of mine will be designing
> the PCB for it and he would like to start routing asap even while the FPGA
> software is still being written. So he wants to have a complete pin
> assignment already. As a matter of fact, the FPGA software will probably
> often be rewritten on the same PCB to accomodate different lab setups.
> 
> My question: are there any guidelines regarding the pin position or should I
> rather have him (my colleague) define the pinout for easiest layout. More
> precisely, should we rather put D[0..31] and A[0..15] on column or row
> interconnects (the ACEX will be written to and read from). We'd hate to see
> the Max+2 fitter fail at the end of the month just because of stupid pin
> positions we can't change anymore.
> 
> Because of this issue we have already oversized the FPGA, normally max.
> 60-70% of the LE's will be used. But apart from EMC guidelines stating that
> 'bunching' of large groups af signals should be avoided, we have found
> nothing more on this topic.
> 
> Jeroen.

Article: 39239
Subject: Re: Flex10KA vs MAX7000S
From: kayrock66@yahoo.com (Jay)
Date: 4 Feb 2002 16:18:34 -0800
Links: << >>  << T >>  << A >>
Those 2 parts are fundamentally different achitectures, one being a
CPLD and the other an FPGA.  The CPLD is faster because it can
implement a much more complex logic function in a single level of
logic than a puny 4 input LUT based FPGA.  Also, the CPLD, due to its
small size can have faster interconnect.  Also, the macrocell is
directly connected to the I/O pad where the FPGA you have to route to
the I/O ring.  In general, the smaller the part, the faster it is, so
your 256MC CPLD is going to be pretty fast.

chrisjc31415@yahoo.co.uk (Chris Cowdery) wrote in message news:<685ae314.0201290400.789cd739@posting.google.com>...
> I've got a cut down PCI design which works nicely in a
> MAX7256SQC208-7. I have changed device to a FLEX10KA30-1 to port it to
> CardBus.
> 
> What I do not understand is why the simulation shows that the design
> on the FLEX10K part has delays of about twice that of the 7256, even
> though the flex part is a -1, and the max is a -7? Thus the timing
> becomes marginal to say the least, yet the datasheet claims PCI 33MHz
> compliance.
> 
> Any ideas?

Article: 39240
Subject: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
From: "sbf" <sfair6@home.com>
Date: Tue, 05 Feb 2002 00:54:14 GMT
Links: << >>  << T >>  << A >>
Igor -

I have seen this a couple of times.  FPGA Express tends to pass arithmetic
operators on to Altera through LPM's while Leonardo generally tries to
synthesize and optimize those structures.  The Altera LPM's have been pretty
fine tuned and are hard to beat these days (that wasn't always the case).

Look for arithmetic operators (especially multiplies & divides) and see what
block sizes Synopsys & Leonardo generate - if you want to stay with leo then
you can always generate LPM black boxes for those type functions.
Secondarily, if the design is hieararchical do a synthesis / place & route
on the lower level modules to see where the differences exist  - it's a good
way to gain insight on coding style & synthesis issues.

Steve

"Igor Peker" <vnpeker@netvision.net.il> wrote in message
news:9a4e9472.0201311500.5e7f701d@posting.google.com...
> Hi,
>
> Can anybody explain me why the same Verilog design from Synopsys FPGA
> Express is fitted by MaxPlus/Quartus into 4992 LCs of Flex10KE-100,
> but from Leonardo -
> no ?
> +: all procedures to extract ROM/RAM, etc. were made in Leo instead of
> FPGA, but Synopsys wins.
>
> Thanks in advance,
> Igor Peker



Article: 39241
Subject: Re: FPGA or Micro-controller in Lowpower designs?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 05 Feb 2002 01:04:30 GMT
Links: << >>  << T >>  << A >>
When comparing an FPGA to a DSP micro, we typically see the FPGA coming in at about 20% of the
microprocessor power for a given data rate, however that assumes that the processor is never going
into an idle state.  I have an article I wrote for EE times a few years back addressing this issue,
which is linked to from the publications page on my website.  However, at very low data rates, your
static power becomes considerably more dominant, so I wouldn't expect that 20% number to hold down
on slow end (you''ll be much closer to parity, or perhaps even less power to run the DSP).

We usually tell our customers that if it can be done with a single microprocessor, to do it there
rather than with an FPGA because the microprocessor design expertise is considerably more abundant
and cheaper than FPGA design expertise.

Jay wrote:

> Hi Arash,
>
> Your design in all likelyhood could be implemented with either
> technology and since so few people are competent in both disciplines,
> I'd suggest you select the one fo the 2 approaches that you are most
> familiar with.  Fundmentally switching CMOS transistors uses mAh's,
> the less you do the better.  So if you have a small uC going fast, or
> a big general FPGA going slow, you'll use acheive similar computation
> and current with the advantage probably going to the uC because of its
> purpose built design and lower internal capacitance.  The FPGA has the
> capability of much higher computational throughput, but since your
> requirements are so slow, this is no advantage to you.
>
> Regards,
> Jay
>
> "Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:<3c5535a1$1@epflnews.epfl.ch>...
> > Hi,
> >
> > I'm starting a new design in which I'm using a multi-channel A/D with a low
> > sampling-rate and Flash memory for the storage and the system is going to be
> > powered by battery. In this stage, I'm not yet sure if using a FPGA would be
> > wise, as I'm very concerned with the power consumption. The gate count of
> > the circuit will be 3k~4k in my opinion so basically any medium Spartan
> > family or even maybe XPLA would do. I've seen a device from ATmel (T87C5111)
> > that consumes only 5mA and I guess is a good candidate too. This makes me
> > hesitate to choose any FPGA over these types of micro-controller in designs
> > were every bit of current matters..
> >
> > Does anyone has experience in using FPGAs in low power applications and is
> > there any suggestion in selection FPGAs over micros in these types of
> > designs?
> >
> > Regards
> > Arash

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39242
Subject: Re: Destroying a CPLD by JTAG
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Tue, 5 Feb 2002 01:59:18 -0000
Links: << >>  << T >>  << A >>
Austin

"Austin Lesea" wrote

> Tim,
>
> I doubt that shorting two outputs kills anything at all.  We have left outputs
> shorted to Vcc and Ground for months with no ill effects.
>
> Maybe ESD is to blame?  Who knows.


My poor syntax.  What I meant was that I have seen FPGA outputs
effortless kill other devices when pins intended to be inputs
are programmed as outputs.

In my limited experience, the FPGA buffers can source enough
current to fry other chips.  I have done this a couple of times,
most recently to a clock generator part.





Article: 39243
Subject: Re: par and carry chains not allowing manual floorplanning
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Mon, 04 Feb 2002 21:03:48 -0500
Links: << >>  << T >>  << A >>
Problem work-around found:

The unbind can be made to work IF one disables the UCF flow during the actual
manual place phase.  Then (I hope) re-enable before saving.

Theron Hicks wrote:

> Falk,
> Thanks, unfortunately, it doesn't work.  (That's the problem.)  Any other
> ideas?
> Theron
>
> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
> news:a3motc$17d1vs$2@ID-84877.news.dfncis.de...
> > "Theron Hicks" <hicksthe@egr.msu.edu> schrieb im Newsbeitrag
> > news:a3mesc$2nln$1@msunews.cl.msu.edu...
> > > Help!!,
> > >     I am having a continuing problem with manual placing of carry chain
> > > parts via floorplanner.  If I take an already placed design and try to
> > move
> > > parts via floorplanner, the carry chains are not allowed to be moved as
> > they
> > > are RPM's.  The placement is _absolutely_ horrible in some cases.  If I
> > > delete the particular chain and bring it back in I get an even worse
> > > placement.  I can not find a way to unbind the chains.  Xilinx support
> has
> > a
> >
> > "UNBIND" is the magic word. Click the carry chain,then click right, you
> will
> > find UNBIND in the menu (or maybe in the menu bar, not sure)
> >
> > --
> > MfG
> > Falk
> >
> >
> >
> >


Article: 39244
Subject: Re: FPGA or Micro-controller in Lowpower designs?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 05 Feb 2002 15:12:53 +1300
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> When comparing an FPGA to a DSP micro, we typically see the FPGA coming in at about 20% of the
> microprocessor power for a given data rate, however that assumes that the processor is never going
> into an idle state.  I have an article I wrote for EE times a few years back addressing this issue,
> which is linked to from the publications page on my website.  However, at very low data rates, your
> static power becomes considerably more dominant, so I wouldn't expect that 20% number to hold down
> on slow end (you''ll be much closer to parity, or perhaps even less power to run the DSP).
> 
> We usually tell our customers that if it can be done with a single microprocessor, to do it there
> rather than with an FPGA because the microprocessor design expertise is considerably more abundant
> and cheaper than FPGA design expertise.

A good summary.

 Some numbers:
Current values, for 32Khz clock operation, typical used as the paceing 
element in Data loggers, are :
 Separate Clock RTC device ( eg PCF8563 )                 - < 1uA
 RTC on 3V uC, eg Cygnal C8051F3xx in 11 pin SMD package  ~ 2uA
 RTC on T87C511                                           ~ tbf ( < 10uA
? )

Operating currents, during ADC/Calculate and FLASH write can be expected
to be
a few mA, with the FLASH write energy being significant.

Average current is determined by the ratio of the two states, but can be
> 99% 
'RTC Clock only' state skewed, so the uA numbers dominate.

-jg

Article: 39245
Subject: Re: LARGE ultra low power FPGA/CPLD recommendation
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 05 Feb 2002 15:18:14 +1300
Links: << >>  << T >>  << A >>
Jay wrote:
> 
> As far as that standby consumption, anything except a conventional
> CPLD will be in the ball park, you need something that is pure leakage
> in standby.  The other thing is that your standby current consumption
> will vary dramatically over temperature since CMOS leakage follows the
> Einstein relationship (exponential with temperature) and to a lesser
> degree over process.
> 
> Since your processing requirements are so mild, what about a uC?  You
> get to use less transistors (thus less leakage) to achive the same
> variety of functionality albeit at a slower rate.
> 
> Regards
> 
> p.s. Please excuse the obvious suggestion, but if you like that cool
> runner part so much, could you just use 2 of them?  I know it isn't as
> cute, but you'd be up and running at least.

 Or, another obvious one, use a uC and a smaller CPLD, and let each
handle what they are best at. 
 We do this a lot, tho not yet at the 'power paranoid' end of the scale.

-jg

Article: 39246
Subject: Re: solutions manuals, and no they are not for school
From: bybell@rocketmail.com (Anthony J Bybell)
Date: 4 Feb 2002 18:19:43 -0800
Links: << >>  << T >>  << A >>
strut911@hotmail.com (strut911) wrote in message news:<4379d3e0.0202022112.6a731e3f@posting.google.com>...
> hi all. 
> i am wondering where one can get solutions manuals to textbooks.

http://www.bookfinder.com

It's a search engine for used bookshops--it's quite a useful site but YMMV.

-t

Article: 39247
Subject: Re: Dual ported RAM in SpartanII, output = ?????
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 04 Feb 2002 18:45:33 -0800
Links: << >>  << T >>  << A >>
I answered this last week:
The read operation is dynamic, it occurs as a result of the active clock edge.
After that, it ignores the content of the cell that has been read,

So, the simple answer is that any writing into the already read cell has no
impact on the read output.

But, there is no internal arbitration. If read and write clock edges are very
close to each other ( within a ns or two ), the read output cannot be
guaranteed, is "undefined". It could be the old, the new, or any mixture of the
two.

Hope this helps

Peter Alfke, Xilinx Applications
================================
Jay wrote:

> Sometimes people add extra logic to detect when the two address are
> the same and provide a deterministic result.
>
> Something like:
> if WriteAddress==ReadAddress
> then ReadData<=WriteData
> else
> ReadData<=memory[ReadAddress]
>
> ... you get the idea
>
> Regards
> Jay
>
> "Harjo Otten" <h.otten@rohill.geen.spam.nl> wrote in message news:<8bqd3a.j61.ln@svr004.rohill.nl>...
> > A question I cannot seem to find a consistent answer for in the xilinx docs:
> >
> > What's the value of an output port (e.g. port A) on a dual ported RAM block,
> > when  data is written to this location through port B. Device = SpartanII
> >
> > IMO it can be either the data from port B, the data that was stored at that
> > location or undefined data.
> >
> > In my design it doesn't really matter if it's the data from port B or the
> > stored data, as long as it's not undefined. Does anybody know if the output
> > goes really undefined or not ???
> >
> > Thanx,
> >
> > H.


Article: 39248
Subject: Re: FPGA or Micro-controller in Lowpower designs?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 05 Feb 2002 03:52:30 GMT
Links: << >>  << T >>  << A >>
At those low clock rates, you are well below the static power dissipation of an FPGA. This is what I
expected.  If your design will fit in a coolrunner CPLD, then you'd be in the ballpark but that doesn't
give you a whole lot of logic to work with.  If you need a custom circuit and really low power, you
should consider an ASIC.  Otherwise, you are probably best off sticking with the uP.

Jim Granville wrote:

> Ray Andraka wrote:
> >
> > When comparing an FPGA to a DSP micro, we typically see the FPGA coming in at about 20% of the
> > microprocessor power for a given data rate, however that assumes that the processor is never going
> > into an idle state.  I have an article I wrote for EE times a few years back addressing this issue,
> > which is linked to from the publications page on my website.  However, at very low data rates, your
> > static power becomes considerably more dominant, so I wouldn't expect that 20% number to hold down
> > on slow end (you''ll be much closer to parity, or perhaps even less power to run the DSP).
> >
> > We usually tell our customers that if it can be done with a single microprocessor, to do it there
> > rather than with an FPGA because the microprocessor design expertise is considerably more abundant
> > and cheaper than FPGA design expertise.
>
> A good summary.
>
>  Some numbers:
> Current values, for 32Khz clock operation, typical used as the paceing
> element in Data loggers, are :
>  Separate Clock RTC device ( eg PCF8563 )                 - < 1uA
>  RTC on 3V uC, eg Cygnal C8051F3xx in 11 pin SMD package  ~ 2uA
>  RTC on T87C511                                           ~ tbf ( < 10uA
> ? )
>
> Operating currents, during ADC/Calculate and FLASH write can be expected
> to be
> a few mA, with the FLASH write energy being significant.
>
> Average current is determined by the ratio of the two states, but can be
> > 99%
> 'RTC Clock only' state skewed, so the uA numbers dominate.
>
> -jg

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39249
Subject: Re: solutions manuals, and no they are not for school
From: steve41@totalise.co.uk (Steve)
Date: 4 Feb 2002 21:38:01 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote in message news:<3C5E97AD.D80C044E@andraka.com>...
> For some, understanding of the material is bolstered by working the problems and making sure the results are
> the same as the solution.  Many times, all that is needed is to work through one or two problems to make sure
> your understanding of the material is correct.

I agree. I normally don't feel totally comfortable until I've worked
one or two problems with some new concept. There will in almost all
areas be a text which does have answers in the back.
If he's legit then fair enough but you have to be a bit suspect about
people asking for solutions manuals on a NG. After what I saw on a
course last year nothing would surprise me about what students will do
to get out of work. He may sound legit but you'd expect him to attempt
to sound honest.

Maybe I'm too skeptical. 

Steve



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