Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 39450

Article: 39450
Subject: Re: Multiple clock domein synchronization.
From: "Kobayashi," <YQL00544@nifty.com>
Date: Mon, 11 Feb 2002 01:45:40 +0900
Links: << >>  << T >>  << A >>
I am using two different outputs of a DLL, which are CLK0 and CLK2X,
and distribute two clock domains using BUFGs( e.g. CLK0 is 100MHz, 
CLK2X is 200MHz ).
Of course the clock net loading are different. Maybe if I design the same
circuit on ASIC, I have to treat the clocks with big skew. But on FPGA
the clock routing is fixed. Can I recognize there are no skew with them?

Now I use negative edge of CLK2X for signals between the two domains 
to keep things safe. I think the circuit can run correctly even if
the skew is 1 or 2 ns. But the timing constraints become complicated
and severe. If the skew is very little, I don't have to use negative 
edge and the timing constraints become very simple.

When we use differential signals (LVDS or LVPECL) with 200MHz or 300MHz
implemented by Xilinx VertexE, I think we have to use two clocks because
VertexE doesn't have I/O multiplexer.
Or are there general method(s) which I don't know?

Thanks.

Tadashi.



Article: 39451
Subject: Re: Xilinx EDIF to BIT transation
From: Duane Clark <junkmail@junkmail.com>
Date: Sun, 10 Feb 2002 08:58:59 -0800
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> "Johann Glaser" <Johann.Glaser@gmx.at> schrieb im Newsbeitrag
> news:a45vet$1btfvn$1@ID-115042.news.dfncis.de...
>>I think I didn't depict my problem exact enough. I need _these_ tools, you
>>described. NGDBUILT, MAP, PAR, BITGEN.
>>
>>2) I'd like to have them for linux. But windows executabes (.exe-files)
>>are good enough for me, because I can use Wine (the windows emulator).
>>
> 
> No native windos version available yet.

I'm not sure what you meant by that. The Xilinx tools ngdbuild, map, 
par, bitgen, etc, are indeed all available in native windoze versions, 
and I have been running them under Linux/wine for almost 2 years. But I 
have purchased them, so I have no idea what is available for free.

Yo, Xilinx :-) Most other FPGA CAE tools are now available in Linux 
native versions, even the big guys like Synplicity, Synopsis and 
Modelsim. And even your tools run well on Linux, albeit if the user is 
willing and able to deal with wine. Linux is just a better platform for 
CAE tools than Windoze (okay, maybe that is an opinion), and I really 
think it is time for Xilinx to add official support.

Heck, Wine even has the capability to allow you to compile your Windoze 
source with the Wine libraries, and distribute that as a "Linux native" 
application. At the least, that makes for a reasonable interim solution.

(Just my periodic plea)

-- 
My real email is akamail.com@dclark (or something like that).


Article: 39452
Subject: Re: Xilinx EDIF to BIT transation
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 10 Feb 2002 17:10:47 +0000
Links: << >>  << T >>  << A >>


Falk Brunner wrote:

> "Johann Glaser" <Johann.Glaser@gmx.at> schrieb im Newsbeitrag
> news:a45vet$1btfvn$1@ID-115042.news.dfncis.de...
>
> > I think I didn't depict my problem exact enough. I need _these_ tools, you
> > described. NGDBUILT, MAP, PAR, BITGEN.
> >
> > 1) WebPack only offers them for SpartanII, I need them for Spartan (my
> > Device is XCS10).
>
> Not available in WEBPACK. You have to go for commecial software, maybe the
> student edition of foundation suports Spartan.
>

I didn't realise that. Apologies Johann. I suppose that replacing your Spartan
eval board with a more modern is out of the question ? You can get SpartanII
boards from:

http://www.xess.com
http://www.burched.com

or one of the other places listed in Falk's posting in the `Help getting
started' thread.

>
> > 2) I'd like to have them for linux. But windows executabes (.exe-files)
> > are good enough for me, because I can use Wine (the windows emulator).
>
> No native windos version available yet.
>

I expect Falk meant `Linux' instead of `windos'.

Its one of the strange phenomena of the EDA world that whereas everyone else is
bringing out their tools under Linux Xilinx consistently refuse to even consider
the idea, nor the other one of Tcl scripting.


Article: 39453
Subject: Re: Xilinx EDIF to BIT transation
From: Johann Glaser <Johann.Glaser@gmx.at>
Date: Sun, 10 Feb 2002 18:47:41 +0100
Links: << >>  << T >>  << A >>
Hi!

Thanks for all your answers!

> I didn't realise that. Apologies Johann. I suppose that replacing your
> Spartan eval board with a more modern is out of the question ? You can
> get SpartanII boards from:

Yes, I already ordered a board with a SpartanIIe on it. But it has no
experimenting things like LEDs, buttons, switches, ... Only connectors
with many pins. :-)

And: I don't want to let my current eval board (www.digilent.cc) (~ US$
140,-- for me as hobbyist is not so less :-( ) rot because of the lack of
software. And it is a nice board, I want to work a little bit with it and
get experience.

> Its one of the strange phenomena of the EDA world that whereas everyone
> else is bringing out their tools under Linux Xilinx consistently refuse
> to even consider the idea, nor the other one of Tcl scripting.

The very long task some time ago on Open Source Xilinx tools showed me
(especially the answeres of Peter), that Xilinx is thinking of Linux. They
only don't want to opensource their software. This is not important. It
would be fine, yes. Closed source but free tools for at least the things I
wrote in my postings are enough. No GUI is necessary. Only the command
line tools.

Interestingly these tools have been developed on Unix. The command line
parameters, the way they are executed, the way libraries are used and
named, directories are seperated ("/" instead of "\") ... All this
strengths my thesis. And then the Windows hype has taken place and they
went over to develop them in Windows.

I think that it would not be a big problem to natively compile at least
the low level command line tools for Linux. But this is only a thought of
me, I don't know how they are really programmed.

Using them in Linux with wine so is double the way round. :-) First a Unix
tool is converted to run on Windows. And then with wine it is again run on
Unix (Linux). :-)

But again: I am only searching the command line tools for Windows and for
free.

Bye
  Hansi

Article: 39454
Subject: Re: Xilinx EDIF to BIT transation
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 10 Feb 2002 18:49:24 +0100
Links: << >>  << T >>  << A >>
"Rick Filipkiewicz" <rick@algor.co.uk> schrieb im Newsbeitrag
news:3C66A997.F5A39BFA@algor.co.uk...
> > No native windos version available yet.
> >
>
> I expect Falk meant `Linux' instead of `windos'.

Yes, sure. Looks like I was a little bit skrewed up 8-0. And this at the end
of a relaxing weekend. Uhhhhh . . . .
Things can only get better. ;-)

Regards
Falk




Article: 39455
Subject: Xilinx XC2V6000 - cannot get anything out of jtag port
From: shparekh@yahoo.com
Date: 10 Feb 2002 10:32:31 -0800
Links: << >>  << T >>  << A >>
Hi All,

Your wisdom, 2 cents, etc. will be much appreciated.

I have a jtag chain with 5 xc18v04 plcc and a Virtex 2 XC2V6000 BF957.
 I use "Initialize Chain" in Xilinx's IMPACT.  Unfortunately, I cannot
readback anything.  Apparently, with much probing and isolating the
proms and the fpga from the jtag chain, I see that IMPACT can readback
IDCODES and get chain information from the eeproms, but cannot get
anything out of the fpga.

I am not sure why this happens.  I probed all the signals on jtag
chain going to the fpga and do not see any difference between the
signal quality on the eproms and the fpga.

I would appreciate your feedback.

Thank you.
-sanjay

Article: 39456
Subject: Re: Xilinx synthesis tools
From: Phil Hays <spampostmaster@attbi.com.com>
Date: Sun, 10 Feb 2002 18:48:44 GMT
Links: << >>  << T >>  << A >>
Tim wrote:

> > This is an interesting question, since ISE 4.2 is now working it's way
> > through the manufacturing channel.  The following excerpt is from the
> > "What's New in ISE 4.2" file on the release CD.
> 
> <snip>
> 
> > For syntax examples, see Xilinx Answer Record #13166.
> 
> How would we do that?

Amusing.  I was going to say "go to this URL and search for "13166"",  and I
(luckly) tried it before saying this.

It's not there.

13168 is there.
13165 is there.


I suspect that this a not yet released Xilinx Answer.  Sometime in the future,
try this:

http://www.xilinx.com/support/searchtd.htm

And enter 13166 into the search box.


-- 
Phil Hays

Article: 39457
Subject: Re: Multiple clock domein synchronization.
From: Ray Andraka <ray@andraka.com>
Date: Sun, 10 Feb 2002 19:47:28 GMT
Links: << >>  << T >>  << A >>
I use the clk0 in combination with the clk2x frequently.  At first blush, it
would seem that you can harmlessly shuttle signals back and forth across the
domains without being careful.  As I indicated in my earlier post however,
that is generally dangerous.  There are several factors that can each
introduce skew or jitter on one clock relative to the other.  We had a case a
while back where we were seeing a design fail due to an occasional difference
between the two clock nets of over 0.5 ns.  The DLL itself has a small range
of skews on the signals.  Loading one clock net heavily and the other lightly
adds skew.  From what we could tell though, the worst cause of the
misalignment of the clocks was caused by jitter at the clock input.  We also
noted that activity on single ended I/O pins on the same bank as a single
ended clock input added considerable jitter to the clock input.  As a result,
all of our designs now consider skew whenever signals cross between the 1x
and 2x domains.  You can use the negative clock edge, but you need to be
careful about meeting timing when you do.  We typically create a replica of
the 1x clock in the 2x clock domain by using a 2xclocked flip flop to grab
the 1x clock.  You can use that synthesized clock signal then as a CE to make
sure the transfers happen away from the active edge in the 1x domain.

"Kobayashi," wrote:

> I am using two different outputs of a DLL, which are CLK0 and CLK2X,
> and distribute two clock domains using BUFGs( e.g. CLK0 is 100MHz,
> CLK2X is 200MHz ).
> Of course the clock net loading are different. Maybe if I design the same
> circuit on ASIC, I have to treat the clocks with big skew. But on FPGA
> the clock routing is fixed. Can I recognize there are no skew with them?
>
> Now I use negative edge of CLK2X for signals between the two domains
> to keep things safe. I think the circuit can run correctly even if
> the skew is 1 or 2 ns. But the timing constraints become complicated
> and severe. If the skew is very little, I don't have to use negative
> edge and the timing constraints become very simple.
>
> When we use differential signals (LVDS or LVPECL) with 200MHz or 300MHz
> implemented by Xilinx VertexE, I think we have to use two clocks because
> VertexE doesn't have I/O multiplexer.
> Or are there general method(s) which I don't know?
>
> Thanks.
>
> Tadashi.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39458
Subject: Re: Multiple clock domein synchronization.
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 11 Feb 2002 09:09:53 +1300
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> I use the clk0 in combination with the clk2x frequently.  At first blush, it
> would seem that you can harmlessly shuttle signals back and forth across the
> domains without being careful.  As I indicated in my earlier post however,
> that is generally dangerous.  There are several factors that can each
> introduce skew or jitter on one clock relative to the other.  We had a case a
> while back where we were seeing a design fail due to an occasional difference
> between the two clock nets of over 0.5 ns.  The DLL itself has a small range
> of skews on the signals.  Loading one clock net heavily and the other lightly
> adds skew.  From what we could tell though, the worst cause of the
> misalignment of the clocks was caused by jitter at the clock input.  We also
> noted that activity on single ended I/O pins on the same bank as a single
> ended clock input added considerable jitter to the clock input.
<snip>

 Interesting comment. I have wondered about this.
 Generating a balanced OP would reduce common mode ground noise, but
ideally needs a balanced load, and balanced delays to do this. 

 Do you mean this improved by generating a balanced version of that 
I/O signal ( ie using two pins ), or did you just move the
offending signal away from the clock ip ?
 
 -jg

Article: 39459
Subject: Re: Multiple clock domein synchronization.
From: Ray Andraka <ray@andraka.com>
Date: Sun, 10 Feb 2002 22:04:12 GMT
Links: << >>  << T >>  << A >>
We solved the problem by not allowing the 2x clock FF's to change on the same edge
as the 1x FF's using CEs.  We didn't have the option of changing the I/O in the
finished design because of board constraints.  We did observe that by turning off
the I/O in the same bank as the clock input that the problem went away.  Further
experiments showed that the single ended outputs switching on the same bank as the
clock input introduced jitter in the internal clock.  I'm guessing that the di/dt
of the outputs modulated the input thresholds enough to cause the jitter.

Jim Granville wrote:

> Ray Andraka wrote:
> >
> > I use the clk0 in combination with the clk2x frequently.  At first blush, it
> > would seem that you can harmlessly shuttle signals back and forth across the
> > domains without being careful.  As I indicated in my earlier post however,
> > that is generally dangerous.  There are several factors that can each
> > introduce skew or jitter on one clock relative to the other.  We had a case a
> > while back where we were seeing a design fail due to an occasional difference
> > between the two clock nets of over 0.5 ns.  The DLL itself has a small range
> > of skews on the signals.  Loading one clock net heavily and the other lightly
> > adds skew.  From what we could tell though, the worst cause of the
> > misalignment of the clocks was caused by jitter at the clock input.  We also
> > noted that activity on single ended I/O pins on the same bank as a single
> > ended clock input added considerable jitter to the clock input.
> <snip>
>
>  Interesting comment. I have wondered about this.
>  Generating a balanced OP would reduce common mode ground noise, but
> ideally needs a balanced load, and balanced delays to do this.
>
>  Do you mean this improved by generating a balanced version of that
> I/O signal ( ie using two pins ), or did you just move the
> offending signal away from the clock ip ?
>
>  -jg

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39460
Subject: Re: par and carry chains not allowing manual floorplanning
From: Ray Andraka <ray@andraka.com>
Date: Sun, 10 Feb 2002 23:00:59 GMT
Links: << >>  << T >>  << A >>
I just tried using the 4.1 sp3 floorplanner for a Virtex (QPRO) design which has
a bunch of RPMs with RLOCs in the code.  What a disaster.  The new floorplanner
is badly screwing up the RLOC'd placement...it looks like maybe it thinks it is
trying to place a virtexII.  I tried reading an FNF from a 3.3 design, that gets
the RLOC'd design in OK, but if you try to move anything the floorplanner breaks
it again.  BTW, I have no major problems with the floorplanner on this design if
I revert back to 3.3i sp8.

I'm wondering if anyone else has seen this.  There is not even a peep about it
in the answers database (yes, I opened a case, but I don't expect to hear
anything until late tomorrow).  Sounds like a real good reason for Xilinx to
provide timing file updates for M3.3i sp8.





Theron Hicks wrote:

> Help!!,
>     I am having a continuing problem with manual placing of carry chain
> parts via floorplanner.  If I take an already placed design and try to move
> parts via floorplanner, the carry chains are not allowed to be moved as they
> are RPM's.  The placement is _absolutely_ horrible in some cases.  If I
> delete the particular chain and bring it back in I get an even worse
> placement.  I can not find a way to unbind the chains.  Xilinx support has a
> few suggestions that I cannot seem to get to work for me.
>     The one thing that I have noticed is that the carry chains are only
> screwed up at the top level of the design.  Unfortunately, if I stick in a
> dummy level above the top level, the problem persists at the origianl top
> level,  so that doesn't seem to be much help.
>     I am considering learning about rloc and similar things.  Can anyone
> recomend a good tutorial on the subject?  Or better yet a fix for the real
> problem?  I am using ise4.1 on a win2k machine.
>
> Thanks,
> Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39461
Subject: Re: par and carry chains not allowing manual floorplanning
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Sun, 10 Feb 2002 18:44:56 -0500
Links: << >>  << T >>  << A >>
Thanks,
    I am glad to know it isn't just me not knowing what is going on.  In my case I
am having trouble with _grossly_ bad placements in a SpartanII device.  Please keep
us posted on the response from Xilinx.  I will try to do the same on the case I
opened.  By the way, does 3.3 do a better job of automatically placing RPMs, etc.?

Thanks,
Theron

Ray Andraka wrote:

> I just tried using the 4.1 sp3 floorplanner for a Virtex (QPRO) design which has
> a bunch of RPMs with RLOCs in the code.  What a disaster.  The new floorplanner
> is badly screwing up the RLOC'd placement...it looks like maybe it thinks it is
> trying to place a virtexII.  I tried reading an FNF from a 3.3 design, that gets
> the RLOC'd design in OK, but if you try to move anything the floorplanner breaks
> it again.  BTW, I have no major problems with the floorplanner on this design if
> I revert back to 3.3i sp8.
>
> I'm wondering if anyone else has seen this.  There is not even a peep about it
> in the answers database (yes, I opened a case, but I don't expect to hear
> anything until late tomorrow).  Sounds like a real good reason for Xilinx to
> provide timing file updates for M3.3i sp8.
>
> Theron Hicks wrote:
>
> > Help!!,
> >     I am having a continuing problem with manual placing of carry chain
> > parts via floorplanner.  If I take an already placed design and try to move
> > parts via floorplanner, the carry chains are not allowed to be moved as they
> > are RPM's.  The placement is _absolutely_ horrible in some cases.  If I
> > delete the particular chain and bring it back in I get an even worse
> > placement.  I can not find a way to unbind the chains.  Xilinx support has a
> > few suggestions that I cannot seem to get to work for me.
> >     The one thing that I have noticed is that the carry chains are only
> > screwed up at the top level of the design.  Unfortunately, if I stick in a
> > dummy level above the top level, the problem persists at the origianl top
> > level,  so that doesn't seem to be much help.
> >     I am considering learning about rloc and similar things.  Can anyone
> > recomend a good tutorial on the subject?  Or better yet a fix for the real
> > problem?  I am using ise4.1 on a win2k machine.
> >
> > Thanks,
> > Theron Hicks
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759


Article: 39462
Subject: Re: NT parallel port driver ...Any serial NT drivers?
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Sun, 10 Feb 2002 18:47:55 -0500
Links: << >>  << T >>  << A >>
Thanks,
    I am not the programmer on the project.  I just noticed the similar need and
posted a request.  It sure sounds simple.  I will pass it on to the responsible
person

Thanks,
Theron Hicks

Alex Sherstuk wrote:

> Serial port driver is inherent to WinNT/2K.
> To access serial port from a user program you should open COM1 as a file.
> Certain control functions are necessary to set up this port properly.
>
> Here is a C++ code sample:
>
>   hComm = CreateFile(\\\\.\\COM1,
>                      GENERIC_READ | GENERIC_WRITE,
>                      0,                 // exclusive access
>                      NULL,              // no security attrs
>                      OPEN_EXISTING,
>                      FILE_ATTRIBUTE_NORMAL,
>                      NULL);
>   if (hComm == INVALID_HANDLE_VALUE)
>    {
>      SoftFault("*ERROR*-Can not open communication port %s. ERR=%u\r\n",
> nam, GetLastError());
>    }
>   COMMPROP cprop; // communications properties structure
>   if (!GetCommProperties(hComm, &cprop))
>    {
>     SoftFault("*ERROR*-Can not get properties for communication port %s.
> ERR=%u\r\n",
>                 nam, GetLastError());
>    }
>
> Regards,
>    Alex Sherstuk
>
> "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
> news:3C6414DE.C5192D11@egr.msu.edu...
> > Does any one have serial drivers for WinNT/2K?  I need to get a driver,
> etc.
> > to allow me to talk to an FPGA based device via the com ports in an NT
> > machine.
> >
> > Dave Vanden Bout wrote:
> >
> > > Rick Filipkiewicz wrote:
> > >
> > > > I'm after an WinNT/2K Parallel port driver so I can realise a Flash
> > > > based FPGA config data store.
> > > >
> > > > I'd prefer free or share ware but a modest cost wouldn't be out of the
> > > > question. Could someone point me in the right direction ?
> > >
> > > One package is the DriverLINX software and driver.  Check for it at
> > > www.sstnet.com.  We also have an installation file for it (port95nt.exe)
> > > at
> > > http://www.xess.com/ho07000.html.
> > >
> > > Another option is UNIIO.  The source for this is completely available so
> > > you
> > > can compile the parts you need.  Look for it at www.bbdsoft.com.
> > >
> > > --
> > > || Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
> > > || devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
> > > || http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||
> >


Article: 39463
Subject: Re: par and carry chains not allowing manual floorplanning
From: Ray Andraka <ray@andraka.com>
Date: Mon, 11 Feb 2002 00:59:52 GMT
Links: << >>  << T >>  << A >>
3.3 seems to run considerably faster on a floorplanned design for virtex/E.  4.1 seems
to be faster for virtexII.  As far as automatic placement, neither does a stellar job.
Personally, I find spending a day in floorplanning saves several in PAR and lets you
meet timing pretty consistently.  I'm not a fan of automatic placement because it is
sooo bad.  In this particular case (and I find in a large percentage of my designs),
the automatic placement can't even come up with a placement that works, much less one
that will meet timing.  The PAR tools don't seem to know how to move RPMs around to
make several large ones fit in even if there is plenty of room.  That, of course also
prevents using the standard Xilinx answer for many of the floorplanner issues, which
says to constrain a component from placement then move it.

"Theron Hicks (Terry)" wrote:

> Thanks,
>     I am glad to know it isn't just me not knowing what is going on.  In my case I
> am having trouble with _grossly_ bad placements in a SpartanII device.  Please keep
> us posted on the response from Xilinx.  I will try to do the same on the case I
> opened.  By the way, does 3.3 do a better job of automatically placing RPMs, etc.?
>
> Thanks,
> Theron
>
> Ray Andraka wrote:
>
> > I just tried using the 4.1 sp3 floorplanner for a Virtex (QPRO) design which has
> > a bunch of RPMs with RLOCs in the code.  What a disaster.  The new floorplanner
> > is badly screwing up the RLOC'd placement...it looks like maybe it thinks it is
> > trying to place a virtexII.  I tried reading an FNF from a 3.3 design, that gets
> > the RLOC'd design in OK, but if you try to move anything the floorplanner breaks
> > it again.  BTW, I have no major problems with the floorplanner on this design if
> > I revert back to 3.3i sp8.
> >
> > I'm wondering if anyone else has seen this.  There is not even a peep about it
> > in the answers database (yes, I opened a case, but I don't expect to hear
> > anything until late tomorrow).  Sounds like a real good reason for Xilinx to
> > provide timing file updates for M3.3i sp8.
> >
> > Theron Hicks wrote:
> >
> > > Help!!,
> > >     I am having a continuing problem with manual placing of carry chain
> > > parts via floorplanner.  If I take an already placed design and try to move
> > > parts via floorplanner, the carry chains are not allowed to be moved as they
> > > are RPM's.  The placement is _absolutely_ horrible in some cases.  If I
> > > delete the particular chain and bring it back in I get an even worse
> > > placement.  I can not find a way to unbind the chains.  Xilinx support has a
> > > few suggestions that I cannot seem to get to work for me.
> > >     The one thing that I have noticed is that the carry chains are only
> > > screwed up at the top level of the design.  Unfortunately, if I stick in a
> > > dummy level above the top level, the problem persists at the origianl top
> > > level,  so that doesn't seem to be much help.
> > >     I am considering learning about rloc and similar things.  Can anyone
> > > recomend a good tutorial on the subject?  Or better yet a fix for the real
> > > problem?  I am using ise4.1 on a win2k machine.
> > >
> > > Thanks,
> > > Theron Hicks
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39464
Subject: Re: I think it's a synthesis bug
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Mon, 11 Feb 2002 02:49:41 -0000
Links: << >>  << T >>  << A >>
I think you need to post to comp.arch.fpga (!) to get a better reply.

Looks like a bug to me.  I use the WebPack tools for PALs and they
have "Default Powerup Value of Registers" as an option under
"Implement Design".  Not that this helps you if XST has already
thrown away the flop.

BTW, there is a reset (GSR) on the XC9536, but I guess you mean that
you have not used it?

Dave Higton wrote

> I've just done a simple design on a Xilinx XC9536.  I wanted a signal
> initialised at end of configuration to 0, then set to 1 on the rising
> edge of another signal.  There is no reset input to the XC9536 - it isn't
> needed, the release from configuration does all the resetting I need.
>
> Because there's no reset line, I can't write anything in the VHDL about
> the initial state.  XST saw the setting to 1, decided that the only value
> this signal ever got was 1, and substituted a constant 1.  The real
> functionality required is very different - there would be a delay of about
> 4 minutes 30 seconds from release-from-configuration to the first rising
> edge and the resulting change from 0 to 1.
>
> I think this is a bug in synthesis.  It doesn't allow for the fact that
> there can be other things outside the VHDL that can determine values.
>
> Alternatively, it would be better if initial values could be put into
> the VHDL without requiring an explicit signal from the outside world in
> the entity declaration.
>
> What does the team think?
>
> (I solved the problem by instantiating a D-type FF from the Xilinx
> primitives library.)
>
> Dave



Article: 39465
Subject: inconsistent results after place and route on xilinx XC2V3000
From: cjwang_1225@hotmail.com (chris)
Date: 10 Feb 2002 22:44:26 -0800
Links: << >>  << T >>  << A >>
i am getting inconsistent results after my place and route of the asic
design i am prototyping. currently, i have declared all my clocks in
the static timing analyzer, and get about 97% coverage from it. the
same design is synthesized by synplicity on two different occasions. i
run it through the Xilinx Design Manager at an effort level of 5. the
problem is that only one of my runs out of about 15 multi-pass place
and routes works. the other runs exhibit different behaviors that seem
to be due to timing. the extra 3% is likely to be giving me trouble
since that area is an asynchronous portion of the circuit that is
important to its operation (clock recovery, etc...). is there a way to
make my design work consistently, assuming the code is correct? i
cannot continue to shoot blindly and pray that one run turns out okay.
can i constrain asynchronous parts of the circuit?
chris

Article: 39466
(removed)


Article: 39467
Subject: Re: Looking for Free EDIF/Verilog netlist - Schematic Viewer
From: Shing-Fat Fred Ma <fma@doe.carleton.ca>
Date: 11 Feb 2002 09:15:56 GMT
Links: << >>  << T >>  << A >>


Hi, Srinivasan,

I haven't really looked too deeply myself, but http://www.geda.seul.org/
has lotsa free stuff.

Fred

--------------------------------------------------------------------------
Fred Ma
Department of Electronics
Carleton University, Mackenzie Building
1125 Colonel By Drive
Ottawa, Ontario
Canada     K1S 5B6
fma@doe.carleton.ca
==========================================================================

Srinivasan Venkataramanan wrote:

> Hi All,
>        Trying to set up a simple design flow at home using FREE EDA
> tools, I tried using Webpack for synthesis, but after synthesis I
> couldn't see any schematics. I know that Webpack can write EDIF (but
> not quite sure how to do that - if someone knows please do let me
> know) or Verilog netlist as output, but is there any schematic viewer
> (free) for the same? After some web search I found one at
> http://www.e-tools.com/content/download.html (EStudiopro), but when I
> try to run the same, it says "License expired" - though the web page
> doesn't talk about any license for this particular product.
>
> Any links is greatly appreciated.
>
> TIA,
> Srinivasan
>
> --
> Srinivasan Venkataramanan
> ASIC Design Engineer
> Software & Silicon Systems India Pvt. Ltd. (An Intel company)
> Bangalore, India, Visit: http://www.simputer.org)
> "I don't Speak for Intel"




Article: 39468
Subject: XILINX Webpack 4.1 beginners question
From: Hartmut Schaefer <Hartmut.Schaefer@hartmut-schaefer.de>
Date: Mon, 11 Feb 2002 14:35:13 +0100
Links: << >>  << T >>  << A >>
Hi,

I recently moved from Foundation to Webpack and run into a problem which
must have a simple solution but I just can't find it.

I am using Schematic entry and put on my sheet for example one counter
using the symbol CB4CE from the SpartanII library. I add some gates to
make it a count-to-13 counter and create a symbol.
Then I create another sheet and put on it a count-to-12-counter using
again the symbol CB4CE from the library. Then I create a symbol of that
sheet.
I create a new schematic and put both defined counters in it. Then I add
some IO-Pins etc. and call it the main sheet.
If I now start synthesizing the main sheet I get the error messages:

ERROR:HDLParsers:3340 - Project file test.prj names two source files,
c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
primary unit, work/FTCE_MXILINX
ERROR:HDLParsers:3340 - Project file test.prj names two source files,
c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
primary unit, work/FTCE_MXILINX/SCHEMATIC
ERROR:HDLParsers:3340 - Project file test.prj names two source files,
c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
primary unit, work/CB4CE_MXILINX
ERROR:HDLParsers:3340 - Project file test.prj names two source files,
c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
primary unit, work/CB4CE_MXILINX/SCHEMATIC

So the synthesizer complains about FTCE (which is a part of CB4CE) and
CB4CE being defined twice. Looking in the vhf-files shows that this is
of course true (FTCE and CB4CE are definded as entity in both files).
But why is this a problem? But it can't be true that I can use a library
symbol only once in a design?

Another question by the way: Where can I find a kind of "reference
manual" for the library symbols (e.g. FTCE, CB4CE and all others)?

Last question: Am I right that with Webpack there is only one top-level
schematic file unlike Foundation, where the whole design can consist of
several sheets?

Thanks in advance

Hartmut

Article: 39469
Subject: Re: NT parallel port driver
From: "Dan Oprisan" <dandy1313@yahoo.com>
Date: Mon, 11 Feb 2002 16:11:11 +0100
Links: << >>  << T >>  << A >>
"Rick Filipkiewicz" <rick@algor.co.uk> wrote:

> I'm after an WinNT/2K Parallel port driver so I can realise a Flash
> based FPGA config data store.
>
> I'd prefer free or share ware but a modest cost wouldn't be out of the
> question. Could someone point me in the right direction ?


Check this:

http://users.skynet.be/k-net/ParPort/

bye, Dan



Article: 39470
Subject: Altera's new family Stratix
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Mon, 11 Feb 2002 16:37:56 GMT
Links: << >>  << T >>  << A >>
looks really cool. I especially like the embedded multipliers and
adders. Isn't competition great?
http://www.altera.com/products/devices/stratix/stx-index.jsp

Muzaffer Kal

http://www.dspia.com
DSP algorithm implementations for FPGA systems

Article: 39471
Subject: Sequential commands in statemachine
From: "Michael Boehnel" <boehnel@iti.tu-graz.ac.at>
Date: Mon, 11 Feb 2002 08:42:16 -0800
Links: << >>  << T >>  << A >>
Hello!

I'd like to implement a statemachine where in one state a signal, say X is analyzed (if command) and X is set afterwards according to the previous value of X.
At the moment I have 3 solutions, but I wonder if they are correct and good.

1)

   when S1=>         -- S1 is the actual state

      NS<=S2;
     
      if (x="1010") then
         do something
      else
         do something
      end if;
      x="1111"
 
   when S2=>
      -- x should be "1111" here; is this correct?
       :

        

2)
   when S1=>         -- S1 is the actual state

      NS<=S2;
     
      if (x="1010") then
         do something
         X="1111"
      else
         do something
         X="1111"
      end if;
    
 
   when S2=>
      -- x should be "1111" here; is this correct?
       :

Are 1) and 2) equivalent?

Is this possible in both ways (1 and 2) without having any timing problems after synthesis/p&r?

Is the only safe solution to include waitstates or what is better?

3) With waitstates (can get quite unreadable)

   when S1=>         -- S1 is the actual state

      NS<=S1a;
     
      if (x="1010") then
         do something        
      else
         do something       
      end if;

   when S1a=>
      NS<=S2;

 
   when S2=>
      -- x should be "1111" here; is this correct
       :

What is the standard solution for solving such a problem. Unfortunately my VHDL book don't cover state-machines of this type.

Regards,

Michael

Article: 39472
Subject: Re: Multiple clock domein synchronization.
From: "Tadashi Kobayashi" <YQL00544@nifty.com>
Date: Tue, 12 Feb 2002 01:43:20 +0900
Links: << >>  << T >>  << A >>
Thanks for your reply.
I would like to confirm your suggestion. Please look at the following using
non-proportional font.
        _________           _________           _________           _________           
CLK0   |         |_________|         |_________|         |_________|         |
       __ ___________________ ___________________ ___________________ ________
data0  __X___________________X___________________X___________________X________
        ____      ____      ____      ____      ____      ____      ____      
CLK2X  |    |____|    |____|    |____|    |____|    |____|    |____|    |____|
          _________           _________           _________           ________
CE     __|         |_________|         |_________|         |_________|        
       ____________ ___________________ ___________________ __________________
data2x ____________X___________________X___________________X__________________

The "data0" is synchronized by CLK0. The replica which you said is the
"data2x" generated from "data0" and "CE". Then we can get enough setup and
hold time even if there is the clock skew between CLK0 and CLK2X.

If the frequency of CLK2X is very high such as 266MHz, I think generating CE
becomes very difficult. Maybe when we use CLK90, it is very hard to make the
constraint meet.

I considered the following method. The "toggle0" is toggled signal
synchronized by CLK0, and the "toggle1" is copy from toggle0 using negative
edge of CLK0. Then we can generate the CE synchronized by CLK2X, using
exclusive or of toggle0 and toggle1.
         _________           _________           _________           _________           
CLK0    |         |_________|         |_________|         |_________|         |
           ___________________                     ___________________
toggle0 __|                   |___________________|                   |________
                     ___________________                     __________________
toggle1 ____________|                   |___________________|                   
         ____      ____      ____      ____      ____      ____      ____     
CLK2X   |    |____|    |____|    |____|    |____|    |____|    |____|    |____|
           _________           _________           _________           ________
CE      __|         |_________|         |_________|         |_________|        

But I think we cannot get enough hold time if CLK0 and CLK2X have some skew.
Do you know better method?

best regards,
Tadashi.





Article: 39473
Subject: Spartan Program/Verify
From: atali@cygrp.com (Aare Tali)
Date: 11 Feb 2002 09:00:59 -0800
Links: << >>  << T >>  << A >>
Hi!

I'm trying to program XC2S200E with WebPack 4.1WP2 impact and don't
understand... If I program the chip without verify, it says
programming OK. When I turn verify on, it finds 300000-400000
mismatches (same chip, same bitstream). The chip does what it is
supposed to do with my code, but still... What settings do I have to
change to get verify right?

Article: 39474
Subject: Xilinx m1map vs map
From: "Martin, Charles" <charles.w.martin@baesystems.com>
Date: Mon, 11 Feb 2002 17:06:53 GMT
Links: << >>  << T >>  << A >>

Anyone know what the behavior of 4.1.02i ISE-Alliance software is with respect to the following
executables:
%XILINX%\bin\nt\map
%XILINX%\bin\nt\m1map

I'm trying to determine the dependency utilized to determine which executable is utilized during the
mapping process. I suspect that it's device/architecture dependent, but wonder how the software
'knows' or 'decides' which executable to use.
 
+ dependant upon the device (-p switch) identified when map called
+ dependant upon the .ngd file fed into map (-p switch also thrown during ngdbuild)
+ dependant upon the device specific Synthesis output (edif) fed into ngdbuild
+ other.






Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search