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Messages from 39475

Article: 39475
Subject: Re: Sequential commands in statemachine
From: "Michael Boehnel" <boehnel@iti.tu-graz.ac.at>
Date: Mon, 11 Feb 2002 09:26:13 -0800
Links: << >>  << T >>  << A >>
I have missed a problem. What happens in the following case.

S1, E, Y, X: are all signals

when S0=> 
      CS<=S1;
      Y="0110"
   
when S1=>
   CS<=S2;
    if E="1" then
         LSB(Y)<="1"  -- not VHDL syntax, LSB=rightmost bit.
   else
         MSB(Y)<="1";
   end if;
   X<=Y;

when S2=>
      -- is X="0111" here, assuming E was "1" in the previous state?

Or are there any timing problems? VHDL gurus please don't mock me :-)

Michael

Article: 39476
Subject: Re: Altera's new family Stratix
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 11 Feb 2002 10:01:24 -0800
Links: << >>  << T >>  << A >>
Imitation is the sincerest form of flattery.

Thank you, Altera  (from all of the IC Designers here at Xilinx).

Austin



Muzaffer Kal wrote:

> looks really cool. I especially like the embedded multipliers and
> adders. Isn't competition great?
> http://www.altera.com/products/devices/stratix/stx-index.jsp
>
> Muzaffer Kal
>
> http://www.dspia.com
> DSP algorithm implementations for FPGA systems


Article: 39477
Subject: Re: XILINX Webpack 4.1 beginners question
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 11 Feb 2002 20:15:03 +0100
Links: << >>  << T >>  << A >>
"Hartmut Schaefer" <Hartmut.Schaefer@hartmut-schaefer.de> schrieb im
Newsbeitrag news:3C67C891.2455@hartmut-schaefer.de...
> If I now start synthesizing the main sheet I get the error messages:
>
> ERROR:HDLParsers:3340 - Project file test.prj names two source files,
> c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
> primary unit, work/FTCE_MXILINX

Looks like that you accidently named the two counters identical.

> But why is this a problem? But it can't be true that I can use a library
> symbol only once in a design?

No, you can use it more than one time, BUT you cant define TWO circuit with
the same name.

> Another question by the way: Where can I find a kind of "reference
> manual" for the library symbols (e.g. FTCE, CB4CE and all others)?

Its somewhere in the Online help. Can be downloaded from Xilinx.

> Last question: Am I right that with Webpack there is only one top-level
> schematic file unlike Foundation, where the whole design can consist of
> several sheets?

Not at all. The GUI does a automatic syntax and hierachy check (and sorts
the files accordingly), but you can define multiple toplevels.

--
MfG
Falk





Article: 39478
Subject: Re: Spartan Program/Verify
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 11 Feb 2002 20:19:14 +0100
Links: << >>  << T >>  << A >>
"Aare Tali" <atali@cygrp.com> schrieb im Newsbeitrag
news:a8b3964d.0202110900.387796de@posting.google.com...
> Hi!
>
> I'm trying to program XC2S200E with WebPack 4.1WP2 impact and don't
> understand... If I program the chip without verify, it says
> programming OK. When I turn verify on, it finds 300000-400000
> mismatches (same chip, same bitstream). The chip does what it is
> supposed to do with my code, but still... What settings do I have to
> change to get verify right?

Hmm, I dont know. Never did verify before. But I assume that the readback
bitstrem contains also the state of all FFs, and RAMs, and when your FPGA is
running, the states are not as on power up. I think you have to delay the
startup sequence somehow.

--
MfG
Falk





Article: 39479
Subject: Re: Altera's new family Stratix
From: Ray Andraka <ray@andraka.com>
Date: Mon, 11 Feb 2002 20:04:42 GMT
Links: << >>  << T >>  << A >>
Looks like someone at Altera has been listening to my rants about the
problems with their arithmetic mode.  They put an XOR gate in front of
the LUT to permit use as an adder-subtractor.  Likewise, the sload and
sclear are added logic to make loadable and clearable accumulators
possible in one level of logic.  How about adders with muxed or gated
inputs?  Nope, still need two levels for those.  The carry save
architecture is interesting, and should help to speed up arithmetic.
It is also interesting to note that the carry chain now goes across
rows,which should help tremendously with routing congestion in
data-flow designs (bravo).

The DSP block looks interesting.  Guess that is case of keeping up with
the Joneses.

All in all, this part looks like a huge improvement over earlier
families.  It still doesn't address the SRL16 capabilities, which I use
not only for the many small delays found in typical DSP designs, but
also to provide a capability for reloading LUT contents.  This part is
certainly usable for DSP, and closes the gap between the big 2
considerably.

Austin Lesea wrote:

> Imitation is the sincerest form of flattery.
>
> Thank you, Altera  (from all of the IC Designers here at Xilinx).
>
> Austin
>
> Muzaffer Kal wrote:
>
> > looks really cool. I especially like the embedded multipliers and
> > adders. Isn't competition great?
> > http://www.altera.com/products/devices/stratix/stx-index.jsp
> >
> > Muzaffer Kal
> >
> > http://www.dspia.com
> > DSP algorithm implementations for FPGA systems

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39480
Subject: Re: Multiple clock domein synchronization.
From: Ray Andraka <ray@andraka.com>
Date: Mon, 11 Feb 2002 20:18:31 GMT
Links: << >>  << T >>  << A >>
Keep the CE very local (use only on the interface between clock domains) and
duplicate it as needed.  You'll need to floorplan the interface as well.

capture the not 1x clock with a FF clocked on then neg edge of 2x clock, then in
adjacent slice, clock that with positive edge of 2x clock.  This creates a CE in
the 2x domain.  If it and your data path register are floorplanned, you can drive
the ce's on your data path register with that synthesized CE at the high clock
rates.  Don't try to distribute that CE all over the chip, the routing isn't fast
enough for that.  Instead, duplicate the CE circuit as needed.  You should only
need the CE for the crossing point, not for the whole circuit.


Tadashi Kobayashi wrote:

> Thanks for your reply.
> I would like to confirm your suggestion. Please look at the following using
> non-proportional font.
>         _________           _________           _________           _________
> CLK0   |         |_________|         |_________|         |_________|         |
>        __ ___________________ ___________________ ___________________ ________
> data0  __X___________________X___________________X___________________X________
>         ____      ____      ____      ____      ____      ____      ____
> CLK2X  |    |____|    |____|    |____|    |____|    |____|    |____|    |____|
>           _________           _________           _________           ________
> CE     __|         |_________|         |_________|         |_________|
>        ____________ ___________________ ___________________ __________________
> data2x ____________X___________________X___________________X__________________
>
> The "data0" is synchronized by CLK0. The replica which you said is the
> "data2x" generated from "data0" and "CE". Then we can get enough setup and
> hold time even if there is the clock skew between CLK0 and CLK2X.
>
> If the frequency of CLK2X is very high such as 266MHz, I think generating CE
> becomes very difficult. Maybe when we use CLK90, it is very hard to make the
> constraint meet.
>
> I considered the following method. The "toggle0" is toggled signal
> synchronized by CLK0, and the "toggle1" is copy from toggle0 using negative
> edge of CLK0. Then we can generate the CE synchronized by CLK2X, using
> exclusive or of toggle0 and toggle1.
>          _________           _________           _________           _________
> CLK0    |         |_________|         |_________|         |_________|         |
>            ___________________                     ___________________
> toggle0 __|                   |___________________|                   |________
>                      ___________________                     __________________
> toggle1 ____________|                   |___________________|
>          ____      ____      ____      ____      ____      ____      ____
> CLK2X   |    |____|    |____|    |____|    |____|    |____|    |____|    |____|
>            _________           _________           _________           ________
> CE      __|         |_________|         |_________|         |_________|
>
> But I think we cannot get enough hold time if CLK0 and CLK2X have some skew.
> Do you know better method?
>
> best regards,
> Tadashi.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39481
Subject: Re: XILINX Webpack 4.1 beginners question
From: Hartmut Schaefer <Hartmut.Schaefer@hartmut-schaefer.de>
Date: Mon, 11 Feb 2002 22:15:29 +0100
Links: << >>  << T >>  << A >>
Hi Falk,

> Looks like that you accidently named the two counters identical.

the counters are taken from the XILINX library, not defined by myself.
In the meantime I got an answer from XILINX that this problem will be
solved in a future edition of Webpack coming in the first week of march.

> No, you can use it more than one time, BUT you cant define TWO circuit with
> the same name.

The problem is that this is also true for the XILINX library symbols
which are not primitive cells like AND or OR or others. And so you can't
use the same libary symbol in different sheets.

> Its somewhere in the Online help. Can be downloaded from Xilinx.

Xilinx told me where to find it. If anyone else wants to know, it can be
found at:

http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm

Choose Libraries Guide.

> > Last question: Am I right that with Webpack there is only one top-level
> > schematic file unlike Foundation, where the whole design can consist of
> > several sheets?
> 
> Not at all. The GUI does a automatic syntax and hierachy check (and sorts
> the files accordingly), but you can define multiple toplevels.

But then each toplevel creates a separate configuration file. What I
meant is that with Foundation you could distribute your design over
several independent sheets, while with Webpack you have to create
symbols of all sheets and put all symbols in one single top-level sheet.

Regards
Hartmut

Article: 39482
Subject: Re: XILINX Webpack 4.1 beginners question
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Mon, 11 Feb 2002 14:22:52 -0700
Links: << >>  << T >>  << A >>
Hello Hartmut,

The HDLParsers:3340  issue has been addressed by the next release of
ISE (all versions), due out in the first week of March.  In the meantime,
you could edit the .vhf files to only include one instantiation of the
repeated
module as a workaround.

As far as a reference for library symbols, you'll want to check the
Libraries Guide in the 4.1i Software Manuals located here:
http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm

I hope this helps.

Regards,
Kamal

Hartmut Schaefer wrote:

> Hi,
>
> I recently moved from Foundation to Webpack and run into a problem which
> must have a simple solution but I just can't find it.
>
> I am using Schematic entry and put on my sheet for example one counter
> using the symbol CB4CE from the SpartanII library. I add some gates to
> make it a count-to-13 counter and create a symbol.
> Then I create another sheet and put on it a count-to-12-counter using
> again the symbol CB4CE from the library. Then I create a symbol of that
> sheet.
> I create a new schematic and put both defined counters in it. Then I add
> some IO-Pins etc. and call it the main sheet.
> If I now start synthesizing the main sheet I get the error messages:
>
> ERROR:HDLParsers:3340 - Project file test.prj names two source files,
> c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
> primary unit, work/FTCE_MXILINX
> ERROR:HDLParsers:3340 - Project file test.prj names two source files,
> c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
> primary unit, work/FTCE_MXILINX/SCHEMATIC
> ERROR:HDLParsers:3340 - Project file test.prj names two source files,
> c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
> primary unit, work/CB4CE_MXILINX
> ERROR:HDLParsers:3340 - Project file test.prj names two source files,
> c:/.../counter13.vhf and c:/.../counter12.vhf, that both define the same
> primary unit, work/CB4CE_MXILINX/SCHEMATIC
>
> So the synthesizer complains about FTCE (which is a part of CB4CE) and
> CB4CE being defined twice. Looking in the vhf-files shows that this is
> of course true (FTCE and CB4CE are definded as entity in both files).
> But why is this a problem? But it can't be true that I can use a library
> symbol only once in a design?
>
> Another question by the way: Where can I find a kind of "reference
> manual" for the library symbols (e.g. FTCE, CB4CE and all others)?
>
> Last question: Am I right that with Webpack there is only one top-level
> schematic file unlike Foundation, where the whole design can consist of
> several sheets?
>
> Thanks in advance
>
> Hartmut


Article: 39483
Subject: Re: XILINX Webpack 4.1 beginners question
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 11 Feb 2002 22:48:11 +0100
Links: << >>  << T >>  << A >>


"Hartmut Schaefer" <Hartmut.Schaefer@hartmut-schaefer.de> schrieb im
Newsbeitrag news:3C683471.5185@hartmut-schaefer.de...

> But then each toplevel creates a separate configuration file. What I
> meant is that with Foundation you could distribute your design over
> several independent sheets, while with Webpack you have to create
> symbols of all sheets and put all symbols in one single top-level sheet.

Hmm, I do VHDL only.

--
MfG
Falk





Article: 39484
Subject: Re: Altera's new family Stratix
From: John_H <johnhandwork@mail.com>
Date: Mon, 11 Feb 2002 21:49:35 GMT
Links: << >>  << T >>  << A >>
Actually, the 512 bit memory elements have a shift register mode apparantly
with the logic built in (rather than external LE-based logic).  Whether the
functionality is completely there for SRL16 replacement I haven't gotten
into.  The 512 bit rams look like a nice alternative to the CLB SelectRAMs
in my designs.  The one extra thing we now have in Brand A that Brand X
doesn't have is the big memory blocks:  512kbit (versus 18kbit or 4kbit).

And thanks for ranting and raving  :-)


Ray Andraka wrote:  [excerpt]

> All in all, this part looks like a huge improvement over earlier
> families.  It still doesn't address the SRL16 capabilities, which I use
> not only for the many small delays found in typical DSP designs, but
> also to provide a capability for reloading LUT contents.  This part is
> certainly usable for DSP, and closes the gap between the big 2
> considerably.


Article: 39485
Subject: Re: Altera's new family Stratix
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 11 Feb 2002 14:07:04 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:
> It still doesn't address the SRL16 capabilities, which I use
> not only for the many small delays found in typical DSP designs, but
> also to provide a capability for reloading LUT contents.

Do you mean that you can configure a logic element as an SRL16, load
it with bits, then reconfigure it as something other than an SRL16?
Without doing "normal" partial reconfiguration of the device?

Article: 39486
Subject: Re: Help on bus interface needed.
From: kayrock66@yahoo.com (Jay)
Date: 11 Feb 2002 14:07:37 -0800
Links: << >>  << T >>  << A >>
I think I misunderstood your configuration.  Do you have a uP chip
that you've purchased talking to your FPGA as a memory device?


Richard Meester <rme@quest-innovations.com> wrote in message news:<3C64E594.9060200@quest-innovations.com>...
> Hi Jay,
> Thanks for the response,
> 
> Jay wrote:
> 
> > I'm going to make some assumptions because I'm not sure if I
> > understand your description, correct me if I'm wrong.
> > 
> > Like you suggested, go ahead and run your internal processor at twice
> > the external interface.  Enable the data capture and data launch flops
> > on every other clock.  Clock every flip/flop in your design on the
> > higher 2X clock.
> 
> 
> What do you meen by every other clock, clock the lines, and than wait 
> one clock, and then clock again for the next complete cycle?
> 
> Don't i have a metastability problem with the asynchronous read/write/cs 
> lines
> 
> the problem is that the signal below is i.e. the r/w signal. it is 
> asynchronous. if i sample this at twice the frequency i will at 
> somepoint get the correct valie that i need to trigger on.
> 
> ---\________/------
> 
>       ^     ^        samples at one of these points at 100 Mhz.
> 	    ^ DATA must be stable at this point
> 
> However i need to have the data stable before the rising edge of this 
> signal, which is one clock cycle wide @ 100 Mhz. so i have one clock 
> cycle to put the data on the bus.
> I see how to design this, but i am worried about metastability on the 
> asynchronous lines. If i need to take care of this i need to add 2 flops 
> behind it, and after that start making the data available. Overall this 
> will take me at least 3 clock cycles.
> 
> 
> Richard
> 
> 
> 
> 
> 
> 
> 
> 
> 
> > 
> > Don't try to have a 66MHz mem interface and 100MHz internal clock. 
> > Maintain that 2/1 ratio.  Run the memory at 50 and the processor at
> > 100 or run the memory at 66, and run the processor at 133MHz.  Your
> > life will be much easier.
> > 
> > Hope this help,
> > Regards
> > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>...
> > 
> >>Hi All,
> >>
> >>I have some problems finding a good design practice for a bus-interface.
> >>
> >>We have a processor running internally at 100Mhz, and externally at
> >>50Mhz (2 internal bus cycles used for 1 complete external bus cycle).
> >>Now the addresses are set, the cs lines are set, the re_n and we_n
> >>signals are set and the data is set or read. I know all the timing
> >>variables on these lines.
> >>
> >>Now i need to design a bus interface, but i want the internal clock to
> >>run at least at 66 Mhz because i need to access ram at this speed and
> >>want to keep the internal clock speeds at the same speed.
> >>
> >>Now how can i best trigger my internal signals, the we_n line goes
> >>active low after 8 nsecs of valid data, should i use this signal and
> >>feed it into a fflop to trigger on, or should i let the flop trigger at
> >>the internal clock speed and detect that the line has changed state and
> >>take action from there, or should i make the desing completely
> >>combinatorial?
> >>
> >>Thanks in advance,
> >>
> >>Richard
> >>

Article: 39487
Subject: SRL/Logic - was Altera's new family Stratix
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Mon, 11 Feb 2002 22:10:41 -0000
Links: << >>  << T >>  << A >>

"Eric Smith" wrote
> Ray Andraka <ray@andraka.com> writes:
> > It still doesn't address the SRL16 capabilities, which I use
> > not only for the many small delays found in typical DSP designs, but
> > also to provide a capability for reloading LUT contents.
>
> Do you mean that you can configure a logic element as an SRL16, load
> it with bits, then reconfigure it as something other than an SRL16?
> Without doing "normal" partial reconfiguration of the device?

Nope. Configure as an SRL16, shift in 16 bits, then use the address inputs
to select 1-of-16, exactly as a LUT configuration selects 1-of-16.





Article: 39488
Subject: Re: Altera's new family Stratix
From: Ray Andraka <ray@andraka.com>
Date: Mon, 11 Feb 2002 23:27:03 GMT
Links: << >>  << T >>  << A >>
Not exactly.  What you can do is use an SRL16 as a loadable LUT.  If the
WE pin of an SRL16 is held low, it is indistinguishable from a LUT (except
the router is not free to permute the pins and the BX and BY pins are
blocked).  When WE is high, new 'LUT' data gets shifted in the D pin on
each clock.  What this means is that you can substitute SRL16s for LUTs in
your design to obtain LUTs that can have their contents reloaded without
having to go through any device reconfiguration.  It is real low overhead
too.  We use it in our FIR filters so that customers can reload the
coefficients without having to reconfigure, or worse pass the design
through PAR again. Our filter macros permit default coefficients at
compile time which are used to set up the INIT attributes on the SRL16's,
but then the user is free to reload the filter by shifting in new LUT
contents.  This is real handy for block adaptive filters too, not to
mention constant multipliers.

Eric Smith wrote:

> Ray Andraka <ray@andraka.com> writes:
> > It still doesn't address the SRL16 capabilities, which I use
> > not only for the many small delays found in typical DSP designs, but
> > also to provide a capability for reloading LUT contents.
>
> Do you mean that you can configure a logic element as an SRL16, load
> it with bits, then reconfigure it as something other than an SRL16?
> Without doing "normal" partial reconfiguration of the device?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39489
Subject: Re: I think it's a synthesis bug
From: Ray Andraka <ray@andraka.com>
Date: Mon, 11 Feb 2002 23:40:22 GMT
Links: << >>  << T >>  << A >>
I'm pretty sure those devices have a global reset similar to the FPGAs.  In the
FPGA the way we do it is:

process(clk,global_reset)
begin
    if global_reset='1' then
        first_time<='0';
    elsif clk'event and clk='1' then
        first_time<='1';
    end if;
end process;

--Then use the ROC component from the unisim library to connect the global-reset
up to the reset on configuration:

 POC:roc port map(global_reset);



Tim wrote:

> I think you need to post to comp.arch.fpga (!) to get a better reply.
>
> Looks like a bug to me.  I use the WebPack tools for PALs and they
> have "Default Powerup Value of Registers" as an option under
> "Implement Design".  Not that this helps you if XST has already
> thrown away the flop.
>
> BTW, there is a reset (GSR) on the XC9536, but I guess you mean that
> you have not used it?
>
> Dave Higton wrote
>
> > I've just done a simple design on a Xilinx XC9536.  I wanted a signal
> > initialised at end of configuration to 0, then set to 1 on the rising
> > edge of another signal.  There is no reset input to the XC9536 - it isn't
> > needed, the release from configuration does all the resetting I need.
> >
> > Because there's no reset line, I can't write anything in the VHDL about
> > the initial state.  XST saw the setting to 1, decided that the only value
> > this signal ever got was 1, and substituted a constant 1.  The real
> > functionality required is very different - there would be a delay of about
> > 4 minutes 30 seconds from release-from-configuration to the first rising
> > edge and the resulting change from 0 to 1.
> >
> > I think this is a bug in synthesis.  It doesn't allow for the fact that
> > there can be other things outside the VHDL that can determine values.
> >
> > Alternatively, it would be better if initial values could be put into
> > the VHDL without requiring an explicit signal from the outside world in
> > the entity declaration.
> >
> > What does the team think?
> >
> > (I solved the problem by instantiating a D-type FF from the Xilinx
> > primitives library.)
> >
> > Dave

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39490
Subject: Re: Xilinx EDIF to BIT transation
From: In Memory of tecNovia <remember@me.com>
Date: Mon, 11 Feb 2002 17:07:24 -0800
Links: << >>  << T >>  << A >>
On Sun, 10 Feb 2002 13:07:59 +0000, Rick Filipkiewicz
<rick@algor.co.uk> wrote:

--snip--
>
>I'm afraid you have the wrong end of the stick here. There is no utility the
>`converts' an EDIF file to a .bit file. By ``VHDL/Verilog Compiler'' I assume
>you mean a synthesis tool  ? If so which one ?
>
>Form then on the basic process is, roughly:
>
>o NGDBUILD takes in the EDIF(s) and produces a .ngd (= Native Generic
>Database). This is where you specify the Xilinx device family. Since you are
>using an eval board with fixed pinout you will need to specifiy this either
>here in a UCF file or at the next stage via a PCF.
>
--snip--

Thanks for the detailed description.

The EDIF file contains a reference to the part Xilinx XST was told was
the target part, which can be overcome by the ngdbuild  -p parameter.

  (comment "Reference To The Cell Of Highest Level")

  (design xilinx_wrap
    (cellref xilinx_wrap (libraryref DESIGNS))
    (property PART (string "V200E-PQ240-7"))
  )
)

My question is - is the EDIF file truly generic or is it already
family specific. To generate black_box EDIF files for other users to
take and link, do I only need one EDIF file, or do I need one for
VertexE, one for Spartan, etc?

John



Article: 39491
Subject: Re: Xilinx EDIF to BIT transation
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Feb 2002 01:28:06 GMT
Links: << >>  << T >>  << A >>
Depends if you use primitives that are unique to a particular family or not.  For
example, if your edif contains a clkdlle, then it is virtexe specific.  If it
contains only unisim primitives that are common to all families, then you have
something that will work on multiple families.  Our ultra-fast FFT core, for
example uses the same edif netlist for spartanII, virtex and virtexE.  It contains
RLOCs, so it is not compatible with VirtexII.

In Memory of tecNovia wrote:

>
> My question is - is the EDIF file truly generic or is it already
> family specific. To generate black_box EDIF files for other users to
> take and link, do I only need one EDIF file, or do I need one for
> VertexE, one for Spartan, etc?
>
> John

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39492
Subject: Re: Altera's new family Stratix
From: "Peter Ormsby" <faepete.deletethis@mediaone.net>
Date: Tue, 12 Feb 2002 03:28:58 GMT
Links: << >>  << T >>  << A >>

Austin Lesea <austin.lesea@xilinx.com> wrote in message
news:3C6806F4.C858C5C1@xilinx.com...
> Imitation is the sincerest form of flattery.
>
> Thank you, Altera  (from all of the IC Designers here at Xilinx).
>
> Austin


And I'm sure the folks at Altera that came up with Block RAMs, embedded
SerDes and LVDS, the Nios soft processor, the on-die hard-core (ARM)
processor, and the entire MAX product family would like to thank you for
your recognition of their ideas.

Let's face it, there are many good reasons why these two companies are at
the top of the programmable-logic heap.  Both have come up with some very
good ideas and both have taken ideas from the competition and improved on
them.  As Muzaffer Kal said:

"Isn't competition great?"

-Pete-



Article: 39493
Subject: Re: par and carry chains not allowing manual floorplanning
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Feb 2002 04:11:35 GMT
Links: << >>  << T >>  << A >>
Well, I got a response back.  Turns out it is a "known issue".  No word on a
work-around yet.  Fortunately, this particular design is a QPRO design, so the timing
files are listed as "final", therefore the timing from 3.3sp8 is hopefully not going to
change.  Doesn't help me though with the 2000E design I've got to revisit next week.
My thoughts are that Xilinx ought to make the updated timing files available for 3.3
immediately so that people using floorplanner with RPMs aren't in a pickle (do people
really use floorplanner without RPMs?  How tedious can that be?)

"Theron Hicks (Terry)" wrote:

> Thanks,
>     I am glad to know it isn't just me not knowing what is going on.  In my case I
> am having trouble with _grossly_ bad placements in a SpartanII device.  Please keep
> us posted on the response from Xilinx.  I will try to do the same on the case I
> opened.  By the way, does 3.3 do a better job of automatically placing RPMs, etc.?
>
> Thanks,
> Theron
>
> Ray Andraka wrote:
>
> > I just tried using the 4.1 sp3 floorplanner for a Virtex (QPRO) design which has
> > a bunch of RPMs with RLOCs in the code.  What a disaster.  The new floorplanner
> > is badly screwing up the RLOC'd placement...it looks like maybe it thinks it is
> > trying to place a virtexII.  I tried reading an FNF from a 3.3 design, that gets
> > the RLOC'd design in OK, but if you try to move anything the floorplanner breaks
> > it again.  BTW, I have no major problems with the floorplanner on this design if
> > I revert back to 3.3i sp8.
> >
> > I'm wondering if anyone else has seen this.  There is not even a peep about it
> > in the answers database (yes, I opened a case, but I don't expect to hear
> > anything until late tomorrow).  Sounds like a real good reason for Xilinx to
> > provide timing file updates for M3.3i sp8.
> >
> > Theron Hicks wrote:
> >
> > > Help!!,
> > >     I am having a continuing problem with manual placing of carry chain
> > > parts via floorplanner.  If I take an already placed design and try to move
> > > parts via floorplanner, the carry chains are not allowed to be moved as they
> > > are RPM's.  The placement is _absolutely_ horrible in some cases.  If I
> > > delete the particular chain and bring it back in I get an even worse
> > > placement.  I can not find a way to unbind the chains.  Xilinx support has a
> > > few suggestions that I cannot seem to get to work for me.
> > >     The one thing that I have noticed is that the carry chains are only
> > > screwed up at the top level of the design.  Unfortunately, if I stick in a
> > > dummy level above the top level, the problem persists at the origianl top
> > > level,  so that doesn't seem to be much help.
> > >     I am considering learning about rloc and similar things.  Can anyone
> > > recomend a good tutorial on the subject?  Or better yet a fix for the real
> > > problem?  I am using ise4.1 on a win2k machine.
> > >
> > > Thanks,
> > > Theron Hicks
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39494
Subject: Re: Spartan Program/Verify
From: David Miller <spam@quartz.net.nz>
Date: Tue, 12 Feb 2002 17:35:25 +1300
Links: << >>  << T >>  << A >>
Aare Tali wrote:

> understand... If I program the chip without verify, it says
> programming OK. When I turn verify on, it finds 300000-400000


How are you programming it?  JTAG?  SelectMAP?  Serial?

If it's jtag, then I don't know why it isn't verifying.  But, here's a 
hypothesis for you: (as Falk alluded to), the configuration port goes 
away after the FPGA goes into run mode, so the software can't read the 
bitstream back.

If you provide -g persist:yes to bitgen, I think the config port stays 
active and the reads should work.


Just an idea.



-- 
David Miller               | When something disturbs you, it isn't the
Endace Measurement Systems | thing that disturbs you; rather, it is
Mobile: +64-21-704-djm     | your judgement of it, and you have the
Fax:    +64-21-304-djm     | power to change that.  -- Marcus Aurelius


Article: 39495
Subject: Re: Altera's new family Stratix
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 11 Feb 2002 23:55:41 -0500
Links: << >>  << T >>  << A >>
I guess I didn't realize that Xilinx invented multipliers and adders. 

Thanks Xilinx.  ;)




Austin Lesea wrote:
> 
> Imitation is the sincerest form of flattery.
> 
> Thank you, Altera  (from all of the IC Designers here at Xilinx).
> 
> Austin
> 
> Muzaffer Kal wrote:
> 
> > looks really cool. I especially like the embedded multipliers and
> > adders. Isn't competition great?
> > http://www.altera.com/products/devices/stratix/stx-index.jsp
> >
> > Muzaffer Kal
> >
> > http://www.dspia.com
> > DSP algorithm implementations for FPGA systems

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39496
Subject: DONE goes high, but the device doesnt seem to "run"
From: David Miller <spam@quartz.net.nz>
Date: Tue, 12 Feb 2002 18:19:53 +1300
Links: << >>  << T >>  << A >>
Hi,

When I programme this virtexII 1000 via the JTAG chain, the FPGA 
configures and runs.  The DONE LED goes high, and the FPGA starts doing 
its job.

When I try to configure this FPGA through the SelectMAP port from ROM 
using the onboard CPLD, the DONE LED goes high, but the FPGA doesn't 
seem to "run".  Very occasionally, it will run, but mostly it doesn't.

I have looked at the config strobes, and PGM_N, CCS_N, CCLK all appear 
to do the appropriate thing.  Done goes high two cycles after the last 
pulse of CCS_N, and then the world is silent.

The bitstream I am uploading through the JTAG chain is different from 
the one programmed into the ROM, but only by the flags given to bitgen. 
  Both have DriveDone:Yes, but only the jtag version has startupclk set 
to  JTAG.

As near as I can tell, the FPGA startup sequence isn't completing, but I 
don't know why.  It's as if the startup FSM wasn't being clocked.  Yet, 
the normal bitstream has startupclk set to CCLK (according to the .bgn 
file) and CCLK is being driven by a 50 MHz oscillator.

I tried all the solutions mentioned in Answer #5865, and had no luck.  I 
  read somewhere that it is possible to delay the transition to run-mode 
by externally driving DONE low.  I measured the voltage on DONE and 
found it to be just over 3 volts, so that's not happening.

Can anyone shed some light onto this problem?


-- 
David Miller               | When something disturbs you, it isn't the
Endace Measurement Systems | thing that disturbs you; rather, it is
Mobile: +64-21-704-djm     | your judgement of it, and you have the
Fax:    +64-21-304-djm     | power to change that.  -- Marcus Aurelius


Article: 39497
Subject: Re: Altera's new family Stratix
From: Ray Andraka <ray@andraka.com>
Date: Tue, 12 Feb 2002 05:26:33 GMT
Links: << >>  << T >>  << A >>
I've been looking at this today.  There are some things that look like
they've been done right:  The big memory could be a big win in lots of
applications.  The 512 bit memories are numerous enough to use for the
small delay queues I've been harping about.  The mutlipliers, if they
really run at the 250 MHz advertised in the datasheet are quite a bit
faster than the ones in the currently available virtexII, and it looks like
they line up nicely with the LABs so you don't need to surround them with a
bunch of pipeline registers just to get the performance.  The row
architecture reduces the bit pitch to a minor issue, and it looks like it
lines up nicely with the LAB pitch.  I have been impressed by the DSP IP
Altera has been turning out over the last year or so.  It is evident that
they are very serious about getting a stake in the DSP market.  Now it
looks they'll have decent silicon to put it on.  Looks like it could be a
serious contender.

rickman wrote:

> I guess I didn't realize that Xilinx invented multipliers and adders.
>
> Thanks Xilinx.  ;)
>
> Austin Lesea wrote:
> >
> > Imitation is the sincerest form of flattery.
> >
> > Thank you, Altera  (from all of the IC Designers here at Xilinx).
> >
> > Austin
> >
> > Muzaffer Kal wrote:
> >
> > > looks really cool. I especially like the embedded multipliers and
> > > adders. Isn't competition great?
> > > http://www.altera.com/products/devices/stratix/stx-index.jsp
> > >
> > > Muzaffer Kal
> > >
> > > http://www.dspia.com
> > > DSP algorithm implementations for FPGA systems
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39498
Subject: student F2.1i printing problem
From: "Phil Curry" <pmcurry@telocity.com>
Date: Mon, 11 Feb 2002 22:09:50 -0800
Links: << >>  << T >>  << A >>
I'm trying to get my schematics to print out before the quarter ends!

I have installed Xilinx Foundation 2.1i on a Windows98 machine with an HP
932c usb direct connected printer.

When I try to print, it acts like it's printing but nothing ever shows up at
the printer or appears in the print queue. All other apps print fine.

Being a student version, I get ZERO help from Xilinx. Can anyone here give
me a suggestion?

Thanks.
-Phil
--
In theory, practice and theory are the same, but in practice they are
different


Article: 39499
Subject: Re: Help on bus interface needed.
From: Richard Meester <rme@quest-innovations.com>
Date: Tue, 12 Feb 2002 08:16:20 +0100
Links: << >>  << T >>  << A >>
Hi Jay,

Yes, we have an external CPU and external memory. We develop the FPGA to be a DMA controller and some more activity.
We have internal registers inside the FPGA which need to be addressed as a memory device. After this the FPGA can
become bus master.

What i have done now is that i clock the FPGA at 100Mhz, scan the lines and check for the appropriate signals and go
from there. I have 4 clock cycles at 100Mhz at the moment, but in future will advance to 2 clock cycles to respond.
Once the FPGA becomes a bus-master i add a pipeline stage which will allow 1 clock cycle addresses and delayed data
lines when it comes to a read. Also bus turnaround will have a 4 cycle latency. I will transfer chunks of 16/32 words
so the benefit of the pipeline is definately there. Now my problem is do i need to synchronize and concern about
metastability on the incomming lines when the FPGA is a memory device for the external processor?

Thanks,

Richard

Jay wrote:

> I think I misunderstood your configuration.  Do you have a uP chip
> that you've purchased talking to your FPGA as a memory device?
>
> Richard Meester <rme@quest-innovations.com> wrote in message news:<3C64E594.9060200@quest-innovations.com>...
> > Hi Jay,
> > Thanks for the response,
> >
> > Jay wrote:
> >
> > > I'm going to make some assumptions because I'm not sure if I
> > > understand your description, correct me if I'm wrong.
> > >
> > > Like you suggested, go ahead and run your internal processor at twice
> > > the external interface.  Enable the data capture and data launch flops
> > > on every other clock.  Clock every flip/flop in your design on the
> > > higher 2X clock.
> >
> >
> > What do you meen by every other clock, clock the lines, and than wait
> > one clock, and then clock again for the next complete cycle?
> >
> > Don't i have a metastability problem with the asynchronous read/write/cs
> > lines
> >
> > the problem is that the signal below is i.e. the r/w signal. it is
> > asynchronous. if i sample this at twice the frequency i will at
> > somepoint get the correct valie that i need to trigger on.
> >
> > ---\________/------
> >
> >       ^     ^        samples at one of these points at 100 Mhz.
> >           ^ DATA must be stable at this point
> >
> > However i need to have the data stable before the rising edge of this
> > signal, which is one clock cycle wide @ 100 Mhz. so i have one clock
> > cycle to put the data on the bus.
> > I see how to design this, but i am worried about metastability on the
> > asynchronous lines. If i need to take care of this i need to add 2 flops
> > behind it, and after that start making the data available. Overall this
> > will take me at least 3 clock cycles.
> >
> >
> > Richard
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > >
> > > Don't try to have a 66MHz mem interface and 100MHz internal clock.
> > > Maintain that 2/1 ratio.  Run the memory at 50 and the processor at
> > > 100 or run the memory at 66, and run the processor at 133MHz.  Your
> > > life will be much easier.
> > >
> > > Hope this help,
> > > Regards
> > > Richard Meester <rme@quest-innovations.com> wrote in message news:<3C63F9C2.6CBF3BE7@quest-innovations.com>...
> > >
> > >>Hi All,
> > >>
> > >>I have some problems finding a good design practice for a bus-interface.
> > >>
> > >>We have a processor running internally at 100Mhz, and externally at
> > >>50Mhz (2 internal bus cycles used for 1 complete external bus cycle).
> > >>Now the addresses are set, the cs lines are set, the re_n and we_n
> > >>signals are set and the data is set or read. I know all the timing
> > >>variables on these lines.
> > >>
> > >>Now i need to design a bus interface, but i want the internal clock to
> > >>run at least at 66 Mhz because i need to access ram at this speed and
> > >>want to keep the internal clock speeds at the same speed.
> > >>
> > >>Now how can i best trigger my internal signals, the we_n line goes
> > >>active low after 8 nsecs of valid data, should i use this signal and
> > >>feed it into a fflop to trigger on, or should i let the flop trigger at
> > >>the internal clock speed and detect that the line has changed state and
> > >>take action from there, or should i make the desing completely
> > >>combinatorial?
> > >>
> > >>Thanks in advance,
> > >>
> > >>Richard
> > >>

--


Quest Innovations
tel: +31 (0) 227 604046
fax: +31 (0) 227 604053
http://www.quest-innovations.com





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