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Messages from 39575

Article: 39575
Subject: Re: Altera's new family Stratix
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 13 Feb 2002 21:12:18 +0100
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag
news:3C6990D5.28C06D67@xilinx.com...
> "Kunde passen auf."
>
> Oder wie sie sagen in Rom:
>
> Caveat Emptor.
>
> Austin
>
> (Ich kann Deutschen lesen, Danke)

;-))))

Some people sometime miss the fact, that german lost the vote for the
american language by just one vote. . . . .

--
MfG
Falk





Article: 39576
Subject: Re: RAM CORE settings for maximum speed
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Wed, 13 Feb 2002 21:21:52 +0100
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
news:3C6A719D.1E7A3E0F@andraka.com...
> for 4K deep, it should be using 12 BRAMs arranged as 4Kx1 bit slices.
> Just verify that it is doing that and not something silly with muxes.  The
> XCV***-4 parts' BRAM maxes out at about 125 MHz, but to get there you need
> to put pipeline registers immediately before and after all the signals in
> and out of the RAM.  The worst timing is on the ENA and WE inputs.  These
> two really need a duplicated flip-flop driving them and located
> immediately adjacent to the BRAM (1 FF per BRAM). Check your timing reprot
> for the worst case paths.  dollars to donuts the WE and/or ENA paths are
> among the worst.  Also, you should probably duplicate the address
> generators, especially if you have not located all the RAMs close
> together.  One last thing, the automatic place and route does a lousy job
> at placing the BRAMs,  use the floorplanner to place the RAMs close
> together and to place the pipeline registers adjacent to the BRAMs.

Arnt you getting tired of repeating over and over again this BRAM issue? I
think this is a VERY good entry for the FPGA FAQ, isnt it?

--
MfG
Falk





Article: 39577
Subject: Re: Is Leonardo spectrum OEM version for Altera limited?
From: "Paul" <nospam@nospamplease.com>
Date: Wed, 13 Feb 2002 20:46:30 -0000
Links: << >>  << T >>  << A >>
> > I have found while using Leonardo spectrum and Baseline for an Altera
design
> > that when I get to 10-15K gates the design leaves bits out of the
synthesis.
> > I have had this sort of behaviour with Actel licenses where they have a
gate
> > limit. I can't seem to get anyone at Altera or exemplar to be able to
tell
> > me absolutely if the free baseline, Leonardo version is gate limited.
>
> They are separate releases so it's reasonable to
> asuume that the bug set is also different.
>
> Since the full version costs big bucks, it's
> also reasonable to assume that something
> is left out of the Altera-oem version.
>
> One thing the Altera version does have
> is support for both VHDL and Verilog
> in the same design. This is a high-cost
> option in the full version of leo.

Altera state that the Leonardo supplied is equivalent to a full Leonardo
level 1 release but is single vendor only.

I haven't (yet) had any problems (that I know of) with synthesis with about
30% of a 20KE600 filled.
I'm using Leonardo 2001.1d with Quartus 2 1.1 SP2 for place/route.

YMMV

Paul



Article: 39578
Subject: Re: NT parallel port driver
From: "Robert Abiad" <abiad@ssl._deletethis_.berkeley.edu>
Date: Wed, 13 Feb 2002 13:04:26 -0800
Links: << >>  << T >>  << A >>
My favorite driver is:

http://www.eivd.ch/iai/projet/mmp.htm

This one comes with instructions and samples for VC++ and Borland and
Delphi.  For some reason, the others never seemed as simple or clear.

-robert

"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
news:3C63F908.4E013FFD@algor.co.uk...
> I'm after an WinNT/2K Parallel port driver so I can realise a Flash
> based FPGA config data store.
>
> I'd prefer free or share ware but a modest cost wouldn't be out of the
> question. Could someone point me in the right direction ?
>



Article: 39579
Subject: Problem with Lattice Design Expert Starter
From: "Gunther May" <g.may@tu-bs.de>
Date: Wed, 13 Feb 2002 22:15:52 +0100
Links: << >>  << T >>  << A >>
Dear FPGA experts,

I tried building a small design with the Lattice Design Expert Starter 8.4.
While compiling, an error occurs; I really do not know why.

Part of the log file:
---------------------------
Checking design rules...
Selected part is 'ispLSI1032EA-100LT100'
32513 WARNING: Net 'GND' is floating

Reading hardmacro 'C:\ISPTOOLS\ISPCOMP\macro\cbd18'...
32015 INTERNAL ERROR: Primitive 'GND' is invalid

Logical LAF reading and translation completed with errors
---------------------------

Does anyone have an idea why this error occurs?

Thank you,
Gunther



Article: 39580
Subject: Re: Xilinx synthesis tools
From: "Edwin Bland" <edwinb@in-inc.com>
Date: Wed, 13 Feb 2002 21:37:01 GMT
Links: << >>  << T >>  << A >>
I have an 8051 core that I've been able to compile cleanly under ModelSim
4.1 (WebPack4.1).   However, when I try to synthesize it with the Webpack
Tools (for the Spartan 2) it's not successful.  It goes through the first
pass successfully.  On the second pass it goes through 95% of completion &
then reports a XST module that is reportedly unaccessable & aborts.   Does
anyone know if perhaps this is related to the way the code is written or
perhaps this is a bug with the XST Synthesizer?  I haven't tried Synopsis
tools yet.  I will try using Lattice tools for their part lines.  I'd be
happy to post the source for the core if someone can help with this issue.

Thanks,

Edwin Bland, EE

"Arvin Patel" <apatel@chello.no> wrote in message
news:wkzo2nu1v1.fsf@chello.no...
> thomas.stanka@tesat.de (Thomas Stanka) writes:
>
> > Hi all,
> >
> > Arvin Patel <apatel@chello.no> wrote:
> >
> > > Does anyone have any experience with the latest version of
> > > Xilinx XST? I would be interested in any comments on stability
> > > of the tool and of the quality of results.
> >
> > Interessting point. We do the same test (as all abround the world I
guess)
> > since  FE-lizence is no longer included in Xilinx. I will post, wehn we
> > have results.
> >
> > > Does anyone have any comparisons of XST and Synopsys FPGA Express?
> > > I have made some tests and it seems that XST gives slightly
> > > better timing results than FPGA Express.
> >
> > Do you mean after PAR your bitfile is faster, or is it just, that you
get
> > better timing values after synthesis which results in equivalent results
> > after PAR?
> >
> > bye Thomas
> >
> > --
> > Thomas Stanka TE/EMD4
> > Space Communications Systems
> > Tesat Spacecom GmbH & Co KG
> > thomas.stanka@tesat.de
>
>
> Actually we obtained better results after PAR (I don't regard the FE
timing
> report as very a good estimate). In one case almost 30% improvement.
>
> Arvin



Article: 39581
Subject: Re: Altera's new family Stratix
From: "Jim Kearney" <jim@no.spam.please.com>
Date: Wed, 13 Feb 2002 21:45:28 GMT
Links: << >>  << T >>  << A >>
> Some people sometime miss the fact, that german lost the vote for the
> american language by just one vote. . . . .

A lot of people in Germany tried to tell me this story when I lived there,
aber die Geschichte ist einfach nicht wahr.  Here's an excerpt from The
Straight Dope:

"... switching to a language other than English, but it's not known how
serious this was--probably not very.   Nonetheless there's a 150-year-old
legend that English was almost replaced, not by Hebrew but by German.
Supposedly it lost by one vote, cast by a German-speaking Lutheran minister
named Frederick Muhlenberg. Some say the vote took place in the Pennsylvania
legislature and that Muhlenberg voted against it because he didn't want
Pennsylvania to be isolated from the rest of the nation. Another version,
commonly heard in Germany, says the proposal would have passed except that a
German-speaking legislator went to the toilet at the crucial moment.
It never happened, of course. In the 18th century German speakers
constituted a significant fraction of the population only in Pennsylvania
(remember the Pennsylvania Dutch?), and even the most fanatical British
haters weren't crazy enough to think they could change the national language
by legislative fiat. But the story isn't pure invention. Here's what really
happened, courtesy of Dennis Baron, professor of English at the University
of Illinois at Urbana-Champaign:

In 1794 a group of German speakers in Virginia petitioned Congress to
publish federal laws in German as well as English. The intention was not to
supplant English but simply to supplement it. A House committee recommended
publishing German translations of the laws, but on January 13, 1795, "a vote
to adjourn and sit again on the recommendation" (apparently an attempt to
keep the measure alive rather than killing it immediately) failed by a vote
of 42-41. Frederick Muhlenberg (1750-1801) was in fact Speaker of the House
at the time, but how he voted is unknown. Tradition has it that he stepped
down to cast a negative vote, apparently being the German-speaking
equivalent of an Oreo. Not that it mattered. The vote was merely procedural;
its success would not have guaranteed passage of the measure, and in any
case German translations of federal statutes are a far cry from making the
German the official language of the U.S. A similar measure came up a month
later and was also voted down, as were subsequent attempts in later years.

The Muhlenberg story was widely publicized by Franz Loher in his 1847
History and Achievements of the Germans in America. He wrongly set the event
in the Pennsylvania legislature, over which Muhlenberg had previously
presided, and also wrongly claimed that Muhlenberg was reviled by his fellow
German speakers for selling them out. Germans did get on Muhlenberg's case
for later casting the deciding vote in favor of the Jay Treaty, which was
viewed as anti-German; his brother-in-law stabbed him and he lost the next
election in 1796. Loher conflated this genuine controversy with the trivial
language debate and the legend has survived ever since.

The truth is that the U.S. has never had an official language. Several
states have declared English official at one time or another, most recently
in response to the influx of Spanish speakers. The so-called English
Language Amendment (ELA) to the U.S. Constitution, which would give English
official status, has been before Congress since 1981, and given the
country's sour mood it may yet pass. But even if one concedes the usefulness
of a common language in unifying the country, one might as well attempt to
legislate the weather."




Article: 39582
Subject: Re: Problem with Lattice Design Expert Starter
From: "Speedy Zero Two" <david@manorsway.freeserve.co.uk>
Date: Wed, 13 Feb 2002 22:25:23 -0000
Links: << >>  << T >>  << A >>
Dump Lattice and download Xilinx webpack,

Dave

<Bandwidth Snip>



Article: 39583
Subject: Re: Pseudorandom Bitstream
From: Stromeko@nexgo.de (Achim Gratz)
Date: 13 Feb 2002 14:35:04 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote
> Problem is the xilinx tools will not change a netlist consisting of only primitives.  The fix
> has to be in the synthesis tool so that it instantiates FF's instead of SRL16s.  You can force
> the issue by putting a reset on your shift register, since the SRL16 has no reset.  I think
> there may be a syn_register_style attribute in some tools that can be used to prevent inference
> of an SRL16.

There is a global switch that prevents SRL16's to be inferred. That
fixes the problem of the wrong timing report and creates a new one,
CLB usage. I'll try the attribute route later, but the same goes for
that. As for fixing the problem with at the source with a proper
timing constraint on WE of the SRL: I can see the net for each SRL16
WE in the floorplanner, but I can't get at it in the Timing Analyzer
nor the Constraints editor. The files that may contain the timing
information are binary. :-(

> That is because it is  expecting a bit vector.  Casting only works for closely related types.
> Use  the to_unsigned function:
> 
> unsigned_signal <= (others=>'0');
> unsigned_signal<= to_unsigned(10,bits);

Many thanks. All things I tried and that one didn't come to my mind
...

Mike Treseler <mike.treseler@flukenetworks.com> wrote in message 
> It's not much more work to say:
>  unsigned_signal <= (unsigned_signal'range => '0');
>  -- works like a charm and intent is clear.

Thanks to you, too. I knew the multiplication was a hack, but I'm
still trying to wrap my head around VHDL ...

Achim Gratz.

Article: 39584
Subject: Atmel CPLD chip design software?
From: c_oflynn@yahoo.com (Colin O'Flynn)
Date: 13 Feb 2002 14:38:42 -0800
Links: << >>  << T >>  << A >>
Hi,

  I've been playing around with Atmel CPLD's and wondered what other
people are using to do the design work? Atmel provides a free copy of
WinCupl, which is CUPL development language. Is there anyhthing along
the lines of VHDL that Atmel provides? There is ProChip designer, but
that software costs $1000. They say that you 'could qualify' for a
free edition, but so far I haven't been able to ;)

   Thanks,

      -Colin

Article: 39585
Subject: Re: Atmel CPLD chip design software?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 14 Feb 2002 12:02:05 +1300
Links: << >>  << T >>  << A >>
Colin O'Flynn wrote:
> 
> Hi,
> 
>   I've been playing around with Atmel CPLD's and wondered what other
> people are using to do the design work? Atmel provides a free copy of
> WinCupl, which is CUPL development language. Is there anyhthing along
> the lines of VHDL that Atmel provides? There is ProChip designer, but
> that software costs $1000. They say that you 'could qualify' for a
> free edition, but so far I haven't been able to ;)

 We use WinCUPL, in a 'Programmers Editor mode' - ie using a std
Win editor, also used for uC compiler work.
 This supports 100% of Atmels PLDs.

 VHDL flows get tricky for PLD's without EDIF fitters 
( 20-24 pin devices, ATF2500 ), and also have less connection with 
the underlying PLD - both a good and bad thing.

 For smaller designs, up to maybe 128 macrocells, WinCUPL handles it
very well. For large FPGA designs, VHDL is better.

-jg

-- 
======= 80x51 Tools & IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 39586
Subject: Re: Xilinx synthesis tools
From: David Dye <davidd@xilinx.com>
Date: Wed, 13 Feb 2002 16:09:30 -0700
Links: << >>  << T >>  << A >>
This solution was announced a little prematurely by John.  It will become
available after the release of the 4.2i software at the end of this month.

thanks,
david.


Phil Hays wrote:

> Tim wrote:
>
> > > This is an interesting question, since ISE 4.2 is now working it's way
> > > through the manufacturing channel.  The following excerpt is from the
> > > "What's New in ISE 4.2" file on the release CD.
> >
> > <snip>
> >
> > > For syntax examples, see Xilinx Answer Record #13166.
> >
> > How would we do that?
>
> Amusing.  I was going to say "go to this URL and search for "13166"",  and I
> (luckly) tried it before saying this.
>
> It's not there.
>
> 13168 is there.
> 13165 is there.
>
> I suspect that this a not yet released Xilinx Answer.  Sometime in the future,
> try this:
>
> http://www.xilinx.com/support/searchtd.htm
>
> And enter 13166 into the search box.
>
> --
> Phil Hays


Article: 39587
Subject: Re: Making Altera development quicker
From: vitaliyt@xillix.com (Vitaliy Tkachenko)
Date: 13 Feb 2002 16:22:06 -0800
Links: << >>  << T >>  << A >>
Modelsim Altera is a desent tool, but it's slooooow. Though doesn't
have limitations of the Xilinx edition on size of design.
Modelsim SE gives tenfold performance increase (on my design).
Modelsim PE is two times slower than SE.
Aldec HDL 4.2 is 3-4 times slower than Modelsim PE (again on my
design), but still faster than Modelsim Altera.
That time I used a PIII 700 MHz machine with 640 MB of 100 MHz SDRAM. 

AMD Athlon XP1900+ (Clock frequency 1600 MHz) with 1GB of 266 MHz DDR
SDRAM is three times faster than the old PIII machine.

Active HDL 5.1 gave me 30% improvement comparing to Ver 4.2. And may
be SP#2 can give some gain in simulation time.


"Paul" <nospam@nospamplease.com> wrote in message news:<5oea8.38440$as2.6235376@news6-win.server.ntlworld.com>...
> "Jay" <kayrock66@yahoo.com> wrote in message
> news:d049f91b.0202121027.11f52c8e@posting.google.com...
> > To play the devil's avocado a little bit here...  Regarding the dual
> > processor thing.  I wish it weren't true, but all the EDA software
> > I've used on the PC is single threaded.
> 
> I agree to a certain extent, but don't you find that when a simulation etc
> is underway the machine feels extremely sluggish. Having that extra CPU to
> do other things isn't a great performance boost, but it allows the user a
> more responsive machine for other tasks.
> 
> I do however agree with the problem of tasks hopping processor to processor
> as this is often a problem with high-performance games that actually run
> slower on a dual procesor machine.
> 
> On Intel MP boards the CPUs do indeed share the same memory bus, but the
> dual processor Athlon MPs have separate full buses to alleviate memory
> problems to a large extent.
> 
> I think though that your point that the second processor may not give many
> advantages is a valid one unless software deliberately makes use of it. Its
> a 300 gamble I was willing to take, but wouldn't have if Xeons were my only
> choice as the cost differential would have been considerably higher.
> 
> Paul
> 
> PS Thanks to everyone who's given their thoughts here. Most useful.
> 
> In the end I'm hoping that I can utilise ActiveHDL to significantly reduce
> my simulation bottleneck.

Article: 39588
Subject: Re: Problem with Lattice Design Expert Starter
From: mikeandmax@aol.com (Mikeandmax)
Date: 14 Feb 2002 00:56:20 GMT
Links: << >>  << T >>  << A >>
Dave so eloquently stated-
>
>Dump Lattice and download Xilinx webpack,
>
>Dave
>
but not much help for Gunther now, is it.
Sounds like you are using the schematic editor, and perhaps have a floating net
or a signal you named ground?  You should be able to reach a local Lattice FAE,
or perhaps email the problem file to techsupport@latticesemi.com
I would guess this is better than a sharp kick in the head, Dave

Michael Thomas
Lattice FAE NY


Article: 39589
Subject: Re: Is Leonardo spectrum OEM version for Altera limited?
From: kayrock66@yahoo.com (Jay)
Date: 13 Feb 2002 18:22:26 -0800
Links: << >>  << T >>  << A >>
Sounds more like a bug than a gate limit.  Report it as a bug along
with associated files, that usually gets their attention.


"Leon de Boer" <ldeboer@iprimus.com.au> wrote in message news:<3c6a780f$1_1@news.iprimus.com.au>...
> I have found while using Leonardo spectrum and Baseline for an Altera design
> that when I get to 10-15K gates the design leaves bits out of the synthesis.
> I have had this sort of behaviour with Actel licenses where they have a gate
> limit. I can't seem to get anyone at Altera or exemplar to be able to tell
> me absolutely if the free baseline, Leonardo version is gate limited. Does
> anyone know?
> 
> Regards Leon

Article: 39590
Subject: Re: Altera's new family Stratix
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 13 Feb 2002 21:31:59 -0500
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Rick,
> 
> Seriously, we didn't invent them, we just placed them in a fabric, and
> supported them in the FPGA.  And as it turns out, you can get a patent for
> just that kind of assembly of non patentable items arranged in a new or
> novel way together to perform an improved function.  Altera, and we have
> lots of patents, and now that the legal hassling is over, we can apply all
> of our efforts to supplying our customers with the best possible products.
> 
> I appeciate all of the comments, and it is absolutely critical that Xilinx
> listen to customers, because that is what we did with Virtex, and Virtex II
> (and are still doing).
> 
> No time to fiddle around, I have the next two product generations to help
> design, document, and support.
> 
> Austin

Be careful what you ask for, because you might just get it. You asked
for my input, so here it is.

I am not a high speed data/telecom vendor and I don't do gigabit IO. I
use FPGAs for general purpose system "glue" and data movement
operations. There is sometimes a little DSP thrown in for good measure. 

As it turns out, the single biggest limitation in FPGAs that I am facing
is software. I need to be able to design a modular set of interfaces
that can be loaded into the chip in different combinations at run time.
There is no PC and no platform to run tools such as JBITS. There is a
small micro and a sizable hunk of Flash memory. If I could store a dozen
interchangable pieces that can be loaded into an FPGA in different
combinations, it would save me from having to design perhaps as many as
hundreds of different complete designs as distinct bit files. 

Any progress in this area? Not much point in making the chips bigger and
bigger if your software doesn't keep up.


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39591
Subject: What do the Spartan-II Global Clock delay binary values for 66MHz PCI
From: Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com>
Date: Wed, 13 Feb 2002 21:03:46 -0600
Links: << >>  << T >>  << A >>
        I will like to know if someone reading this posting knows what
the Xilinx BITGEN Global Clock delay option's binary values mean.
According to LogiCORE PCI Implementation Guide 3.0 Page 2-12, Xilinx
requires most 66MHz PCI design to add additional delay on global clock
buffer to meet 66MHz PCI's harsh Tsu < 3ns setup time.
However, the Implementation Guide doesn't mention what values should be
entered, and even the manual for BITGEN doesn't discuss the meaning of
the binary values.
According to the Implementation Guide, the release note of LogiCORE PCI
or the associated UCF file discusses it, but I have no intention of
obtaining a license for LogiCORE PCI because I already developed my own
PCI IP core.
The device I am targeting current is Spartan-II XC2S150-6CPQ208 just
because normally I target the slower Speed Grade -5 part, but I am aware
that a Fine Pitch BGA package version may be needed for 66MHz PCI
because of ground bounce concern of a PQFP package.
        To tell you the truth, I don't have to get my PCI IP core to be
able to meet 66MHz PCI timings (Now 5V 33MHz PCI is easy for my PCI IP
core + XC2S150-5CPQ208 after some floorplanning), but I will like to
know the meaning of the Global Clock delay values just for my curiosity.
Some people reading this posting may have thought of the Xilinx's
mysterious and infamous (Infamous because it is a secret feature.)
PCILOGIC or some people call it "The secret IRDY and TRDY pins or box",
but following the suggestions of some people who experimented with it in
the past, I figured out a way to attach PCILOGIC to my PCI IP core for
ISE WebPACK 4.1 + XST design flow.
I did Post P&R simulation of my PCI IP core with PCILOGIC attached, and
the design worked absolutely fine during simulation, but I haven't
tested the design in a real system yet.
I must say that PCILOGIC is sort of a mixed bag because the IRDY and
TRDY input's propagation delay are pretty large (Around 1.3ns for Speed
Grade -6 and 1.609ns for Speed Grade -5.) compared to the regular
4-input or 5-input LUTs.
Perhaps the value of PCILOGIC may be the rumored PCI_CE dedicated CE
(Clock Enable) routing, but ISE WebPACK 4.1 doesn't come with FPGA
Editor, so I have no way of confirming that.
        Normally, I prefer not receiving replies to my E-mail account
directly, and prefer getting replies posted to the newsgroup because
that way other people who are having similar problems can search through
Google Groups to find past articles.
However, if you know the meaning of the Global Clock delay values, but
don't want to post it to the newsgroup perhaps because you fear
retaliation from Xilinx disclosing this secret feature, you can E-mail
me the information (Of course, remove the two "ihatespam" strings.).
Once the information is E-mailed to me, I will post the information ot
the newsgroup, although I will never reveal who gave me the information.
Also, if there are those who want to know how PCILOGIC works, and how it
can be used in a PCI IP core, I can post a Verilog code sample that
works with ISE WebPACK 4.1 + XST.



Thanks,



Kevin Brace (If you know what the Global Clock delay binary values mean,
E-mail it to me at "ihatespamkevinbraceusenet@ihatespamhotmail.com"
without the two "ihatespam" strings.)

Article: 39592
Subject: SpartanXL & VHDL -- free software?
From: "Paul Taylor" <p.taylor@ukonline.co.uk>
Date: Thu, 14 Feb 2002 04:24:01 -0000
Links: << >>  << T >>  << A >>
Hello.

About 18 months ago, I etched a PCB for a XCS30XL-4TQ144C
header board. I now want to use it to start teaching myself VHDL,
but WebPACK doesn't support the SpartanXL. Is there a free version
of Foundation with VHDL available for playing with this?

TIA, Paul.



Article: 39593
Subject: Does anybody have the Xilinx Foundation Series 2.1i newest not locked license.dat file?
From: "Albert Wang" <wagain@21cn.com>
Date: Thu, 14 Feb 2002 05:36:47 GMT
Links: << >>  << T >>  << A >>
Hi,

Does anybody have the Xilinx Foundation Series 2.1i newest not locked
license.dat file? My license file have already out of date and I need to go
back to a project which was designed under 2.1i for some detail matter. The
3.1i also helpful.

Thanks very much!




Article: 39594
Subject: Re: NT parallel port driver
From: "Hans Summers" <Hans.Summers@Tudor.Com>
Date: Thu, 14 Feb 2002 07:29:54 -0000
Links: << >>  << T >>  << A >>

I tried a number of drivers, with very limited success until I tried this
shareware one:

http://www.entechtaiwan.com/tools.htm

------------------
Hans Summers
http://www.HansSummers.Com




"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
news:3C63F908.4E013FFD@algor.co.uk...
> I'm after an WinNT/2K Parallel port driver so I can realise a Flash
> based FPGA config data store.
>
> I'd prefer free or share ware but a modest cost wouldn't be out of the
> question. Could someone point me in the right direction ?
>



Article: 39595
Subject: Re: RAM CORE settings for maximum speed
From: dottavio@ised.it (Antonio)
Date: 13 Feb 2002 23:39:44 -0800
Links: << >>  << T >>  << A >>
The problem is that to speed up my thesis I would want to use the ram
single port core but it seems this not produce good results in terms
of speed, this would mean that I'll try to design also the ram circuit
always for XCV1K.
About this are well accepted link to tutorial about this and why not,
example of using of blockram for this application. Thanks and excuse
to Falk for my to be so pedant.

Antonio

Article: 39596
Subject: Re: Foundation 4.1 vs. ISE 4.1?
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Thu, 14 Feb 2002 10:15:28 +0200
Links: << >>  << T >>  << A >>
> Based on experience (see the par and carry chains not... thread), I'd
stick with
> 3.3 unless you are doing a virtexII design.
>

Thanks... am working on Spartan II, so will stick to 3.3

adrian




Article: 39597
Subject: Re: Foundation 4.1 vs. ISE 4.1?
From: ZhengLin <zdzlin@163.com>
Date: Thu, 14 Feb 2002 00:57:08 -0800
Links: << >>  << T >>  << A >>
Ise supports language designs  very well, and it will use less resource when doing the same thing in the foundatation when a projrct is designed by using language, so if you using language and you have time, you'd better to learn how to use ise!

Article: 39598
Subject: Trivial (?) problem with Xilinx - System Generator (tristate port pin)?
From: "Bernhard Holzmayer" <Holzmayer.Bernhard@foerstergroup.de>
Date: Thu, 14 Feb 2002 09:58:28 +0100
Links: << >>  << T >>  << A >>
Hello.

While doing my first steps with Xilinx System Generator (V2.1), I
hit a
(maybe trivial) problem:

I have a port / pin, which is both, input and output.
It must be written depending on a flag's state, being high-Z
otherwise.
In VHDL it would be something like the following:
...
...process(flag, data)
begin
  if (flag = '1') then
    port <= "ZZZZZZZZ";
  else
    port <= data;
  end if;
end process;

Help me: how can I set this port into the high-Z state using SysGen?
Does anyone know this ???

Bernhard





Article: 39599
Subject: Re: fifo in coregen? Xilinx (ise4.1) is screwed up!
From: ZhengLin <zdzlin@163.com>
Date: Thu, 14 Feb 2002 01:05:41 -0800
Links: << >>  << T >>  << A >>
Yes, you'd better let your clock(both the read and write) run continously, and you had to initial it when power up, or it could not work normally!



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