Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 39800

Article: 39800
Subject: Mux implemented as tristate
From: skepticon@yahoo.com (Skept)
Date: 19 Feb 2002 18:10:40 -0800
Links: << >>  << T >>  << A >>
Hello,

I'm trying to achieve a muxing function using tri-state buffers in Xilinx.
However, synthesis is still giving me mux instead.

the following is what I'm trying to implement:

//tristate mux function
assign o_temp	= ~sel_mux[0] ? in[3:0]   : 4'bzzzz;
assign o_temp	= ~sel_mux[1] ? in[7:4]   : 4'bzzzz;
assign o_temp	= ~sel_mux[2] ? in[11:8]  : 4'bzzzz;
assign o_temp	= ~sel_mux[3] ? in[15:12] : 4'bzzzz;
assign o_temp	= ~sel_mux[4] ? in[19:16] : 4'bzzzz;
assign o_temp	= ~sel_mux[5] ? in[23:20] : 4'bzzzz;
assign o_temp	= ~sel_mux[6] ? in[27:24] : 4'bzzzz;
assign o_temp	= ~sel_mux[7] ? in[31:28] : 4'bzzzz;

always @(posedge clk or negedge rstn)
begin
  if (~rstn)
    out	<= 4'h0;
  else
    out	<= o_temp;
end

the intention is to generate the combinational mux out (o_temp) as
tristate buffers followed by a register.

how do i do what i want??

thanks in advance.

Article: 39801
Subject: Re: Xilinx ISE 3.3 upgrade to 4.1
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Feb 2002 04:48:13 GMT
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:

> hamish@cloud.net.au wrote:
>
> > Rick Filipkiewicz <rick@algor.co.uk> wrote:
> > > Is it possible to use 4.1i speed files when building with 3.3i ? e.g. for an
> > > XCV600E I could just copy over the %XILINX%/virtexe/data/v600e.spd from my 4.1i
> > > installation to my 3.3i one ?
> >
> > No, you'll get error messages about the file format version numbers
> > being different. (I tried it.)
> >
> > Hamish
> > --
> > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
>
> Oh b******s! So its back to the ``exposed butt'' position or use 4.1i.

Rick, call your FAE or the hotline and DEMAND a set of tiing files for 3.3sp8.  The sky
high butt position is likely to get you (sun) burned in a very compromising position,
and as you note, the 4.1 tools are a step backwards from 3.3sp8 for anything but
VirtexII.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39802
Subject: Re: Xilinx IP Core multiplier performance
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Feb 2002 04:56:44 GMT
Links: << >>  << T >>  << A >>
They are pretty well optimized, although there is still a little bit of room for improvement.  That
improvement comes mostly in the floorplanning, not the design of the multiplier however.   If you know
what you are doing, it takes about a day to write a parameterized VHDL design to generate a multiplier
with placement (I know, I did ours which we use in place of the xilinx core for the improved placement).
See the multipliers in FPGAs page on my website as a starting point.

Anyway, the coregen multipliers are better in terms of both density and speed than the average designer is
likely to turn out.  Unless you are wanting to learn the details of the multiplier, go ahead and use the
core.  You won't go far wrong, and in most cases it is plenty fast.

Jay wrote:

> I would have to say that they are already optimized.  Indeed, the
> multiplier performance is a bench mark by which many FPGA vendors are
> judged, so I'd imagine some effort has been expended in this
> direction.
>
> However, having said that, I think its a great project.  Being a
> newbe, means you are not prejudiced by the existing art, and are more
> free to consider novel approaches the old times ruled out long ago for
> now obsolete reasons.
>
> Przemyslaw Wegrzyn <czajnik@czajsoft.pl> wrote in message news:<a4rh5v$9bs$1@panorama.wcss.wroc.pl>...
> > Hello !
> >
> > I need to implement signed 16x16 bit multiplier in my graduate project, I'm
> > going to use Spartan-II device.
> >
> > The question is:
> > Are the multipliers generated by Xilinx's Multiplier Generator v4.0 IP well
> > optimized ?
> > Can I gain any better performance/resource utilisation building a
> > multiplier block myself (at reasonable effort) ?
> >
> > P.Wegrzyn

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39803
Subject: Re: Faster designs
From: Phil Hays <spampostmaster@attbi.com.com>
Date: Wed, 20 Feb 2002 06:02:05 GMT
Links: << >>  << T >>  << A >>
Craig Ward wrote:

> Can anyone give me advice on how to improve my clock speed in my design.  I
> am using timing constraints before you ask!!.
> The chip is a Virtex2000E and I am using synplify and the latest Xilinx PAR
> (ise 4.1etc).  The delays in my design appear to be caused by a few long
> nets
> (fan out 1 etc).  There is lots of free space on the chip so this is not a
> problem.  My target speed is 6.25ns period and the best I can get to is 7ns
> etc with par effort at maximum.  I have tried re-entrant routing with no
> success.

Several things to try, ordered from the end of the process to the start of the
process.  Note that doing the right one of the following will probably solve
your problems:

First, make PAR work harder.  Best chance of success comes from multipass place
and route, with much of the gain from better placement.  I'd try 10 to 30 cost
tables.  Try re-entrant routing on the best couple of results.  Look closely at
why the best couple of results fail.

Second, floorplan the key registers for the critical paths.  The register names
are fairly stable across design changes, so these probably will not need to be
redone after a design change.  I'd suggest "ucf flow", so your physical
constraints go into the design.ucf file along with your timing constraints.  

Third, place key logic into four bit entity architectures and force these into
LUTS so as to give a fixed name for placement.

Fourth, reduce and pipeline logic.  You said "single fanout", but how many
levels of logic?

Fifth, make sure that your synthesis constraints don't get forwarded to PAR. 
Tell synplify to "don't write vendor constraint file", write your timing
constraints (and physical constraints from #2) into the design.ucf file, and
delete the design.ncf file.  Make sure that your design.ucf file has all
required timing constraints in it!

Sixth, buy a faster speed grade part (assuming you don't already have the
fastest) for prototypes, and do the effort to fit into slower speed grade parts
later.

There are higher cost/effort methods, but try the above "easy" stuff first. 
Feel free to ask questions here.  In terms of order of things to try first, #4
might be the best place to start.


-- 
Phil Hays

Article: 39804
Subject: Re: Faster designs
From: lyqin@cti.com.cn (Leon Qin)
Date: 19 Feb 2002 23:58:27 -0800
Links: << >>  << T >>  << A >>
have you try Amplify(from synplicity) ?
It's a great tool!!!


"Craig Ward" <ccward@waitrose.com> wrote in message news:<u75b2r8rif62ed@corp.supernews.com>...
> Hi,
> 
> Can anyone give me advice on how to improve my clock speed in my design.  I
> am using timing constraints before you ask!!.
> The chip is a Virtex2000E and I am using synplify and the latest Xilinx PAR
> (ise 4.1etc).  The delays in my design appear to be caused by a few long
> nets
> (fan out 1 etc).  There is lots of free space on the chip so this is not a
> problem.  My target speed is 6.25ns period and the best I can get to is 7ns
> etc with par effort at maximum.  I have tried re-entrant routing with no
> success.
> 
> The design is still being updated and added to so can anyone tell me how I
> can get better par in general ?  I would imagine that manual placement would
> give me better results in theory but then each time i changed the design I
> would have to repeat this process??  Help!
> 
> Cheers
> Craig

Article: 39805
Subject: Re: FPGA choices and questions
From: lyqin@cti.com.cn (Leon Qin)
Date: 20 Feb 2002 00:06:52 -0800
Links: << >>  << T >>  << A >>
ZhengLin <zdzlin@163.com> wrote in message news:<ee74e16.10@WebX.sUN8CHnE>...
> Actel's FPGA can be programed only once, or it's prom can only be programed only once, but Xilinx's new part, such as spartan 2, can use a flash to program the fpga, if you don't have much experience in fpga design, I support you'd better not use actel's device for your first design!


Actel's ProAsic And ProAsicPlus fpga can be programed many times!

Article: 39806
Subject: Re: Virtex II multiplier pipeline
From: David Hawke <dhawke@xilinx.com>
Date: Wed, 20 Feb 2002 09:29:46 +0000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------3CA3BA4FBB2A377967FC00C8
Content-Type: multipart/alternative;
 boundary="------------D241CE1DFA6834ACC8B77407"


--------------D241CE1DFA6834ACC8B77407
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Clark,

You can only use the BMULT in 4.1i automatically. 3.1i doesn't understand the
MULT18x18S.

All you need to do is instantiate the MULT18X18S, and this will give you the
internally pipelined version of the mult.

Dave

Clark Pope wrote:

> We recently upgraded our foundation ISE with a service pack. Now our filters
> using the Virtex II embedded multiplies is taking 12 ns instead of the 10ns
> we had before the upgrade.(Which probably reflects more accurate timing) I
> looked at the design in FPGA editor and found that even though the MULT
> component has a clock input our design is not using it(even though we've
> registered the i/o in VHDL).
>
> Does anyone now how to force the tools to use the clock input on the V2 MULT
> component from VHDL?
>
> Thanks,
> Clark




Article: 39807
Subject: Re: Virtex II multiplier pipeline
From: "MH" <blahblah@blahblah.blah>
Date: Wed, 20 Feb 2002 09:32:22 -0000
Links: << >>  << T >>  << A >>

"Clark Pope" <cepope@mindspring.com> wrote in message news:a4unt4$tlv$1@slb2.atl.mindspring.net...
>
> Does anyone now how to force the tools to use the clock input on the V2 MULT
> component from VHDL?


Instantiate as "MULT18X18S" instead of "MULT18X18".
See Xilinx answer #12533.


MH.





Article: 39808
Subject: Need good PCI book
From: "Victor Levandovsky" <vic@elsyst.km.ua>
Date: Wed, 20 Feb 2002 11:54:58 +0200
Links: << >>  << T >>  << A >>








Article: 39809
Subject: Re: spartan2 clock input from LVPECL signals
From: "David Frith" <david.frith@ffei.co.uk>
Date: Wed, 20 Feb 2002 12:18:55 -0000
Links: << >>  << T >>  << A >>
"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
news:a4uak6$jco$1@msunews.cl.msu.edu...
> I am designing a system using a 100MHz clock.  The orignal clock is a 3.3v
> LVPECL output.  I will be distributing the clock differntially.  I am
> wondering about any differential input standards for the Spartan2 that
might
> be appropriate to this signal.  (For example, there is a simple voltage
> divider conversion from LVPECL to LVDS.) Otherwise I will need to include
a
> an LVPECL to LVTTL translator.  This is not a big deal, but if I can avoid
> it, I would prefer to do so.

We convert the LVPECL output from a 100331 device to LVDS to feed into a
Virtex-E device and it works fine up to and beyond 200MHz.

Capacitively couple the 2 differential LVPECL signals (0.01uF), reference
the signals to about 1.2v (51R on each half of the pair to a 130R/75R/0.1uF
reference on the 3v3 supply) and possibly include something to prevent
over-driving the FPGA inputs (series 100R near the FPGA pins).

David



Article: 39810
Subject: Re: Coolrunner and ISP
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 20 Feb 2002 08:55:48 -0500
Links: << >>  << T >>  << A >>
That may sound easy, but there are four devices on the board in the scan
chain; a DSP chip, the MCU, an XC2Se FPGA and the XCR3256XL CPLD. I had
planned to program the CPLD and FPGA via the DSP rather than directly
from the MCU (the MCU can access the entire DSP memory map via the DSP
host port). There are no extra pins on the MCU to directly control the
CPLD. Also, with the CPLD in the scan chain, I don't see how the TDI pin
can be driven by a device on the board unless the CPLD is the first
device in the chain. But even then, when the CPLD is driven by the MCU,
all the other devices in the scan chain will be clocked on their JTAG
port including the MCU! 

Maybe I am missing something, but this sounds very complicated to me. I
was expecting the CPLD to be programmable via non-JTAG dedicated pins
like the FPGA. The JTAG programming seems fine if you want to program
via a cable, but it does not seem to be compatible with boundary scan if
programmed from an on board MCU that is also part of the scan chain. 



David Hawke wrote:
> 
> Rick,
> 
> Just connect the port to the MCU, implement an SVF player in the MCU
> (details on our web site), and then ensure that the MCU cannot drive when
> the board is being boundary scanned.
> 
> Dave
> 
> rickman wrote:
> 
> > I think I may have missed a significant point about the Coolrunner CPLDs
> > and ISP. I picked the XCR3256XL because I needed to be able to do
> > boundary scan on the board for production test and I wanted to be able
> > to change the design on the fly (meaning from the MCU on the board). But
> > it looks like the only way to program this part is to use the JTAG port.
> > Connecting the JTAG port to the MCU prevents me from using the JTAG port
> > for boundary scan.
> >
> > Am I missing something? Does ISP mean connecting the board to a PC
> > through a JTAG cable? Is that the only way I can program an XPLA3 part?
> > I could replace this part with a 3.3 volt FPGA, but I hate to do that
> > since I expect 3.3 volt FPGAs will be going the way of the dodo bird in
> > a year or two and they are not cheap in the meantime.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 39811
Subject: gate array
From: "svhb" <svhb@pandora.be>
Date: Wed, 20 Feb 2002 15:10:43 +0100
Links: << >>  << T >>  << A >>
Hi,

I've done a design in a SpartanXL 30, what is the best way to convert it to
a gate array, from the verilog code or from the edif output from the
complete placed and routed FPGA?

The design is fully synchronous. I have a testbench in verilog, but because
the desing is using a rather complex serial interface, it takes long to
simulate. Is a verilog testbench appropriate to do the simulations during
asic development?

Thanks



Article: 39812
Subject: Re: Mux implemented as tristate
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 20 Feb 2002 14:45:31 +0000
Links: << >>  << T >>  << A >>


Skept wrote:

> Hello,
>
> I'm trying to achieve a muxing function using tri-state buffers in Xilinx.
> However, synthesis is still giving me mux instead.
>
> the following is what I'm trying to implement:
>
> //tristate mux function
> assign o_temp   = ~sel_mux[0] ? in[3:0]   : 4'bzzzz;
> assign o_temp   = ~sel_mux[1] ? in[7:4]   : 4'bzzzz;
> assign o_temp   = ~sel_mux[2] ? in[11:8]  : 4'bzzzz;
> assign o_temp   = ~sel_mux[3] ? in[15:12] : 4'bzzzz;
> assign o_temp   = ~sel_mux[4] ? in[19:16] : 4'bzzzz;
> assign o_temp   = ~sel_mux[5] ? in[23:20] : 4'bzzzz;
> assign o_temp   = ~sel_mux[6] ? in[27:24] : 4'bzzzz;
> assign o_temp   = ~sel_mux[7] ? in[31:28] : 4'bzzzz;
>
> always @(posedge clk or negedge rstn)
> begin
>   if (~rstn)
>     out <= 4'h0;
>   else
>     out <= o_temp;
> end
>
> the intention is to generate the combinational mux out (o_temp) as
> tristate buffers followed by a register.
>
> how do i do what i want??
>
> thanks in advance.

Most synth tools have some sort of ``convert tri-state to mux'' flag or
directive, I know Synplify does.
Could yours be set by default ?

Anyway: Unless you are very tight for space using a "real" mux is a much
faster way to go and, if you ever ASIC convert, your vendor will hate you :-).


Article: 39813
Subject: Re: Some problem initializing a RAMB4S1
From: dottavio@ised.it (Antonio)
Date: 20 Feb 2002 06:53:14 -0800
Links: << >>  << T >>  << A >>
Thank you Dave, I've change it and now simulation it's ok but still
the result is that the blockram's are not initialized in fact I see in
FPGA Editor that all the init are zeroes.
I'm asking if there is a code that is recognized both from Aldec
simulator and Xilinx Mapper and Placer, I'm also wondering why Aldec
produce code that is not automatically recognized by Xilinx.

Thanks

 Antonio

P.S. I would be gratiful if you can tell me how to change the
following code to obtain the scope of initializing the blockrams



---------------------------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;


--pragma translate_off
--unisim library for simulation. Here a behavioural model of the BRAM
is stored.
library unisim;
use unisim.vcomponents.all;
--pragma translate_on


entity RAm is
  port(
       clk : in std_ulogic;
       ADDR : in STD_LOGIC_VECTOR(11 downto 0);
       dout : out STD_LOGIC_VECTOR(11 downto 0)
  );
end RAm;

architecture RAm of RAm is

---- Component declarations -----

component RAMB4_S1
-- synopsys translate_off
  generic(
       INIT_00 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_01 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_02 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_03 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_04 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_05 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_06 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_07 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_08 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_09 : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0A : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0B : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0C : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0D : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0E : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000";
       INIT_0F : BIT_VECTOR :=
X"0000000000000000000000000000000000000000000000000000000000000000"
  );
-- synopsys translate_on
  port (
       ADDR : in STD_LOGIC_VECTOR(11 downto 0);
       CLK : in std_ulogic;
       DI : in STD_LOGIC_VECTOR(0 downto 0);
       EN : in std_ulogic;
       RST : in std_ulogic;
       WE : in std_ulogic;
       DO : out STD_LOGIC_VECTOR(0 downto 0)
  );
end component;

----     Constants     -----
constant VCC_CONSTANT   : STD_LOGIC := '1';
constant GND_CONSTANT   : STD_LOGIC := '0';

---- Signal declarations used on the diagram ----

signal GND : STD_LOGIC;
signal VCC : STD_LOGIC;

---- Configuration specifications for declared components 



begin

----  Component instantiations  ----

U1 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"f0c33cf0f0f00f0ff0f00f0f0f3cc30ffc03fcc003fc033ffcc03fc0033fc03f",
       INIT_01 => X"000000000000000000000000000000006a52a92aaa6aa5a995a5565554954a56",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"ffcccc33f3cccc33cc3333cfcc3333ffcf30f30cf30c00ffff0030cf30cf0cf3",
       INIT_05 => X"73733939ccccc7c7e3e333339c9ccecefcc0033ff0030ffc3ff0c00ffcc0033f",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"f030300c000f0fcff3f0f000300c0c0ffff00ff30ff0300ff00c0ff0cff00fff",
       INIT_09 => X"f81ffa07fa05fa05a05fa05fe05ff81ff300cff3cff3300ff00ccff3cff300cf",
       INIT_0A => X"ff00abd5ff002addbb5400ffabd500ff4df3df3004ff4df3cfb2ff200cfbcfb2",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(0),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U10 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"3030cfcfcfcf3030f3f30c0c0c0cf3f33cc33cc30ff00ff0f00ff00f3cc33cc3",
       INIT_01 => X"000000000000000000000000000000007ffcf0c0fcf0c000fffcf0c0fcf0c000",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"3cccccc3cfc3c330f330300c3c0c0cc30303ccfc3f33c0c0fcff3303c0cc3f33",
       INIT_05 => X"7ffefeeafefaeaa8eaa8a880a8a0800133cc33cc3cc333c03c333cc3cc33fc33",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"ff000000ff0f0f00ff000000ff0f0f00f3cf30f3f3cf00f0f3ff0c3030ff0c30",
       INIT_09 => X"91896e76767789e8e8ee159191896e76fc00ffcc0033ff00ffc033fffc00ffc0",
       INIT_0A => X"d2d64bd2696b2969696b2d69b42d96b4a55a5aada55a5aa55aa5a55a5aa5a55a",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(5),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U11 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"000ccccc000ccccccccfffffcccfffff33ff33ff33ffffff0033003300333333",
       INIT_01 => X"000000000000000000000000000000007cc3c33cc30f3cf0f8c3873cc31e3ce0",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"ccc0c0c3c30303333333333c3f3c3cccc00ff00f0ff0033f03fcf00f0ff00ff0",
       INIT_05 => X"3cc3c33cc30c3cc33cc3c33cc31c3cc3c0f03f030f03f0fc00f03f0f3f0fc0fc",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"ff0000f0f00f0f00ff0000f0f00f0f00cfcf0030cc0c30333033cfcff3f3cc0c",
       INIT_09 => X"a779615a1a8786e1791e1a87a779615acf33c330cc33cc33330c33ccc330f33c",
       INIT_0A => X"922664d9d992b66d499b926464d9d9b6999c98c667717119673971998ee6e667",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(3),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U12 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"0ff3300f0ff000ff0ff000ffff300cff0300fc3fff0300ff03c0ff3fff00c0ff",
       INIT_01 => X"0000000000000000000000000000000073633133cc8cc6cee6c6676698198c98",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"f03c3c0f0fc3c3f0c3f0f03f3c0f0ff0c3f3cfc3cfc33cc33c3cf33cf33cc330",
       INIT_05 => X"4fb0f20d3cc3cb34cf30f00f2cd3c33ccff3cccc3ccc3330333cf333cff3cccc",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"0f3030ffff0000ff0cf0f0ffcf0000fff0000ffc0fffc00f000ff000f0000ff0",
       INIT_09 => X"a5baa5a25a5f5a5f5a055a05a5faa5bac33c0cc30cc33cccc3300cc30cc33c0c",
       INIT_0A => X"999966b3999966bb6632996666b39966699a96a69669699a9624694969929624",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(1),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U2 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"ccc00333ccc33333333ccccc33fccccccc33cf33cc333333330c33cc33cc0ccc",
       INIT_01 => X"0000000000000000000000000000000040bf02ff33cc3bccc43b44bb23dd33dc",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"000c0c0f0fcfcfff3000000f0c0f0fffcfff303030300ccf0c0cfff3fff33000",
       INIT_05 => X"b0ff00f2f3cf30fb30ff00f0f3df30f3c330c33cf33cf00c0ff3cff0c330c33c",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"f0c0c00f0f0f0ff0f000000f0f0f0ff03c3ccc3c33c33c333c333c3cc3c333c3",
       INIT_09 => X"39dcc63b63999c669c666399399cc62303c00f03f0fcc0f0fc3ff0fc0f033f0f",
       INIT_0A => X"4bb4d2bcb44b2d4b2dc24bd2d2bcb42d177a7ea17ee8e8857ea1e817e885815e",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(2),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U3 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"c3c3c3c3c3c3c3c33c3c3c3c3c3c3c3ccccccccc3333333333333333cccccccc",
       INIT_01 => X"0000000000000000000000000000000070f30c30f3ff30f0f0f30830f3ef30f0",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"0ff0f00cf30c0cc33cc3c330cf30300f03c333c33c333c3cc3c033c33c333c33",
       INIT_05 => X"6aa9a995a9a595569556566a564a6aa93000f0f00f0f000c0fff0f0ff0f0cff3",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"000000ff000f0fff000000ff000f0fff3cc3c30c3cc3f30f0cf03cc3cf303cc3",
       INIT_09 => X"c69e869c9c191879616763e6c69e869c03ccfc33ff3300cccc3f330003cccc3f",
       INIT_0A => X"b99d22bb44469dd4d446b9dd22bb4462eeefeff7888e8eee88ce8eee00080888",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(4),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U4 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"ff00ff00ff00ff00ff00ff00ff00ff00ffff0000ffff0000ffff0000ffff0000",
       INIT_01 => X"00000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff00",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000",
       INIT_05 => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000",
       INIT_09 => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
       INIT_0A => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(11),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U5 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"f00f3fc03fc00ff0f00ffc03fc030ff0f3300ccf0ffff000fff0000f0ccff330",
       INIT_01 => X"00000000000000000000000000000000255a5aa5a55a5aa55aa5a55a5aa5a55a",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"30f0f0f30c0c0c3cc3c3c3cf303030f30c0cf0f0cfc30f0f0f0f3c0cf0f0cfc3",
       INIT_05 => X"daa5a55a5aa5a55aa55a5aa5a55a5aa40fc30fc3fc3ff03c03f003c03c0f3c0f",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"c33c3c3c3cccccc33cc3c3c3c333333cff3000ff00cfff00ff000cff00fff300",
       INIT_09 => X"dad2b4a45b5ad2b2b2b4a525dad2b4a4f00f0ff0f03c0ff0f00fc3f0f00f0ff0",
       INIT_0A => X"dfdbb0204d4ff2b2b2b00d4dfbf22404f550500af550500aaff5f550aff5f550",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(6),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U6 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"3fcc003f003fcc033fcc03ff03ffcc03000ff330f00ffff0f0000ff0f3300fff",
       INIT_01 => X"00000000000000000000000000000000b44f4ff2f22c2ccb2ccbcbb0b00d0dd3",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"fc3c3c3fc0c0c0f0f0f0f0fc030303c0f0f00000f0fc0000ffffc0f0fffff0fc",
       INIT_05 => X"b0cb0db0d30d34d334d34f34f24f2cf2ff33ff3333003f03ff03ff3333003300",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"3ffcfcfcf0c0c0c0fcf0f0f0c0000003000fff00f00ffff0f0000ff0ff000fff",
       INIT_09 => X"3fdcc403bfdcc0033ffcc4023fdcc4033fcc003f03ffcc033fcc003f03ffcc03",
       INIT_0A => X"2ff0f0f0f040f00f0ff0fdf0f0f0f00b344f4ff0f22c2cc33ccbcbb0f00d0dd3",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(8),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U7 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"0030ffff0000f3ff0030ffff0000f3ff00ff00ff00f000ff00fff0ff00ff00ff",
       INIT_01 => X"0000000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"000c0cff00cfcfff000000ff000f0fff00ffffff000000ff00ffffff000000ff",
       INIT_05 => X"00ff00ff20ff00ff00ff00fb00ff00ff00f0f0ff00f0f0ff00f0f0ff00f0f0ff",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"000c0cff00cfcfff000000ff000f0fff00ff00ff00f000ff00fff0ff00ff00ff",
       INIT_09 => X"00f330ff00f330ff00f330ff00f330ff0030ffff0000f3ff0030ffff0000f3ff",
       INIT_0A => X"00ff000f0fff00ff00ff000f0fff00ff00ff00ff00ff00ff00ff00ff00ff00ff",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(10),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U8 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0fff0ffff000f0000ffff0fff0000f000",
       INIT_01 => X"00000000000000000000000000000000fbb0b000fff3f330f3303000fff2f220",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"f30c0cf030cfcf00ff0000f3f00f0f30ff0000ff00ffff00ff0000ff00ffff00",
       INIT_05 => X"ff30f200dff2fb20fb20b004ffb0f300f00f0ff0f00f0ff0f00f0ff0f00f0ff0",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"f00c0cf300cfcf30f30000ff300f0ff0fff0ffff000f0000ffff0fff0000f000",
       INIT_09 => X"f02ccbf0f02ccff0f00ccbf0f02ccbf0f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0",
       INIT_0A => X"ff0f0ff0f0bf0f00ff0f02f0f00f0f00fbb0b000fff3f330f3303000fff2f220",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(9),
       EN => VCC,
       RST => GND,
       WE => GND
  );

U9 : RAMB4_S1
-- synopsys translate_off
  generic map (
       INIT_00 => X"c3cc33f333f3cc3cc3cc30333033cc3cf00ffcc0000ff00f0ff00ffffcc00ff0",
       INIT_01 => X"0000000000000000000000000000000046636339399c9cc69cc6c6636339399c",
       INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_04 => X"0ccccccfc3c3c3f33030303c0c0c0ccf0f0f00000f03f0f0f0f03f0fffff0f03",
       INIT_05 => X"63c639639c39c69cc69c63c639639c39330c330ccf33c330333c330ccf33cf33",
       INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_08 => X"cf0c0c0cf3c3c3cf0c303030cf0f0f0cf00ff0f00f3ff00f0ff0030ff0f00ff0",
       INIT_09 => X"e31cc738639ce33cc338c639e31cc738c3cc33c33c03cc3cc3cc3fc33c33cc3c",
       INIT_0A => X"df2000ffb24fff00ff000db200fffb04c6636333399c9cccccc6c6633339399c",
       INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
       INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
  )
-- synopsys translate_on
  port map(
       ADDR => ADDR,
       CLK => CLK,
       DI(0) => GND,
       DO(0) => dout(7),
       EN => VCC,
       RST => GND,
       WE => GND
  );


---- Power , ground assignment ----

GND <= GND_CONSTANT;
VCC <= VCC_CONSTANT;

end RAm;

Article: 39814
Subject: Counter does not fit CPLD?
From: "Dan Oprisan" <dandy1313@yahoo.com>
Date: Wed, 20 Feb 2002 16:08:52 +0100
Links: << >>  << T >>  << A >>
Hi,

I once configured a Xilinx FPGA using VHDL (it was my diploma thesis). Now I
built myself a small devellopment board using a small ALTERA EPM7064 CPLD
for fooling around. I use the free MAX2 PLUS and Leonardo Spectrum software
provided for free.

I got some very simple designs running, but as it gets slightly complicated,
it won't fit on the CPLD anymore. Either the CPLD is _really_ small, or I my
code is really messed up (although the same code would have worked without
problem on the FPGA).

An example:
I'm trying to divide the ~40MHz clock to 2^29 in order to see a LED
blinking. The place & route fails with the message:

Error: Logic cell LED requires too many (30/16) shareable expanders

The code snippet:

     VARIABLE    q      : std_logic_vector(28 DOWNTO 0);
     SIGNAL      ledbuf : std_logic;
BEGIN

  PROCESS (CKR)
  BEGIN

  IF (CKR'EVENT AND CKR = '1') THEN
      IF (q = "00000000000000000000000000000") THEN
       q := "10000000000000000000000000000";
       ledbuf <= NOT ledbuf;
      ELSE
       q := q - "00000000000000000000000000001";

      END IF;
   END IF;

   END PROCESS;

I tried do define q as an integer (and many other things) by I couldn't get
it work. Anybody knows what the problem is?

Thanks, Dan




Article: 39815
Subject: Re: Few pins but more gates
From: "svhb" <svhb@pandora.be>
Date: Wed, 20 Feb 2002 16:32:39 +0100
Links: << >>  << T >>  << A >>
This is a general problem with FPGA's, everyone makes components with
hundreds of I/O on nice and small ball grids. If you make designs with
serial interfaces to keep the nulmber of connections low (e.g. on industiral
machinery, ...), you end up with more logic.

So I think they use the "number of IO pins" in the opposite way for
commercial reasons. It must be : the more logic you want, the less IO you
need.


"Frank Vorstenbosch" <frank@kingswood-consulting.co.uk> wrote in message
news:3C72C32B.3000105@kingswood-consulting.co.uk...
> Hallo!
>
> I'm trying to put my small design into a MAX3064ATC44 but would really
> like more than the 64 registers this device offers me.  I do want to
> keep the 44 pin TQFP, but maybe 96 or even 128 registers would be nice.
>
> Any suggestions?
>
> Frank
> --
> ------------------------------------------------------------------------
> Frank A. Vorstenbosch   <SPAM_ACCEPT="NONE">    Phone:  +44-7976-430 569
> Wimbledon, London SW19                  frank@kingswood-consulting.co.uk
>



Article: 39816
Subject: Re: Modelsim questions
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Wed, 20 Feb 2002 09:10:50 -0700
Links: << >>  << T >>  << A >>

Yury,

Did you say you compiled the SIMPRIM and other Xilinx libraries?  If so,
that may be why it is running so slow.  ModelSim-XE should not be too
painful for a 60% utilized 2S200 even when running timing simulation
(although painful is a relative word).  If however you compiled the
libraries, it could be very painful.  The libraries for ModelSim-XE are
pre-compiled not only for your convenience but also to help "speed-up" the
software for you.  What I mean by that is when using the pre-compiled
Xilinx libraries, they are only counted as one line of code per element
rather than the number of executable lines that make up the library.  If
however, you compiled the library, each element will count as several more
lines and you will reach the line limitation threshold much quicker and
thus be penalized with poorer simulator performance.

The moral of the story, do not compile the Xilinx libraries when using
ModelSim-XE.  When you install the software, the libraries are
pre-compiled and pre-mapped.  If you need an update, download it from the
Xilinx web site at: http://support.xilinx.com/support/mxelibs/index.htm
and simply unzip it to the ModelSim directory.  That is it.


--  Brian



Yury wrote:

> Modelsim XE is able to do everything that Modelsim PE can (according
> to Xilinx). I have used both. The XE version can be used without ISE
> software. You can use Modelsim XE, for example, for compiling
> Foundation VHDL libraries and then using them (Simprim, Unisim,
> Coregen, etc.). While slower then PE/SE, Modelsim XE will be able to
> perform pre-PAR simulation for you. However... if you want to do a
> post PAR functional (and possibly include the timing information)
> simulation then you are in for a treat. I attempted to use Modelsim XE
> for simulating post PAR 60% utilized Spartan-II-200. All I can say is
> there is a better way to spend my time. The simulation was taking
> forever without any timing info.
>  If I new ahead of time that ModelSim XE would be such a poor piece of
> software I would never have advised my emploer to purchase it. I guess
> you get what you pay for stands ($900 can not buy you a desent
> simulator).


Article: 39817
Subject: Re: Coolrunner and ISP
From: Alan Nishioka <alann@accom.com>
Date: Wed, 20 Feb 2002 08:29:25 -0800
Links: << >>  << T >>  << A >>
rickman wrote:

>That may sound easy, but there are four devices on the board in the scan
>chain; a DSP chip, the MCU, an XC2Se FPGA and the XCR3256XL CPLD. I had
>planned to program the CPLD and FPGA via the DSP rather than directly
>from the MCU (the MCU can access the entire DSP memory map via the DSP
>host port). There are no extra pins on the MCU to directly control the
>CPLD. Also, with the CPLD in the scan chain, I don't see how the TDI pin
>can be driven by a device on the board unless the CPLD is the first
>device in the chain. But even then, when the CPLD is driven by the MCU,
>all the other devices in the scan chain will be clocked on their JTAG
>port including the MCU! 
>
JTAG should operate completely independently from the function of any 
chip.  You should be able to put all the other chips in JTAG bypass 
(while they are running or not) and only affect the single chip you want 
(the CPLD).  JTAG CPU emulators work this way.  They allow the CPU to 
run at full speed and still allow access to the CPU internals via the 
JTAG port.

Alan Nishioka
alann@accom.com


Article: 39818
Subject: Re: Some problem initializing a RAMB4S1
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Wed, 20 Feb 2002 09:36:14 -0700
Links: << >>  << T >>  << A >>



Antonio,

If you are using the latest version of XST as your synthesis tool, all you need to do is take out all
of the "-- synopsys translate_off" and "--synopsys translate_on" from your code (including the one
around the UNISIM library declaration) and you should have what you want.  XST can not recognize
generics for RAM and use them for passing initinization information. If you are using another synthesis
tool (unless there has been some recent changes), you will need to keep the translate_off/on's and add
attribute declartions to your code like:

attribute INIT_00: string;
attribute INIT_01: string;
   :
   :

attribute INIT_00 of U1 : label is "f0c33cf0f0f00f0ff0f00f0f0f3cc30ffc03fcc003fc033ffcc03fc0033fc03f";
attribute INIT_01 of U1 : label is "000000000000000000000000000000006a52a92aaa6aa5a995a5565554954a56";
   :
   :

For each INIT in order to pass it via the synthesis tool.  You will have to make sure both generic and
attribute values are the same or else you may get a simulation-implementation mis-match.
Altenantively, you can add this information in the UCF file and pass it that way if you do not wish to
add those line to your code.

--  Brian

Antonio wrote:

> Thank you Dave, I've change it and now simulation it's ok but still
> the result is that the blockram's are not initialized in fact I see in
> FPGA Editor that all the init are zeroes.
> I'm asking if there is a code that is recognized both from Aldec
> simulator and Xilinx Mapper and Placer, I'm also wondering why Aldec
> produce code that is not automatically recognized by Xilinx.
>
> Thanks
>
>  Antonio
>
> P.S. I would be gratiful if you can tell me how to change the
> following code to obtain the scope of initializing the blockrams
>
> ---------------------------------------------------------------------------------------------------
> -- Design unit header --
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> --pragma translate_off
> --unisim library for simulation. Here a behavioural model of the BRAM
> is stored.
> library unisim;
> use unisim.vcomponents.all;
> --pragma translate_on
>
> entity RAm is
>   port(
>        clk : in std_ulogic;
>        ADDR : in STD_LOGIC_VECTOR(11 downto 0);
>        dout : out STD_LOGIC_VECTOR(11 downto 0)
>   );
> end RAm;
>
> architecture RAm of RAm is
>
> ---- Component declarations -----
>
> component RAMB4_S1
> -- synopsys translate_off
>   generic(
>        INIT_00 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_01 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_02 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_03 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_04 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_05 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_06 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_07 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_08 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_09 : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_0A : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_0B : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_0C : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_0D : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_0E : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
>        INIT_0F : BIT_VECTOR :=
> X"0000000000000000000000000000000000000000000000000000000000000000"
>   );
> -- synopsys translate_on
>   port (
>        ADDR : in STD_LOGIC_VECTOR(11 downto 0);
>        CLK : in std_ulogic;
>        DI : in STD_LOGIC_VECTOR(0 downto 0);
>        EN : in std_ulogic;
>        RST : in std_ulogic;
>        WE : in std_ulogic;
>        DO : out STD_LOGIC_VECTOR(0 downto 0)
>   );
> end component;
>
> ----     Constants     -----
> constant VCC_CONSTANT   : STD_LOGIC := '1';
> constant GND_CONSTANT   : STD_LOGIC := '0';
>
> ---- Signal declarations used on the diagram ----
>
> signal GND : STD_LOGIC;
> signal VCC : STD_LOGIC;
>
> ---- Configuration specifications for declared components
>
> begin
>
> ----  Component instantiations  ----
>
> U1 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"f0c33cf0f0f00f0ff0f00f0f0f3cc30ffc03fcc003fc033ffcc03fc0033fc03f",
>        INIT_01 => X"000000000000000000000000000000006a52a92aaa6aa5a995a5565554954a56",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"ffcccc33f3cccc33cc3333cfcc3333ffcf30f30cf30c00ffff0030cf30cf0cf3",
>        INIT_05 => X"73733939ccccc7c7e3e333339c9ccecefcc0033ff0030ffc3ff0c00ffcc0033f",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"f030300c000f0fcff3f0f000300c0c0ffff00ff30ff0300ff00c0ff0cff00fff",
>        INIT_09 => X"f81ffa07fa05fa05a05fa05fe05ff81ff300cff3cff3300ff00ccff3cff300cf",
>        INIT_0A => X"ff00abd5ff002addbb5400ffabd500ff4df3df3004ff4df3cfb2ff200cfbcfb2",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(0),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U10 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"3030cfcfcfcf3030f3f30c0c0c0cf3f33cc33cc30ff00ff0f00ff00f3cc33cc3",
>        INIT_01 => X"000000000000000000000000000000007ffcf0c0fcf0c000fffcf0c0fcf0c000",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"3cccccc3cfc3c330f330300c3c0c0cc30303ccfc3f33c0c0fcff3303c0cc3f33",
>        INIT_05 => X"7ffefeeafefaeaa8eaa8a880a8a0800133cc33cc3cc333c03c333cc3cc33fc33",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"ff000000ff0f0f00ff000000ff0f0f00f3cf30f3f3cf00f0f3ff0c3030ff0c30",
>        INIT_09 => X"91896e76767789e8e8ee159191896e76fc00ffcc0033ff00ffc033fffc00ffc0",
>        INIT_0A => X"d2d64bd2696b2969696b2d69b42d96b4a55a5aada55a5aa55aa5a55a5aa5a55a",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(5),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U11 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"000ccccc000ccccccccfffffcccfffff33ff33ff33ffffff0033003300333333",
>        INIT_01 => X"000000000000000000000000000000007cc3c33cc30f3cf0f8c3873cc31e3ce0",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"ccc0c0c3c30303333333333c3f3c3cccc00ff00f0ff0033f03fcf00f0ff00ff0",
>        INIT_05 => X"3cc3c33cc30c3cc33cc3c33cc31c3cc3c0f03f030f03f0fc00f03f0f3f0fc0fc",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"ff0000f0f00f0f00ff0000f0f00f0f00cfcf0030cc0c30333033cfcff3f3cc0c",
>        INIT_09 => X"a779615a1a8786e1791e1a87a779615acf33c330cc33cc33330c33ccc330f33c",
>        INIT_0A => X"922664d9d992b66d499b926464d9d9b6999c98c667717119673971998ee6e667",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(3),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U12 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"0ff3300f0ff000ff0ff000ffff300cff0300fc3fff0300ff03c0ff3fff00c0ff",
>        INIT_01 => X"0000000000000000000000000000000073633133cc8cc6cee6c6676698198c98",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"f03c3c0f0fc3c3f0c3f0f03f3c0f0ff0c3f3cfc3cfc33cc33c3cf33cf33cc330",
>        INIT_05 => X"4fb0f20d3cc3cb34cf30f00f2cd3c33ccff3cccc3ccc3330333cf333cff3cccc",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"0f3030ffff0000ff0cf0f0ffcf0000fff0000ffc0fffc00f000ff000f0000ff0",
>        INIT_09 => X"a5baa5a25a5f5a5f5a055a05a5faa5bac33c0cc30cc33cccc3300cc30cc33c0c",
>        INIT_0A => X"999966b3999966bb6632996666b39966699a96a69669699a9624694969929624",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(1),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U2 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"ccc00333ccc33333333ccccc33fccccccc33cf33cc333333330c33cc33cc0ccc",
>        INIT_01 => X"0000000000000000000000000000000040bf02ff33cc3bccc43b44bb23dd33dc",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"000c0c0f0fcfcfff3000000f0c0f0fffcfff303030300ccf0c0cfff3fff33000",
>        INIT_05 => X"b0ff00f2f3cf30fb30ff00f0f3df30f3c330c33cf33cf00c0ff3cff0c330c33c",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"f0c0c00f0f0f0ff0f000000f0f0f0ff03c3ccc3c33c33c333c333c3cc3c333c3",
>        INIT_09 => X"39dcc63b63999c669c666399399cc62303c00f03f0fcc0f0fc3ff0fc0f033f0f",
>        INIT_0A => X"4bb4d2bcb44b2d4b2dc24bd2d2bcb42d177a7ea17ee8e8857ea1e817e885815e",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(2),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U3 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"c3c3c3c3c3c3c3c33c3c3c3c3c3c3c3ccccccccc3333333333333333cccccccc",
>        INIT_01 => X"0000000000000000000000000000000070f30c30f3ff30f0f0f30830f3ef30f0",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"0ff0f00cf30c0cc33cc3c330cf30300f03c333c33c333c3cc3c033c33c333c33",
>        INIT_05 => X"6aa9a995a9a595569556566a564a6aa93000f0f00f0f000c0fff0f0ff0f0cff3",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"000000ff000f0fff000000ff000f0fff3cc3c30c3cc3f30f0cf03cc3cf303cc3",
>        INIT_09 => X"c69e869c9c191879616763e6c69e869c03ccfc33ff3300cccc3f330003cccc3f",
>        INIT_0A => X"b99d22bb44469dd4d446b9dd22bb4462eeefeff7888e8eee88ce8eee00080888",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(4),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U4 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"ff00ff00ff00ff00ff00ff00ff00ff00ffff0000ffff0000ffff0000ffff0000",
>        INIT_01 => X"00000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff00",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000",
>        INIT_05 => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000",
>        INIT_09 => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
>        INIT_0A => X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(11),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U5 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"f00f3fc03fc00ff0f00ffc03fc030ff0f3300ccf0ffff000fff0000f0ccff330",
>        INIT_01 => X"00000000000000000000000000000000255a5aa5a55a5aa55aa5a55a5aa5a55a",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"30f0f0f30c0c0c3cc3c3c3cf303030f30c0cf0f0cfc30f0f0f0f3c0cf0f0cfc3",
>        INIT_05 => X"daa5a55a5aa5a55aa55a5aa5a55a5aa40fc30fc3fc3ff03c03f003c03c0f3c0f",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"c33c3c3c3cccccc33cc3c3c3c333333cff3000ff00cfff00ff000cff00fff300",
>        INIT_09 => X"dad2b4a45b5ad2b2b2b4a525dad2b4a4f00f0ff0f03c0ff0f00fc3f0f00f0ff0",
>        INIT_0A => X"dfdbb0204d4ff2b2b2b00d4dfbf22404f550500af550500aaff5f550aff5f550",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(6),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U6 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"3fcc003f003fcc033fcc03ff03ffcc03000ff330f00ffff0f0000ff0f3300fff",
>        INIT_01 => X"00000000000000000000000000000000b44f4ff2f22c2ccb2ccbcbb0b00d0dd3",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"fc3c3c3fc0c0c0f0f0f0f0fc030303c0f0f00000f0fc0000ffffc0f0fffff0fc",
>        INIT_05 => X"b0cb0db0d30d34d334d34f34f24f2cf2ff33ff3333003f03ff03ff3333003300",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"3ffcfcfcf0c0c0c0fcf0f0f0c0000003000fff00f00ffff0f0000ff0ff000fff",
>        INIT_09 => X"3fdcc403bfdcc0033ffcc4023fdcc4033fcc003f03ffcc033fcc003f03ffcc03",
>        INIT_0A => X"2ff0f0f0f040f00f0ff0fdf0f0f0f00b344f4ff0f22c2cc33ccbcbb0f00d0dd3",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(8),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U7 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"0030ffff0000f3ff0030ffff0000f3ff00ff00ff00f000ff00fff0ff00ff00ff",
>        INIT_01 => X"0000000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"000c0cff00cfcfff000000ff000f0fff00ffffff000000ff00ffffff000000ff",
>        INIT_05 => X"00ff00ff20ff00ff00ff00fb00ff00ff00f0f0ff00f0f0ff00f0f0ff00f0f0ff",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"000c0cff00cfcfff000000ff000f0fff00ff00ff00f000ff00fff0ff00ff00ff",
>        INIT_09 => X"00f330ff00f330ff00f330ff00f330ff0030ffff0000f3ff0030ffff0000f3ff",
>        INIT_0A => X"00ff000f0fff00ff00ff000f0fff00ff00ff00ff00ff00ff00ff00ff00ff00ff",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(10),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U8 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0fff0ffff000f0000ffff0fff0000f000",
>        INIT_01 => X"00000000000000000000000000000000fbb0b000fff3f330f3303000fff2f220",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"f30c0cf030cfcf00ff0000f3f00f0f30ff0000ff00ffff00ff0000ff00ffff00",
>        INIT_05 => X"ff30f200dff2fb20fb20b004ffb0f300f00f0ff0f00f0ff0f00f0ff0f00f0ff0",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"f00c0cf300cfcf30f30000ff300f0ff0fff0ffff000f0000ffff0fff0000f000",
>        INIT_09 => X"f02ccbf0f02ccff0f00ccbf0f02ccbf0f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0",
>        INIT_0A => X"ff0f0ff0f0bf0f00ff0f02f0f00f0f00fbb0b000fff3f330f3303000fff2f220",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(9),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> U9 : RAMB4_S1
> -- synopsys translate_off
>   generic map (
>        INIT_00 => X"c3cc33f333f3cc3cc3cc30333033cc3cf00ffcc0000ff00f0ff00ffffcc00ff0",
>        INIT_01 => X"0000000000000000000000000000000046636339399c9cc69cc6c6636339399c",
>        INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_04 => X"0ccccccfc3c3c3f33030303c0c0c0ccf0f0f00000f03f0f0f0f03f0fffff0f03",
>        INIT_05 => X"63c639639c39c69cc69c63c639639c39330c330ccf33c330333c330ccf33cf33",
>        INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_08 => X"cf0c0c0cf3c3c3cf0c303030cf0f0f0cf00ff0f00f3ff00f0ff0030ff0f00ff0",
>        INIT_09 => X"e31cc738639ce33cc338c639e31cc738c3cc33c33c03cc3cc3cc3fc33c33cc3c",
>        INIT_0A => X"df2000ffb24fff00ff000db200fffb04c6636333399c9cccccc6c6633339399c",
>        INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
>        INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000"
>   )
> -- synopsys translate_on
>   port map(
>        ADDR => ADDR,
>        CLK => CLK,
>        DI(0) => GND,
>        DO(0) => dout(7),
>        EN => VCC,
>        RST => GND,
>        WE => GND
>   );
>
> ---- Power , ground assignment ----
>
> GND <= GND_CONSTANT;
> VCC <= VCC_CONSTANT;
>
> end RAm;



Article: 39819
Subject: Re: Some problem initializing a RAMB4S1
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Wed, 20 Feb 2002 09:43:50 -0700
Links: << >>  << T >>  << A >>




Brian Philofsky wrote:

>
> Antonio,
>
> If you are using the latest version of XST as your synthesis tool, all
> you need to do is take out all of the "-- synopsys translate_off" and
> "--synopsys translate_on" from your code (including the one around the
> UNISIM library declaration) and you should have what you want.  XST
> can not recognize generics for RAM and


^

|
                                                             That should
be now, not not.
It should read XST can now recognize generics for RAM...

Sorry for the confusion.


--  Brian




> use them for passing initinization information. If you are using
> another synthesis tool (unless there has been some recent changes),
> you will need to keep the translate_off/on's and add attribute
> declartions to your code like:
>
> attribute INIT_00: string;
> attribute INIT_01: string;
>    :
>    :
>
> attribute INIT_00 of U1 : label is
> "f0c33cf0f0f00f0ff0f00f0f0f3cc30ffc03fcc003fc033ffcc03fc0033fc03f";
> attribute INIT_01 of U1 : label is
> "000000000000000000000000000000006a52a92aaa6aa5a995a5565554954a56";
>    :
>    :
>
> For each INIT in order to pass it via the synthesis tool.  You will
> have to make sure both generic and attribute values are the same or
> else you may get a simulation-implementation mis-match.
> Altenantively, you can add this information in the UCF file and pass
> it that way if you do not wish to add those line to your code.
>
> --  Brian
>
> Antonio wrote:
>
>> Thank you Dave, I've change it and now simulation it's ok but still
>> the result is that the blockram's are not initialized in fact I see
>> in
>> FPGA Editor that all the init are zeroes.
>> I'm asking if there is a code that is recognized both from Aldec
>> simulator and Xilinx Mapper and Placer, I'm also wondering why Aldec
>>
>> produce code that is not automatically recognized by Xilinx.
>>
>> Thanks
>>
>>  Antonio
>>
>> P.S. I would be gratiful if you can tell me how to change the
>> following code to obtain the scope of initializing the blockrams
>>
>> ----------------------------------------------------------------
>> ----------------------------------
>> -- Design unit header --
>> library IEEE;
>> use IEEE.std_logic_1164.all;
>>
>> --pragma translate_off
>> --unisim library for simulation. Here a behavioural model of the
>> BRAM
>> is stored.
>> library unisim;
>> use unisim.vcomponents.all;
>> --pragma translate_on
>>
>> entity RAm is
>>   port(
>>        clk : in std_ulogic;
>>        ADDR : in STD_LOGIC_VECTOR(11 downto 0);
>>        dout : out STD_LOGIC_VECTOR(11 downto 0)
>>   );
>> end RAm;
>>
>> architecture RAm of RAm is
>>
>> ---- Component declarations -----
>>
>> component RAMB4_S1
>> -- synopsys translate_off
>>   generic(
>>        INIT_00 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_01 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_02 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_03 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_04 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_05 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_06 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_07 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_08 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_09 : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_0A : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_0B : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_0C : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_0D : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_0E : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000";
>>
>>        INIT_0F : BIT_VECTOR :=
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   );
>> -- synopsys translate_on
>>   port (
>>        ADDR : in STD_LOGIC_VECTOR(11 downto 0);
>>        CLK : in std_ulogic;
>>        DI : in STD_LOGIC_VECTOR(0 downto 0);
>>        EN : in std_ulogic;
>>        RST : in std_ulogic;
>>        WE : in std_ulogic;
>>        DO : out STD_LOGIC_VECTOR(0 downto 0)
>>   );
>> end component;
>>
>> ----     Constants     -----
>> constant VCC_CONSTANT   : STD_LOGIC := '1';
>> constant GND_CONSTANT   : STD_LOGIC := '0';
>>
>> ---- Signal declarations used on the diagram ----
>>
>> signal GND : STD_LOGIC;
>> signal VCC : STD_LOGIC;
>>
>> ---- Configuration specifications for declared components
>>
>> begin
>>
>> ----  Component instantiations  ----
>>
>> U1 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"f0c33cf0f0f00f0ff0f00f0f0f3cc30ffc03fcc003fc033ffcc03fc0033fc03f",
>>
>>        INIT_01 =>
>> X"000000000000000000000000000000006a52a92aaa6aa5a995a5565554954a56",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"ffcccc33f3cccc33cc3333cfcc3333ffcf30f30cf30c00ffff0030cf30cf0cf3",
>>
>>        INIT_05 =>
>> X"73733939ccccc7c7e3e333339c9ccecefcc0033ff0030ffc3ff0c00ffcc0033f",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"f030300c000f0fcff3f0f000300c0c0ffff00ff30ff0300ff00c0ff0cff00fff",
>>
>>        INIT_09 =>
>> X"f81ffa07fa05fa05a05fa05fe05ff81ff300cff3cff3300ff00ccff3cff300cf",
>>
>>        INIT_0A =>
>> X"ff00abd5ff002addbb5400ffabd500ff4df3df3004ff4df3cfb2ff200cfbcfb2",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(0),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U10 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"3030cfcfcfcf3030f3f30c0c0c0cf3f33cc33cc30ff00ff0f00ff00f3cc33cc3",
>>
>>        INIT_01 =>
>> X"000000000000000000000000000000007ffcf0c0fcf0c000fffcf0c0fcf0c000",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"3cccccc3cfc3c330f330300c3c0c0cc30303ccfc3f33c0c0fcff3303c0cc3f33",
>>
>>        INIT_05 =>
>> X"7ffefeeafefaeaa8eaa8a880a8a0800133cc33cc3cc333c03c333cc3cc33fc33",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"ff000000ff0f0f00ff000000ff0f0f00f3cf30f3f3cf00f0f3ff0c3030ff0c30",
>>
>>        INIT_09 =>
>> X"91896e76767789e8e8ee159191896e76fc00ffcc0033ff00ffc033fffc00ffc0",
>>
>>        INIT_0A =>
>> X"d2d64bd2696b2969696b2d69b42d96b4a55a5aada55a5aa55aa5a55a5aa5a55a",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(5),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U11 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"000ccccc000ccccccccfffffcccfffff33ff33ff33ffffff0033003300333333",
>>
>>        INIT_01 =>
>> X"000000000000000000000000000000007cc3c33cc30f3cf0f8c3873cc31e3ce0",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"ccc0c0c3c30303333333333c3f3c3cccc00ff00f0ff0033f03fcf00f0ff00ff0",
>>
>>        INIT_05 =>
>> X"3cc3c33cc30c3cc33cc3c33cc31c3cc3c0f03f030f03f0fc00f03f0f3f0fc0fc",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"ff0000f0f00f0f00ff0000f0f00f0f00cfcf0030cc0c30333033cfcff3f3cc0c",
>>
>>        INIT_09 =>
>> X"a779615a1a8786e1791e1a87a779615acf33c330cc33cc33330c33ccc330f33c",
>>
>>        INIT_0A =>
>> X"922664d9d992b66d499b926464d9d9b6999c98c667717119673971998ee6e667",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(3),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U12 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"0ff3300f0ff000ff0ff000ffff300cff0300fc3fff0300ff03c0ff3fff00c0ff",
>>
>>        INIT_01 =>
>> X"0000000000000000000000000000000073633133cc8cc6cee6c6676698198c98",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"f03c3c0f0fc3c3f0c3f0f03f3c0f0ff0c3f3cfc3cfc33cc33c3cf33cf33cc330",
>>
>>        INIT_05 =>
>> X"4fb0f20d3cc3cb34cf30f00f2cd3c33ccff3cccc3ccc3330333cf333cff3cccc",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"0f3030ffff0000ff0cf0f0ffcf0000fff0000ffc0fffc00f000ff000f0000ff0",
>>
>>        INIT_09 =>
>> X"a5baa5a25a5f5a5f5a055a05a5faa5bac33c0cc30cc33cccc3300cc30cc33c0c",
>>
>>        INIT_0A =>
>> X"999966b3999966bb6632996666b39966699a96a69669699a9624694969929624",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(1),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U2 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"ccc00333ccc33333333ccccc33fccccccc33cf33cc333333330c33cc33cc0ccc",
>>
>>        INIT_01 =>
>> X"0000000000000000000000000000000040bf02ff33cc3bccc43b44bb23dd33dc",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"000c0c0f0fcfcfff3000000f0c0f0fffcfff303030300ccf0c0cfff3fff33000",
>>
>>        INIT_05 =>
>> X"b0ff00f2f3cf30fb30ff00f0f3df30f3c330c33cf33cf00c0ff3cff0c330c33c",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"f0c0c00f0f0f0ff0f000000f0f0f0ff03c3ccc3c33c33c333c333c3cc3c333c3",
>>
>>        INIT_09 =>
>> X"39dcc63b63999c669c666399399cc62303c00f03f0fcc0f0fc3ff0fc0f033f0f",
>>
>>        INIT_0A =>
>> X"4bb4d2bcb44b2d4b2dc24bd2d2bcb42d177a7ea17ee8e8857ea1e817e885815e",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(2),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U3 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"c3c3c3c3c3c3c3c33c3c3c3c3c3c3c3ccccccccc3333333333333333cccccccc",
>>
>>        INIT_01 =>
>> X"0000000000000000000000000000000070f30c30f3ff30f0f0f30830f3ef30f0",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"0ff0f00cf30c0cc33cc3c330cf30300f03c333c33c333c3cc3c033c33c333c33",
>>
>>        INIT_05 =>
>> X"6aa9a995a9a595569556566a564a6aa93000f0f00f0f000c0fff0f0ff0f0cff3",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"000000ff000f0fff000000ff000f0fff3cc3c30c3cc3f30f0cf03cc3cf303cc3",
>>
>>        INIT_09 =>
>> X"c69e869c9c191879616763e6c69e869c03ccfc33ff3300cccc3f330003cccc3f",
>>
>>        INIT_0A =>
>> X"b99d22bb44469dd4d446b9dd22bb4462eeefeff7888e8eee88ce8eee00080888",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(4),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U4 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"ff00ff00ff00ff00ff00ff00ff00ff00ffff0000ffff0000ffff0000ffff0000",
>>
>>        INIT_01 =>
>> X"00000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff00",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000",
>>
>>        INIT_05 =>
>> X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"ff0c0c00ffcfcf00ff000000ff0f0f00ffff0000ffff0000ffff0000ffff0000",
>>
>>        INIT_09 =>
>> X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
>>
>>        INIT_0A =>
>> X"ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00ff00",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(11),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U5 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"f00f3fc03fc00ff0f00ffc03fc030ff0f3300ccf0ffff000fff0000f0ccff330",
>>
>>        INIT_01 =>
>> X"00000000000000000000000000000000255a5aa5a55a5aa55aa5a55a5aa5a55a",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"30f0f0f30c0c0c3cc3c3c3cf303030f30c0cf0f0cfc30f0f0f0f3c0cf0f0cfc3",
>>
>>        INIT_05 =>
>> X"daa5a55a5aa5a55aa55a5aa5a55a5aa40fc30fc3fc3ff03c03f003c03c0f3c0f",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"c33c3c3c3cccccc33cc3c3c3c333333cff3000ff00cfff00ff000cff00fff300",
>>
>>        INIT_09 =>
>> X"dad2b4a45b5ad2b2b2b4a525dad2b4a4f00f0ff0f03c0ff0f00fc3f0f00f0ff0",
>>
>>        INIT_0A =>
>> X"dfdbb0204d4ff2b2b2b00d4dfbf22404f550500af550500aaff5f550aff5f550",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(6),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U6 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"3fcc003f003fcc033fcc03ff03ffcc03000ff330f00ffff0f0000ff0f3300fff",
>>
>>        INIT_01 =>
>> X"00000000000000000000000000000000b44f4ff2f22c2ccb2ccbcbb0b00d0dd3",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"fc3c3c3fc0c0c0f0f0f0f0fc030303c0f0f00000f0fc0000ffffc0f0fffff0fc",
>>
>>        INIT_05 =>
>> X"b0cb0db0d30d34d334d34f34f24f2cf2ff33ff3333003f03ff03ff3333003300",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"3ffcfcfcf0c0c0c0fcf0f0f0c0000003000fff00f00ffff0f0000ff0ff000fff",
>>
>>        INIT_09 =>
>> X"3fdcc403bfdcc0033ffcc4023fdcc4033fcc003f03ffcc033fcc003f03ffcc03",
>>
>>        INIT_0A =>
>> X"2ff0f0f0f040f00f0ff0fdf0f0f0f00b344f4ff0f22c2cc33ccbcbb0f00d0dd3",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(8),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U7 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"0030ffff0000f3ff0030ffff0000f3ff00ff00ff00f000ff00fff0ff00ff00ff",
>>
>>        INIT_01 =>
>> X"0000000000000000000000000000000000ff00ff00ff00ff00ff00ff00ff00ff",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"000c0cff00cfcfff000000ff000f0fff00ffffff000000ff00ffffff000000ff",
>>
>>        INIT_05 =>
>> X"00ff00ff20ff00ff00ff00fb00ff00ff00f0f0ff00f0f0ff00f0f0ff00f0f0ff",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"000c0cff00cfcfff000000ff000f0fff00ff00ff00f000ff00fff0ff00ff00ff",
>>
>>        INIT_09 =>
>> X"00f330ff00f330ff00f330ff00f330ff0030ffff0000f3ff0030ffff0000f3ff",
>>
>>        INIT_0A =>
>> X"00ff000f0fff00ff00ff000f0fff00ff00ff00ff00ff00ff00ff00ff00ff00ff",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(10),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U8 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0fff0ffff000f0000ffff0fff0000f000",
>>
>>        INIT_01 =>
>> X"00000000000000000000000000000000fbb0b000fff3f330f3303000fff2f220",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"f30c0cf030cfcf00ff0000f3f00f0f30ff0000ff00ffff00ff0000ff00ffff00",
>>
>>        INIT_05 =>
>> X"ff30f200dff2fb20fb20b004ffb0f300f00f0ff0f00f0ff0f00f0ff0f00f0ff0",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"f00c0cf300cfcf30f30000ff300f0ff0fff0ffff000f0000ffff0fff0000f000",
>>
>>        INIT_09 =>
>> X"f02ccbf0f02ccff0f00ccbf0f02ccbf0f0c3f0f0f0f03cf0f0c3f0f0f0f03cf0",
>>
>>        INIT_0A =>
>> X"ff0f0ff0f0bf0f00ff0f02f0f00f0f00fbb0b000fff3f330f3303000fff2f220",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(9),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> U9 : RAMB4_S1
>> -- synopsys translate_off
>>   generic map (
>>        INIT_00 =>
>> X"c3cc33f333f3cc3cc3cc30333033cc3cf00ffcc0000ff00f0ff00ffffcc00ff0",
>>
>>        INIT_01 =>
>> X"0000000000000000000000000000000046636339399c9cc69cc6c6636339399c",
>>
>>        INIT_02 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_03 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_04 =>
>> X"0ccccccfc3c3c3f33030303c0c0c0ccf0f0f00000f03f0f0f0f03f0fffff0f03",
>>
>>        INIT_05 =>
>> X"63c639639c39c69cc69c63c639639c39330c330ccf33c330333c330ccf33cf33",
>>
>>        INIT_06 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_07 =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_08 =>
>> X"cf0c0c0cf3c3c3cf0c303030cf0f0f0cf00ff0f00f3ff00f0ff0030ff0f00ff0",
>>
>>        INIT_09 =>
>> X"e31cc738639ce33cc338c639e31cc738c3cc33c33c03cc3cc3cc3fc33c33cc3c",
>>
>>        INIT_0A =>
>> X"df2000ffb24fff00ff000db200fffb04c6636333399c9cccccc6c6633339399c",
>>
>>        INIT_0B =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0C =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0D =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0E =>
>> X"0000000000000000000000000000000000000000000000000000000000000000",
>>
>>        INIT_0F =>
>> X"0000000000000000000000000000000000000000000000000000000000000000"
>>   )
>> -- synopsys translate_on
>>   port map(
>>        ADDR => ADDR,
>>        CLK => CLK,
>>        DI(0) => GND,
>>        DO(0) => dout(7),
>>        EN => VCC,
>>        RST => GND,
>>        WE => GND
>>   );
>>
>> ---- Power , ground assignment ----
>>
>> GND <= GND_CONSTANT;
>> VCC <= VCC_CONSTANT;
>>
>> end RAm;
>



Article: 39820
Subject: Re: Counter does not fit CPLD?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 20 Feb 2002 16:51:36 +0000
Links: << >>  << T >>  << A >>


Dan Oprisan wrote:

> Hi,
>
> I once configured a Xilinx FPGA using VHDL (it was my diploma thesis). Now I
> built myself a small devellopment board using a small ALTERA EPM7064 CPLD
> for fooling around. I use the free MAX2 PLUS and Leonardo Spectrum software
> provided for free.
>
> I got some very simple designs running, but as it gets slightly complicated,
> it won't fit on the CPLD anymore. Either the CPLD is _really_ small, or I my
> code is really messed up (although the same code would have worked without
> problem on the FPGA).
>
> An example:
> I'm trying to divide the ~40MHz clock to 2^29 in order to see a LED
> blinking. The place & route fails with the message:
>
> Error: Logic cell LED requires too many (30/16) shareable expanders
>
> The code snippet:
>
>      VARIABLE    q      : std_logic_vector(28 DOWNTO 0);
>      SIGNAL      ledbuf : std_logic;
> BEGIN
>
>   PROCESS (CKR)
>   BEGIN
>
>   IF (CKR'EVENT AND CKR = '1') THEN
>       IF (q = "00000000000000000000000000000") THEN
>        q := "10000000000000000000000000000";
>        ledbuf <= NOT ledbuf;
>       ELSE
>        q := q - "00000000000000000000000000001";
>
>       END IF;
>    END IF;
>
>    END PROCESS;
>
> I tried do define q as an integer (and many other things) by I couldn't get
> it work. Anybody knows what the problem is?
>
> Thanks, Dan

To really understand you'll have to get the EPM7K data book and study the
architecure but I'd hazard a guess that the logic functions are just too wide.
For a 29 bit up counter (I know yours is a down but the argument is the same)
the input to the last FF is something like:

XOR (q[28], AND (q[27], ..., q[0]) )

which has a 29 bit fan-in.

Try breaking your counter into 2 or even 4 parts. You could also pipeline the
``wrap'' condition.


Article: 39821
Subject: Re: Need good PCI book
From: steen_junk@yahoo.com (Steen Larsen)
Date: 20 Feb 2002 09:00:04 -0800
Links: << >>  << T >>  << A >>
Shanley/Anderson's _PCI System Architecture_ from Mindshare is the
best I have seen.  The 4th edition has been out sometime, but seems
confusing with making explicit PCI 2.2 spec differences.  The 3rd
edition just presents the facts.

(Personally I like the Mindshare books since they maintain the same
documentation method and waveform notations across all books such as
USB, AGP, ISA, processors)

You should be able to download the full spec from www.pcisig.org.  At
the end there is a sample state machine description that helps
describe master/target transactions.

-Steen
(replace junk with tech for email reply)

"Victor Levandovsky" <vic@elsyst.km.ua> wrote in message news:<a4vrpr$f9k$1@ally.taide.net>...

Article: 39822
Subject: Re: Virtex-II and SDRAM Controller at 133MHz
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Feb 2002 17:10:07 GMT
Links: << >>  << T >>  << A >>
You should be able to pull it off, especially if pipeline latency is not an issue.  We are
doing a 133MHz SDRAM interface as part of a video processor in spartanII for a customer next
month, and are not particularly worried about it.  Make sure your board layout is good, and if
driving more than one chip make sure the lines are properly terminated.  If it is a single
SDRAM on a private interface to the FPGA, you can get probably away without terminators if you
are careful with the board layout and route.

rickman wrote:

> Thanks for the insight. My design is not connecting a micro to the RAM,
> it is a DMA controller from IO devices to/from SDRAM. So the latency is
> not as large of an issue. I will be moving data in blocks of at least 8
> words and maybe as many as 32, so the latency won't be a huge impact on
> the total bus usage time. I will want to minimize the time the DSP is
> kicked off the bus to transfer blocks. Otherwise, it is not an issue.
>
> This is working with a 150 MHz DSP and I was surprized to find that the
> external memory interface will only run up to 100 MHz. I was looking at
> using 133 or 150 MHz memory. I guess I will be able to use the cheap
> stuff.
>
> I have worked with SDRAM before, but we were only running at 33 MHz (PCI
> bus speed). That was an XC4000XL IIRC. 33 MHz was no problem and the
> rest of the circuit running at 50 MHz was no problem. I did basic
> floorplanning for the large blocks (mux/demux, FIFO, memory interface)
> and it worked without problems.
>
> There was one place where I was muxing a clock through the chip (not
> used internally) and I needed a very fast route from the CLB to the IOB
> next to it. The software could not seen the find the optimal route and I
> always had to hand route that one path to save that extra half nS. It
> acutally was not too bad. The chip editor was pretty easy to use and
> there were never any other signals in the way.
>
> Based on what you are saying, I expect with a little floorplanning I
> should have no trouble at 100 MHz. Thanks.
>
> Rick Filipkiewicz wrote:
> >
> > rickman wrote:
> >
> > > Ray,
> > >
> > > I would like to draw on your experience if I can. I am looking at doing
> > > a SDRAM and SBSRAM interface in an XC2SE chip and would like to get an
> > > idea of what speed grade I will need. Turns out that the DSP chip will
> > > only support up to 100 MHz on the memory bus so I won't have to push the
> > > speed much. Will this be easy on the slowest speed grade which seems to
> > > be a -6? Since there only seem to be two speed grades at this time, I
> > > don't expect to see that much difference (and no industrial in the -7).
> > > I can't tell from the data sheet as it does not have data for the -7 yet
> > > (even though I can buy the parts).
> > >
> > > From your experience will a 100 MHz SDRAM interface be easy in a
> > > XC2S200E-6 ?
> > >
> >
> > Rickman,
> >
> > If I might give my experience -
> >
> > I've got 100MHz working in an XCV600E-6 with only the auto P&R tools and (almost) purely
> > synthesised logic - only a couple of places where I've had to instantiate MUXF5s + a lot
> > of ``syn_keep'' constraints to tell Synplify what to do. For us low latency is vital,
> > latency from our MIPS CPU's start of cycle strobe to the first read dataum back at the
> > CPU is 10 clocks. To put this into context the best latency I've seen for an ASIC
> > controller is 9. If the SpartanIIE timing is the same as the original Virtex-E its
> > doable but not easy without floorplanning esp. if the device useage is high.
> >
> > I'm now pushing on to the 133MHz goal in a -7, I've been keeping floorplanning in
> > reserve for this.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39823
Subject: Re: Pseudorandom Bitstream
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Feb 2002 17:13:57 GMT
Links: << >>  << T >>  << A >>
Depends if a) the multiplier is fast enough (it is quite a bit slower than what you can do in the
fabric), and b) if you need the multiplier for something else that might be harder to do than random
number generates.  It is a game of resource allocation to get the most efficient overall design.

Lasse Langwadt Christensen wrote:

> Ray Andraka wrote:
> >
> > Exactly.  In fact, all the LFSR is is a special case of the CRC hardware.  I did't want to
> > confuse the issue, but as you say, you can create a parallel version of the LFST that appears at
> > the outputs to advance N clocks in a single clock.
> >
>
> I'm wondering if it in a VirtexII would makes sense to use a multiplier,
> AFIAR a
> normal way to generate random numbers in SW is something like x[n+1] =
> (x[n]*a + b) % c
>
> -Lasse
>
> > jrc wrote:
> >
> > > It is pretty easy to contruct a state-machine to mimic the effects of
> > > a LFSR shift register that has been clocked an arbitrary number of
> > > times. To use your example the normal logic for X^3+X^2+1 using four
> > > flip-flops is:
> > >
> > > ff0=ff3^ff2^1 (xnor the last two flip-flops in the shift register)
> > > ff1=ff0 (shift)
> > > ff2=ff1 (shift)
> > > ff3=ff2 (shift)
> > >
> > > For each clock, the following design will produce the same four bit
> > > sequence produced by clocking the orignal design four times:
> > >
> > > ff0=ff3^ff2^ff0 (three term xor)
> > > ff1=ff1^ff0^1 (xnor)
> > > ff2=ff2^ff1^1 (xnor)
> > > ff3=ff3^ff2^1 (xnor)
> > >
> > > So the bit sequence for ff0 the upper design is:
> > >
> > > 0111011001010000111...
> > >
> > > The bit sequence for the four flip-flops on second design is:
> > >
> > > 3210
> > > ----
> > > 0111
> > > 0110
> > > 0101
> > > 0000
> > > 1110
> > > ...
> > >
> > > I always called this generating pseudorandom in parallel. It is used a
> > > lot in communications work. Once you get the knack you can generate
> > > any sequence in any width. If you add flip-flops you can actually
> > > generate this sequence 8 bits at a time or even wider.
> > >
> > > JRC
> > >
> > > Ray Andraka <ray@andraka.com> wrote in message news:<3C62A21F.C8BFFA23@andraka.com>...
> > > > No.  The neighboring bits, when taken a byte at a time from an LFSR are time shifted copies
> > > > of previous bits.  If you take more than 1 bit per clock from an LFSR, you lose the uniform
> > > > white properties.  Consider the 4 bit LFSR  X^3+X^2+1:
> > > >
> > > > 0000
> > > > 0001
> > > > 0011
> > > > 0111
> > > > 1110
> > > > 1101
> > > > 1011
> > > > 0110
> > > > 1100
> > > > 1001
> > > > 0010
> > > > 0101
> > > > 1010
> > > > 0100
> > > > 1000
> > > > 0000
> > > >
> > > > Note that only the right most bit is random, the other bits are the same as the rightmost
> > > > but delayed by 1,2 and 3 clocks.  If you use more than one bit per clock from an LFSR, you
> > > > wind up with a correlation that colors the output and destroys the uniform random
> > > > properties.  The bottom line is that an LFSR at 100MHz produces a random BIT stream at 100
> > > > MHz, not a byte stream.  To get a random byte stream, you need to clock the LFSR 8 times
> > > > between samples so as to get new bit values (uncorrelated to any bits in previous sample)
> > > > in all 8 bits, which gives you a random byte stream of 100/8= 12.5 MHz.
> > > >
> > > > vt313@comsys.ntu-kpi.kiev.ua wrote:
> > > >
> > > > > In the LSFR bitstream the bytes of neighboring bits,
> > > > > considered as signed vectors, are practically
> > > > > uncorrelated, and belong to the interval (-1.0 : 1.0).
> > > > > Therefore LSFR generator at 100 MHz
> > > > > provides the byte stream at 100 MHz.
> > > > >
> > > > > If you add couples of neigboring
> > > > > sampling bytes from LSFR,
> > > > > then you get the  approximation
> > > > > of the "triangle" distribution.
> > > > >
> > > > > If you want the Gaussian distribution,
> > > > > then you would add n>10 neigboring
> > > > > sampling bytes from LSFR,
> > > > > and get the rather exact approximation
> > > > > of the Gaussian distribution.
> > > > >
> > > > > Anatoli  S.
> > > >
> > > > --
> > > > --Ray Andraka, P.E.
> > > > President, the Andraka Consulting Group, Inc.
> > > > 401/884-7930     Fax 401/884-7950
> > > > email ray@andraka.com
> > > > http://www.andraka.com
> > > >
> > > >  "They that give up essential liberty to obtain a little
> > > >   temporary safety deserve neither liberty nor safety."
> > > >                                           -Benjamin Franklin, 1759
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
>
> --
> ----------------------------
> - Lasse Langwadt Christensen
> - Aalborg - Danmark

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39824
Subject: Re: Xilinx ISE 3.3 upgrade to 4.1
From: Ray Andraka <ray@andraka.com>
Date: Wed, 20 Feb 2002 17:18:35 GMT
Links: << >>  << T >>  << A >>
Bull-twinkies is right ( I assume that is what b*******s means).  I encourage you to
yell loudly at Xilinx.  Maybe if enough people let them know that there is a problem it
might get solved.  In the mean time, demand a set of current timing files for 3.3sp8.
They exist, but you have to beg your FAE for them, as they are not posted on the
website.  While you are at the yelling, ask Xilinx why the 3.3sp8 speed file updates
are not openly available as a download from the website.

Rick Filipkiewicz wrote:

> hamish@cloud.net.au wrote:
>
> > Rick Filipkiewicz <rick@algor.co.uk> wrote:
> > > Is it possible to use 4.1i speed files when building with 3.3i ? e.g. for an
> > > XCV600E I could just copy over the %XILINX%/virtexe/data/v600e.spd from my 4.1i
> > > installation to my 3.3i one ?
> >
> > No, you'll get error messages about the file format version numbers
> > being different. (I tried it.)
> >
> > Hamish
> > --
> > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
>
> Oh b******s! So its back to the ``exposed butt'' position or use 4.1i.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search