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Messages from 39825

Article: 39825
Subject: Re: Virtex II multiplier pipeline
From: "Seb" <someone@microsoft.com>
Date: Wed, 20 Feb 2002 18:44:51 +0100
Links: << >>  << T >>  << A >>

How did you create the multipliers? I've created mine with CoreGenerator and
was able to choose wheter to use clock or not...among many other options

cheers,
Seb


"Clark Pope" <cepope@mindspring.com> wrote in message
news:a4unt4$tlv$1@slb2.atl.mindspring.net...
> We recently upgraded our foundation ISE with a service pack. Now our
filters
> using the Virtex II embedded multiplies is taking 12 ns instead of the
10ns
> we had before the upgrade.(Which probably reflects more accurate timing) I
> looked at the design in FPGA editor and found that even though the MULT
> component has a clock input our design is not using it(even though we've
> registered the i/o in VHDL).
>
> Does anyone now how to force the tools to use the clock input on the V2
MULT
> component from VHDL?
>
> Thanks,
> Clark
>
>
>



Article: 39826
Subject: Re: Need good PCI book
From: Keith R. Williams <krw@btv.ibm.com>
Date: Wed, 20 Feb 2002 12:48:40 -0500
Links: << >>  << T >>  << A >>
In article <ba62bd8d.0202200900.145d38e6@posting.google.com>, 
steen_junk@yahoo.com says...
> Shanley/Anderson's _PCI System Architecture_ from Mindshare is the
> best I have seen.  The 4th edition has been out sometime, but seems
> confusing with making explicit PCI 2.2 spec differences.  The 3rd
> edition just presents the facts.

I second this recommendation (though I only have the second and fourth 
editions).  The ISBN (4th edition) is 0-201-30974-2.  

If you can find one of their (MindShare) PCI classes it's well worth 
the time.  Don Anderson taught the one I took a few years ago. Without 
a doubt, it was one of the best courses I've taken.  

> (Personally I like the Mindshare books since they maintain the same
> documentation method and waveform notations across all books such as
> USB, AGP, ISA, processors)

The ding I give their books is that the index could be better.  They're 
well organized though, so it's not all that hard to find things.

> You should be able to download the full spec from www.pcisig.org.  At
> the end there is a sample state machine description that helps
> describe master/target transactions.

Don't you have to be a PCI Sig member to download the spec? I thought 
the spec was $100 for non-members. Shanley and Anderson is *far* easier 
to understand anyway.


Article: 39827
Subject: KEEP constraints on std_logic_vector
From: atali@cygrp.com (Aare Tali)
Date: 20 Feb 2002 12:41:18 -0800
Links: << >>  << T >>  << A >>
I'm working on XC95XL design and I need 8-wide multiplexer that has
about 10-12 inputs on each bit. If I assign pins as optimal for the
board layout (next to each other) the logic block runs out of product
terms. To work around this I created 8 extra signals and implemented
5-6 input multiplexers on them, placed them into different logic
blocks, provided some space between them for less product-term-hungry
signals and forced these signals to KEEP (using attribute in VHDL
source). So far so good.
                 __                    __
Some inputs    -|  |----- MUX2 -------|  |--- MUX1 output
Some selects   -|__|   More inputs  --|  |
                       More selects --|__|

But when I look at fitter report I see that I can actually optimize
out one or two of these extra multiplexer bits. One of them was
actually placed into same logic block as the final multiplexer for
this bit, so I could combine at least these two.

WebPack doesn't let me do 'attribute KEEP of Mux2(0) : signal is
"TRUE";'. I've also tried all reasonable and unreasonable ways to put
it into UCF file, so far nothing.

The only way I got it working was to create 8 signals, copy output of
Mux2 into these signals (signal0, signal1...) and feed signals into
Mux1. In this case I can optimize signal0 independently of others.

Is there any less ugly way to do this?

Article: 39828
Subject: PCI/FPGA evaluation board
From: Jesus Molina <chus@cs.umd.edu>
Date: Wed, 20 Feb 2002 16:27:09 -0500
Links: << >>  << T >>  << A >>

Hello,

I am trying to find a PCI / FPGA development  board. I have already seen
some of then at the Xilinx webpage. I will really appreciate some advice,
as I am new to the FPGA world.

In the board I need at least a PCI core, IDE controller core (
both implemented in an FPGA) Flash and SDRAM memory, and a processor
or some type of way to expand the board to add a processor.

Sample boards I have found are the H.O.T II distributed by Virtual
Computer Corporation or the ones distributed by nallatech.
Thanks for your help,

Jesus




Article: 39829
Subject: Re: Counter does not fit CPLD?
From: kayrock66@yahoo.com (Jay)
Date: 20 Feb 2002 13:38:48 -0800
Links: << >>  << T >>  << A >>
Your problem is that you're doing a very wide compare and the software
is attempting to do it all in a single level of logic to meet the
rated speed of the part.  If you really want to do such a wide
compare, you can try writting the code in a more structural fashion to
use 2 levels of logic.  Or, if you just want to make your LED blink,
hook it up to the MSB of your free running counter.

Regards

"Dan Oprisan" <dandy1313@yahoo.com> wrote in message news:<a50e64$shn$1@nathan.rz.tu-harburg.de>...
> Hi,
> 
> I once configured a Xilinx FPGA using VHDL (it was my diploma thesis). Now I
> built myself a small devellopment board using a small ALTERA EPM7064 CPLD
> for fooling around. I use the free MAX2 PLUS and Leonardo Spectrum software
> provided for free.
> 
> I got some very simple designs running, but as it gets slightly complicated,
> it won't fit on the CPLD anymore. Either the CPLD is _really_ small, or I my
> code is really messed up (although the same code would have worked without
> problem on the FPGA).
> 
> An example:
> I'm trying to divide the ~40MHz clock to 2^29 in order to see a LED
> blinking. The place & route fails with the message:
> 
> Error: Logic cell LED requires too many (30/16) shareable expanders
> 
> The code snippet:
> 
>      VARIABLE    q      : std_logic_vector(28 DOWNTO 0);
>      SIGNAL      ledbuf : std_logic;
> BEGIN
> 
>   PROCESS (CKR)
>   BEGIN
> 
>   IF (CKR'EVENT AND CKR = '1') THEN
>       IF (q = "00000000000000000000000000000") THEN
>        q := "10000000000000000000000000000";
>        ledbuf <= NOT ledbuf;
>       ELSE
>        q := q - "00000000000000000000000000001";
> 
>       END IF;
>    END IF;
> 
>    END PROCESS;
> 
> I tried do define q as an integer (and many other things) by I couldn't get
> it work. Anybody knows what the problem is?
> 
> Thanks, Dan

Article: 39830
Subject: Re: gate array
From: kayrock66@yahoo.com (Jay)
Date: 20 Feb 2002 13:53:00 -0800
Links: << >>  << T >>  << A >>
You would use your verilog (hopefully unchanged) to synthesis to your
gate array vendor's cell library output at an EDIF netlist.  Expect
differences in memory I/O's, clocking and reset.  If there are
changes, use the same design database but use parameters and defines
to maintain the differences between the 2 technologies.  And your
current test bench would be used for verification on your post synth
netlists.  DON'T USE PROBES in your test bech like
mydesign.level1.level2.mysignal, they aren't meaningfull in gate level
simulations.

Regards

"svhb" <svhb@pandora.be> wrote in message news:<3c73ae41$0$12223$4d4efb8e@news.be.uu.net>...
> Hi,
> 
> I've done a design in a SpartanXL 30, what is the best way to convert it to
> a gate array, from the verilog code or from the edif output from the
> complete placed and routed FPGA?
> 
> The design is fully synchronous. I have a testbench in verilog, but because
> the desing is using a rather complex serial interface, it takes long to
> simulate. Is a verilog testbench appropriate to do the simulations during
> asic development?
> 
> Thanks

Article: 39831
Subject: Re: Xilinx IP Core multiplier performance
From: Przemyslaw Wegrzyn <czajnik@czajsoft.pl>
Date: Thu, 21 Feb 2002 00:07:45 +0100
Links: << >>  << T >>  << A >>



> Anyway, the coregen multipliers are better in terms of both density and speed than the average designer is
> likely to turn out.  Unless you are wanting to learn the details of the multiplier, go ahead and use the
> core.  You won't go far wrong, and in most cases it is plenty fast.

Thanx for your answer. BTW, I can't find any info on what type of multiplier does the coregen create.
Again, is Booth method a way to improve performance of multipliers implemented in _FPGA_  ?

-=Czaj-nick=-




Article: 39832
Subject: Re: Need good PCI book
From: steen_junk@yahoo.com (Steen Larsen)
Date: 20 Feb 2002 15:08:45 -0800
Links: << >>  << T >>  << A >>
Keith, thanks for the correction.
-Steen

Keith R. Williams <krw@btv.ibm.com> wrote in message news:<MPG.16ddab65a423de39989730@enews.newsguy.com>...
> In article <ba62bd8d.0202200900.145d38e6@posting.google.com>, 
> steen_junk@yahoo.com says...
> > Shanley/Anderson's _PCI System Architecture_ from Mindshare is the
> > best I have seen.  The 4th edition has been out sometime, but seems
> > confusing with making explicit PCI 2.2 spec differences.  The 3rd
> > edition just presents the facts.
> 
> I second this recommendation (though I only have the second and fourth 
> editions).  The ISBN (4th edition) is 0-201-30974-2.  
> 
> If you can find one of their (MindShare) PCI classes it's well worth 
> the time.  Don Anderson taught the one I took a few years ago. Without 
> a doubt, it was one of the best courses I've taken.  
> 
> > (Personally I like the Mindshare books since they maintain the same
> > documentation method and waveform notations across all books such as
> > USB, AGP, ISA, processors)
> 
> The ding I give their books is that the index could be better.  They're 
> well organized though, so it's not all that hard to find things.
> 
> > You should be able to download the full spec from www.pcisig.org.  At
> > the end there is a sample state machine description that helps
> > describe master/target transactions.
> 
> Don't you have to be a PCI Sig member to download the spec? I thought 
> the spec was $100 for non-members. Shanley and Anderson is *far* easier 
> to understand anyway.

Article: 39833
Subject: Re: Need good PCI book
From: Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com>
Date: Wed, 20 Feb 2002 17:37:29 -0600
Links: << >>  << T >>  << A >>
You probably have to be more specific on what you really want.
"Need a good PCI book" is a vague answer, and you should explain what
you are trying to accomplish.
I will assume that you are trying to develop a PCI IP core an FPGA for
some kind of project you are working on.
        Most of the time, the standard answer you will get is to
purchase a copy of PCI Local Bus Revision 2.2 Specification from PCISIG
(about $40 + shipping http://www.pcisig.com), PCI System Architecture
4th Edition ($39.95 ISBN 0-201-30974-2), or PCI Hardware and Software
4th Edition (Annabooks about $100 ISBN 092939259-0).
However, the problem with the existing books about PCI bus is that they
pretty much discuss the bus protocol only, and not the most important
part on how to implement a PCI interface.
Like someone else who already replied to your question, PCI Local Bus
Revision 2.2 Specification Appendix B has a sample state machine
diagram, so you will likely start from there, but that won't cover the
details of the actual PCI IP core implementation.
Since there are almost no good books available on the implementation
side of a PCI IP core, there will be a lot of trial and error during the
design, and I went through that during the development of my PCI IP core
(Although my PCI IP core is still not completely done yet.).
Also, if you are going to do this with an FPGA, you will have to have a
good understanding of the target architecture.
Example of that will be delays of various internal resources,
interconnect structure, and I/O pad FF merging rules.
If you don't design the logic carefully, you won't meet 33MHz PCI's 7ns
setup time, even with relatively new FPGAs like Virtex/Spartan-II.
Using a floorplanning tool is likely going to be another must even for a
33MHz PCI IP core to meet 7ns setup time.



Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)

Article: 39834
Subject: Re: PCI/FPGA evaluation board
From: Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com>
Date: Wed, 20 Feb 2002 17:38:57 -0600
Links: << >>  << T >>  << A >>
I cannot think of a board that totally satisfies your requirements, but
if you don't need to have IDE or Flash memory, Insight Electronics
Spartan-II PCI Development Kit is a good choice.

http://208.129.228.206/solutions/kits/xilinx/ 


The hardware alone will cost only $145, but the problem is that either
you will have to license Spartan-II PCI IP core from Xilinx which costs
$2,000, obtain a PCI IP core from somewhere other than Xilinx, or you
will have to develop your own PCI IP core.
Opencore.org (http://www.opencore.org) has a PCI IP core project of
their own going on for some time, and they have a working sample design
with their PCI IP core, but they also seem to admit that their PCI IP
core is not fully debugged.
If you are not happy with Opencore.org PCI IP core, and will have to
develop your own PCI IP core, I will say that it is possible to develop
your own with Xilinx's free ISE WebPACK since I have been doing so for
some time, and I actually got my design to work when plugged my Insight
Electronics Spartan-II PCI board into a real computer.
Probably the hardest part of a PCI IP core design is to design the logic
carefully, so that it will meet 33MHz PCI's unforgiving 7ns setup time.
Automatic P&R tool will almost certainly not meet 7ns setup time at
least for Spartan-II speed grade -5 because is not very good in grouping
relavent LUTs, and placing them at the correct location.
You will definitely have to use Floorplanner to place some timing
critical LUTs manually.
Good understanding of a Virtex architecture (Delays of various internal
resources, Virtex's interconnect structure, and IOB FF merging rules.) 
is essential, and justing being able to do some synthesizable HDL coding
is definitely not enough to meet 7ns setup time.
You will have to know (Or learn through trial and error.) HDL coding
techniques that minimizes the levels of logic for a Virtex architecture
FPGA.
However, it is probably possible to develop a sort of working (setup
time of 10 to 12ns) target mode only PCI IP in probably 2 to 3 months,
but fully debugging it with getting the 7ns setup time right might take
many more months.




Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)




Jesus Molina wrote:
> 
> Hello,
> 
> I am trying to find a PCI / FPGA development  board. I have already seen
> some of then at the Xilinx webpage. I will really appreciate some advice,
> as I am new to the FPGA world.
> 
> In the board I need at least a PCI core, IDE controller core (
> both implemented in an FPGA) Flash and SDRAM memory, and a processor
> or some type of way to expand the board to add a processor.
> 
> Sample boards I have found are the H.O.T II distributed by Virtual
> Computer Corporation or the ones distributed by nallatech.
> Thanks for your help,
> 
> Jesus

Article: 39835
Subject: Re: PCI/FPGA evaluation board
From: Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com>
Date: Wed, 20 Feb 2002 17:40:37 -0600
Links: << >>  << T >>  << A >>
I meant Opencores.org (http://www.opencores.org).



Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)

Article: 39836
Subject: Re: PCI/FPGA evaluation board
From: Jesus Molina <chus@cs.umd.edu>
Date: Wed, 20 Feb 2002 19:35:40 -0500
Links: << >>  << T >>  << A >>

Hello,

> Spartan-II PCI Development Kit is a good choice.>
> http://208.129.228.206/solutions/kits/xilinx/

They are not selling them any more, I called and they are working in a new
PCI card.

> Opencore.org (http://www.opencore.org) has a PCI IP core project of
> their own going on for some time, and they have a working sample design
> with their PCI IP core, but they also seem to admit that their PCI IP
> core is not fully debugged.

Thanks for the insightfull review. The IP cores is less expensive for
research (500$) However, as I am planningto use the opencore IDE driver,
it will be interesting to check the PCI core too.

Thanks again,

Jesus


Article: 39837
Subject: Re: PCI/FPGA evaluation board
From: Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com>
Date: Wed, 20 Feb 2002 19:21:12 -0600
Links: << >>  << T >>  << A >>
Jesus Molina wrote:
> 
> Hello,
> 
> > Spartan-II PCI Development Kit is a good choice.>
> > http://208.129.228.206/solutions/kits/xilinx/
> 
> They are not selling them any more, I called and they are working in a new
> PCI card.
> 

        Wow!
Considering the price, it was a really good board, so I am surprised
that Insight Electronics discontinued it.
Hopefully, the new card will also have a larger Spartan-II like XC2S200,
and a faster -6 speed grade because Virtex/Spartan-II are the fastest
and the last FPGAs that can handle 5V PCI.
Virtex-II/Virtex-E/Spartan-IIE don't support 5V PCI (3.3V PCI is
supported though, but almost no PC motherboards support it.) without an
external voltage level conversion chip.




> > Opencore.org (http://www.opencore.org) has a PCI IP core project of
> > their own going on for some time, and they have a working sample design
> > with their PCI IP core, but they also seem to admit that their PCI IP
> > core is not fully debugged.
> 
> Thanks for the insightfull review. The IP cores is less expensive for
> research (500$) However, as I am planningto use the opencore IDE driver,
> it will be interesting to check the PCI core too.
> 
> Thanks again,
> 
> Jesus


        $500 doesn't sound too bad, but I guess that depends on your
budget.
I suppose for a personal project, even $500 is too much.
Looking at various IP cores at Opencores.org, I won't totally count on
the quality of the IP cores listed there.
If the quality of the IP cores are so bad, it might be faster/easier to
develop your own.
A lot of them seem don't seem to be fully debugged, and regarding
Opencores.org PCI IP core, there is no mention of whether or not it can
meet 7ns setup time for 33MHz PCI.
If the logic is designed carefully, it probably will meet 7ns setup
time, but that will likely be after some floorplanning.
Again, that will depend on how many levels of logic unregistered signal
paths have.




Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)

Article: 39838
Subject: Re: Do I need to install software in order to use Multilinx?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Feb 2002 03:14:12 GMT
Links: << >>  << T >>  << A >>
The web pack only supports the JTAG programming with parallel III.  If you
want to use the other programming features of multilinx, I'm afraid you are
stuck doing an install of 3.3 or 4.1.  Once there was a time when you could
load up the device programmer (in those days hardware debugger) without
having to load up the full xilinx tools, which was really nice for those of
us (most everyone I've worked with)  who do not have their development
machine in the lab with the actual hardware.  Now, if you are like most,
you have to violate the terms of the license to install a second instance
on your lab machine...that is if it will even fit.  *SIGH*

Falk Brunner wrote:

> <ZhengLin> schrieb im Newsbeitrag news:ee74e92.0@WebX.sUN8CHnE...
> > Just use foundatation 4.1!
>
> NO, just install the JTAG-Programmer from Webpack, it will automaticall
> install the parallel cable driver.
>
> --
> MfG
> Falk

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39839
Subject: Re: Do I need to install software in order to use Multilinx?
From: "X. Q." <qijun@okigrp.com.sg>
Date: Thu, 21 Feb 2002 11:32:55 +0800
Links: << >>  << T >>  << A >>
Thanks for your comments.
Here my problem is that, after I connect thePWR and GND pins from a
MultiLinx cable
onto my board, the power supply indicates there is a short circuits. The
resistance between
the PWR and GND is near zero on a multimeter.
This happens even after I invoked ISE 4.1 and such. It wasn't able to
program. It's obvious
that ISE 4.1 didn't control the multilinx.

Qijun






"Ray Andraka" <ray@andraka.com> wrote in message
news:3C746704.42C6438D@andraka.com...
> The web pack only supports the JTAG programming with parallel III.  If you
> want to use the other programming features of multilinx, I'm afraid you
are
> stuck doing an install of 3.3 or 4.1.  Once there was a time when you
could
> load up the device programmer (in those days hardware debugger) without
> having to load up the full xilinx tools, which was really nice for those
of
> us (most everyone I've worked with)  who do not have their development
> machine in the lab with the actual hardware.  Now, if you are like most,
> you have to violate the terms of the license to install a second instance
> on your lab machine...that is if it will even fit.  *SIGH*
>
> Falk Brunner wrote:
>
> > <ZhengLin> schrieb im Newsbeitrag news:ee74e92.0@WebX.sUN8CHnE...
> > > Just use foundatation 4.1!
> >
> > NO, just install the JTAG-Programmer from Webpack, it will automaticall
> > install the parallel cable driver.
> >
> > --
> > MfG
> > Falk
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 39840
Subject: Re: Xilinx IP Core multiplier performance
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Feb 2002 03:34:11 GMT
Links: << >>  << T >>  << A >>
Coregen creates one of the "computed partial products" multipliers, depending on the family.  In XC4000, it does
it as shown in the computed partial products to get a 2xN partial.  For the virtex families, it uses special
logic in the carry chain to compact the size of the 2xN computed partial product, which is shown in my
multipliers page.

Przemyslaw Wegrzyn wrote:

> > Anyway, the coregen multipliers are better in terms of both density and speed than the average designer is
> > likely to turn out.  Unless you are wanting to learn the details of the multiplier, go ahead and use the
> > core.  You won't go far wrong, and in most cases it is plenty fast.
>
> Thanx for your answer. BTW, I can't find any info on what type of multiplier does the coregen create.
> Again, is Booth method a way to improve performance of multipliers implemented in _FPGA_  ?
>
> -=Czaj-nick=-

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39841
(removed)


Article: 39842
Subject: Need largest CPLD devices?
From: "X. Q." <qijun@okigrp.com.sg>
Date: Thu, 21 Feb 2002 11:38:07 +0800
Links: << >>  << T >>  << A >>
I built my design with Spartan-II. Now the research centre in another
country
needs my design. Let's pressume they don't have any expertise in FPGA and
such, while they want my design. How can I transport my design to them? My
design is 10K gates in ASIC. Can I get any CPLD which can hold this design?
I understand FPGA dies after I unplug the power.

Best Regards
XQ.




Article: 39843
Subject: Re: Do I need to install software in order to use Multilinx?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Feb 2002 03:49:52 GMT
Links: << >>  << T >>  << A >>
SOunds like a problem with your multilinx cable.  It shouldn't short even if it
is not connected to the computer.  Check to make sure you got the proper
polarity of the power cables.  Also check that it isn't a problem of a short
through system grounds.

"X. Q." wrote:

> Thanks for your comments.
> Here my problem is that, after I connect thePWR and GND pins from a
> MultiLinx cable
> onto my board, the power supply indicates there is a short circuits. The
> resistance between
> the PWR and GND is near zero on a multimeter.
> This happens even after I invoked ISE 4.1 and such. It wasn't able to
> program. It's obvious
> that ISE 4.1 didn't control the multilinx.
>
> Qijun
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3C746704.42C6438D@andraka.com...
> > The web pack only supports the JTAG programming with parallel III.  If you
> > want to use the other programming features of multilinx, I'm afraid you
> are
> > stuck doing an install of 3.3 or 4.1.  Once there was a time when you
> could
> > load up the device programmer (in those days hardware debugger) without
> > having to load up the full xilinx tools, which was really nice for those
> of
> > us (most everyone I've worked with)  who do not have their development
> > machine in the lab with the actual hardware.  Now, if you are like most,
> > you have to violate the terms of the license to install a second instance
> > on your lab machine...that is if it will even fit.  *SIGH*
> >
> > Falk Brunner wrote:
> >
> > > <ZhengLin> schrieb im Newsbeitrag news:ee74e92.0@WebX.sUN8CHnE...
> > > > Just use foundatation 4.1!
> > >
> > > NO, just install the JTAG-Programmer from Webpack, it will automaticall
> > > install the parallel cable driver.
> > >
> > > --
> > > MfG
> > > Falk
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39844
Subject: Problem While Downloading to Spartan 2 FPGA using JTAG
From: yatiks@yahoo.com (Kumar)
Date: 20 Feb 2002 22:54:46 -0800
Links: << >>  << T >>  << A >>
Hi,

        I am using B5 Spartan2+ Board from Bruch Electronics Designs
containing XC2s200-5PQ208 FPGA .Xilinx ISE BASEX software .Impact
Programing tool (Downloading mode JTAG).Synthesis and implimentation
through FPGA Express .PC Configuration P4 1.7GHz with 850 chipset from
Intel.

Problem : I have not faced any problem till generating Bit files.While
       Downloading the bit file to FPGA ( XC2s200-5PQ208 ) through
JTAG ,I am facing a problem "Cable connection failed. Elapsed time =  
  23 sec" . and getting a warning error
WARNING:iMPACT:547 - Can not find cable, please check cable setup !

		Then I connected the same Board to other PC with less speed( config
--366 Mhz Celeron ) I have not faced any problem in programming the
FPGA ( XC2s200-5PQ208 ) through JTAG with same cable (length = appr 5
feet).

  Can anybody tell what is causing the problem (is the speed of the PC
or something else)  and also how can I solve this problem ????????

regards
Yathish Kumar
yatiks@yahoo.com

Article: 39845
Subject: Re: Need largest CPLD devices?
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Thu, 21 Feb 2002 07:56:58 +0100
Links: << >>  << T >>  << A >>
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

"X. Q." <qijun@okigrp.com.sg> skrev i meddelandet
news:3c746c0c@news.starhub.net.sg...
> I built my design with Spartan-II. Now the research centre in another
> country
> needs my design. Let's pressume they don't have any expertise in FPGA and
> such, while they want my design. How can I transport my design to them? My
> design is 10K gates in ASIC. Can I get any CPLD which can hold this
design?
> I understand FPGA dies after I unplug the power.
>
> Best Regards
> XQ.
>
>

Why not send them an FPGA + a Preprogrammed Configurator?
- An Atmel AT17 is always appreciated :-)
--
Best Regards
Ulf at atmel dot com




Article: 39846
Subject: Re: FPGA choices and questions
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Thu, 21 Feb 2002 08:03:07 +0100
Links: << >>  << T >>  << A >>
>
> Does that mean that the JTAG-ICE will support debug with the device in a
> scan chain? I am interested in using the AVR ATmega64 or 128 in a design
> with boundary scan and a couple of FPGAs. But I am being told even
> though the ATmega chips support boundary scan and JTAG debug, the
> software doesn't support JTAG debug with the chip in a scan chain!!!
> Boundary scan without a scan chain does not make a lot of sense.
>
> It would make some sense that when they change the software to handle
> the two devices in one chip, they might fix the software to handle a
> chip in a scan chain as well...
>

Current "normal" AVR parts needs to be the  first part in the scan chain for
it to work
for boundary scan.
I hope to see some development here in the future :-)

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.




Article: 39847
Subject: Re: Virtex-E BRAM timing
From: "H.L" <alphaboran@yahoo.com>
Date: Thu, 21 Feb 2002 09:17:15 +0200
Links: << >>  << T >>  << A >>
Thanks Peter and Jay.

"H.L" <alphaboran@yahoo.com> wrote in message
news:a4t9p2$hog$1@ulysses.noc.ntua.gr...
> Hello all,
> I know that this issue is well discussed in this newsgroup but still I
have
> some questions.
> In a Virtex-E FPGA the setup time for the EN,WE signals are 2.5 ns and
2.2ns
> (plz confirm) but the setup time for the address,data is about 1.1ns (plz
> confirm). I want to use 3 BRAMs 128x32  in a Virtex-E 600 (speed grade 6)
@
> 77 MHz (or clock period=12ns), do I have to keep the "input" signals
stable
> for 2 clock periods to succeed a correct timing in the read/write
operations
> or is it totally wrong (except for too slow)?
>
> Best Regards,
> Harris
>
>



Article: 39848
Subject: SRL16E Initialization
From: AT <antonin.hegar@tescan.cz>
Date: Thu, 21 Feb 2002 00:16:53 -0800
Links: << >>  << T >>  << A >>
Hallo,

I would like to make divider by 32 from SRL16E of SpartanII, but
translate occurs this error (WebPack 4.1):
    "logical block 'divog' with type 'srl16e0' is unexpanded"

 divG: SRL16E
    generic map(INIT => X"8000")
    port map ( D => inter(1), CE => Enable, CLK => Clock,
       A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3),
       Q => inter(0));

 divoG: SRL16E
   generic map(INIT => X"0000")
   port map ( D => inter(0), CE => Enable, CLK => Clock,
      A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3),
      Q => inter(1));

Is it impossible initialize SRL16Es by different values?
Thanks.
AT

Article: 39849
Subject: Re: Some problem initializing a RAMB4S1
From: dottavio@ised.it (Antonio)
Date: 21 Feb 2002 00:17:45 -0800
Links: << >>  << T >>  << A >>
Thank you Brian this is the answer I was waiting for.


                   Antonio



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