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Messages from 39850

Article: 39850
Subject: Re: Need good PCI book
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 21 Feb 2002 00:20:26 -0800
Links: << >>  << T >>  << A >>
Kevin Brace <ihatespamkevinbraceusenet@ihatespamhotmail.com> writes:
> Since there are almost no good books available on the implementation
> side of a PCI IP core,

Is that "almost no", or just "no"?  If you know of one, by all means please
let us know.  :-)

Article: 39851
Subject: Re: Orca FPSC synthesizing issue
From: c.heise@tu-bs.de (Carsten)
Date: 21 Feb 2002 08:48:26 GMT
Links: << >>  << T >>  << A >>
Thanks for your efforts.
I need to include the VHDL netlist (which defines only the I/Os of the 
core) to be able to connect my design to the core. This is according to the 
FPSC design flow as shown in the documentation. Next step is to export an 
EDIF netlist from Viewdraw. This EDIF netlist and the VHDL netlist of the 
core are the source files in FPGA Express that I use to synthesize the 
design. Following step is to export an EDIF netlist from FPGA Express and 
im port it into the Orca Foundry.


rickman <spamgoeshere4@yahoo.com> wrote in
news:3C72858F.520A6C49@yahoo.com: 

> I am not clear about what you are trying to do. If you want to create a
> bit stream, then why do you need to include VHDL for the embedded
> PCI-Core? This part is already in the silicon and should not be
> represented in the bit stream.
> 
> If you are trying to perform simulation, I expect you should do this
> before you synthesize. You will need some form of model for the
> PCi-Core. If you translate the schematic to VHDL, then your VHDL for
> the PCI-Core should be a module in the VHDL that is produced. 
> 
> But the fact that you are trying to produce an EDIF netlist says to me
> that you are doing the former rather than the later. So why are you
> trying to include the PCI-Core in the bit stream?

Article: 39852
Subject: Re: Do I need to install software in order to use Multilinx?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 21 Feb 2002 08:53:57 +0000
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

<snip>

> load up the device programmer (in those days hardware debugger) without
>

<end snip>

It appears that the hardware debugger has vanished from 4.1i. Have Xilinx
abandoned it in favour of JBits and/or ChipScope ?




Article: 39853
Subject: Re: PCI/FPGA evaluation board
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 21 Feb 2002 09:04:55 +0000
Links: << >>  << T >>  << A >>


Kevin Brace wrote:

>
> Virtex-II/Virtex-E/Spartan-IIE don't support 5V PCI (3.3V PCI is
> supported though, but almost no PC motherboards support it.) without an
> external voltage level conversion chip.

I shouldn't worry too much about the 3v3 vs. 5v PCI problem. Our Virtex-E board
works fine with 5V PCI cards, all we added is a bunch of QuickSwitch type parts
to protect the non-5V tolerant Viretx-E IOs [Xilinix recommends 100Rs for this
but QS parts are less interfering].

I checked out the PCI signals coming from the FPGA looked like at various points
along the PCI bus using a DSO and they easily made the 5V transition point
within the 33MHz PCI timing spec. In fact there was margin to spare since IIRC
the clock-to-final-crossing was about 13.5nsec. In fact there was no reflection
step that I could see even though the PCI is an unterminated, first reflection,
bus.



Article: 39854
Subject: Re: CLKDLL x4 problem
From: David Bishop <dbishop@vhdl.org>
Date: Thu, 21 Feb 2002 14:30:12 GMT
Links: << >>  << T >>  << A >>


Tim wrote:
> 
> Starting from a 10MHz clock, you can use Peter's circuit to double
> to 20MHz, then run the faster clock through the DLL.  Still outside
> limits, but will almost certainly work on the bench - stick to
> 25MHz in shipping product.

It turns out that the ES parts will lock on less than 20 MHz, with
a special "tweek" from Xilinx.  Supposedly there will be a tactical
patch for this.  Also, look at the erratta sheets!  Some of the ES
parts have problems locking on the FX output of a DCM.


-- 
NAME:     David W. Bishop           INTERNET: dbishop@vhdl.org  (  \  )
US MAIL:  Hilton NY                 A Long time ago,             \__\/
PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
For Supernova info:  http://www.RochesterAstronomy.org/snimages/  | |
For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
All standard disclaimers apply.                                [_______]

Article: 39855
Subject: FPGA'2002: JOIN US SUNDAY
From: tessier@spock.ecs.umass.edu (Russell Tessier)
Date: 21 Feb 2002 14:46:51 GMT
Links: << >>  << T >>  << A >>
FPGA 2002 Final Program and Information
ACM/SIGDA Tenth International Symposium on Field Programmable Gate Arrays
Sponsored by ACM/SIGDA
with support from Actel, Cypress Semiconductor, Altera and Xilinx
Monterey Beach Hotel, Monterey, California
February 24-26, 2002

web site: http://www.ecs.umass.edu/ece/fpga2002/

Please join us THIS COMING SUNDAY for the annual FPGA symposium. 

Highlights include:

- 26 top technical papers covering cutting-edge research
- numerous poster sessions for discussion and meeting with colleagues
- new, scenic symposium location at the Monterey Beach Hotel
- Monday night banquet at the Monterey Aquarium

Hope to see you there!

----------------------------------------------------------------

PROGRAM
--------------------
SUNDAY, February 24, 2002

6:00PM	Registration
7:00PM  Welcoming Reception

MONDAY, February 25, 2002

7:30AM  Continental Breakfast and Registration
8:20AM  Opening Remarks, Martine Schlag, Steve Trimberger

Session 1. Interconnect Architecture
Chair: Steve Wilton, University of British Columbia
8:30AM  Interconnect Enhancements for a High-Speed PLD Architecture, 
        Michael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, 
        Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, 
        Sergey Shumarayev, Altera
8:50AM  FPGA Switch Block Layout and Evaluation, Herman Schmit, Vikas
        Chandra, Carnegie Mellon University
9:10AM  Circuit Design of FPGA Routing Switches, Guy G. Lemieux, 
        David M. Lewis, University of Toronto

9:30AM  Coffee Break and Poster Presentations

Session 2. Arithmetic
Chair: Tom Kean, Algotronix
10:30AM A Faster Distributed Arithmetic Architecture for FPGAs, 
        Radhika S. Grover, Weijia Shang, Qiang Li, Santa Clara University
10:50AM Efficient Architectures for Implementing Montgomery Modular 
        Multiplication and RSA Modular Exponentiation on
        Reconfigurable Logic, Alan Daly, Liam Marnane, University 
        College, Cork
11:10AM A Flexible Floating-Point Format for Optimizing Data-Paths and
        Operators in FPGA Based DSPs, J. Dido, N. Geraudie, L.
        Loiseau, O. Payeur, Y. Savaria, École Polytechnique de Montréal; 
        D. Poirier, Miranda Technologies, Inc.

11:30 AM Poster Presentations
12:00 N  Lunch

Session 3. Physical Design
Chair: Russ Tessier, University of Massachusetts - Amherst
1:30PM Efficient Circuit Clustering for Area and Power Reduction in 
       FPGAs, Amit Singh, Malgorzata Marek-Sadowska, University 
       of California, Santa Barbara
1:50PM Integrated Retiming and Placement for Field Programmable Gate 
       Arrays, Deshanand P. Singh, Stephen D. Brown, University of Toronto
2:10PM SPFD-Based Global Rewiring, Jason Cong, Yizhou Lin, Wangning
       Long, University of California, Los Angeles
2:30PM Eve: A CAD Tool for Manual Placement and Pipelining Assistance 
       of FPGA Circuits, William Chow, Jonathan Rose, University of Toronto

2:50PM Coffee Break and Poster Presentations

Session 4.  Cellular and Cryptographic Applications
Chair: Scott Hauck, University of Washington
3:50PM Application of FPGA Technology to Accelerate the 
       Finite-Difference Time-Domain (FDTD) Method, Ryan N. Schneider, 
       Laurence E. Turner, Michal M. Okoniewski, University of Calgary
4:10PM FPGA Implementation of Neighborhood-of-Four Cellular Automata 
       Random Number Generators, Barry Shackleford, Motoo Tanaka, 
       Richard J. Carter, Greg Snider, Hewlett-Packard
4:30PM Cryptographic Rights Management of FPGA Intellectual Property 
       Cores, Tom Kean, Algotronix
4:50PM Poster Presentations

6:30PM Busses Depart for Monterey Bay Aquarium
7:00PM-11:00PM Dinner at the Monterey Bay Aquarium

TUESDAY, February 26, 2002

7:30 AM Breakfast

Session 5. Synthesis, Verification and Test
Chair: Jason Cong, UCLA
8:30AM Constrained Clock Shifting for Field Programmable Gate Arrays, 
       Deshanand P. Singh, Stephen D. Brown, University of Toronto
8:50AM Timing Verification of Dynamically Reconfigurable Logic for 
       the Xilinx Virtex FPGA Series, Ian Robertson, University of 
       Strathclyde; David Robinson, The Alba Centre; James Irvine, 
       University of Strathclyde
9:10AM FPGA Test Time Reduction Through a Novel Interconnect Testing
       Scheme, Stuart McCracken, Zeljko Zelic, McGill University

9:30AM Coffee Break and Poster Presentations

Session 6.  Architecture Analysis and Automation
Chair: Vaughn Betz, Altera
10:30AM On the Sensitivity of FPGA Architectural Conclusions to 
        Experimental Assumptions, Tools and Techniques, Andy Yan, Rebecca
        Cheng, Steven Wilton, University of British Columbia
10:50AM Dynamic Power Consumption in Virtex-II FPGA Family, Li Shang, 
        Princeton University; Alireza S. Kaviani, Kusuma Bathala, Xilinx, Inc.
11:10AM Automatic Layout of Domain-Specific Reconfigurable Subsystems 
        for System-on-a-Chip, Shawn Phillips, Scott Hauck, 
        University of Washington 

11:30AM Poster Presentations

12:00 N Lunch

Session 7.  Software for Reconfigurable Systems
Chair: Miriam Leeser, Northeastern University
1:30PM Performance-Constrained Pipelining of Software Loops onto 
       Reconfigurable Hardware, Greg Snider, Hewlett-Packard
1:50PM Configuration Prefetching Techniques for Partial Reconfigurable 
       Coprocessor with Relocation and Defragmentation, Zhiyuan Li, 
       Northwestern University; Scott Hauck, University of Washington
2:10PM Analysis of Quasi-Static Scheduling Techniques in a Virtualized 
       Reconfigurable Machine, Yury Markovskiy, Eylon Caspi, Randy
       Huang, Joseph Yeh, Michael Chu, University of California 
       Berkeley; André DeHon, Caltech; John Wawrzynek, University of 
       California, Berkeley
2:30PM Incremental Reconfiguration of Multi-FPGA Systems, K.K. Lee, 
       Synopsys; D.F. Wong, University of Texas at Austin

2:50PM Coffee Break and Poster Presentations

Session 8.  Innovative Applications
Chair: Ray Andraka, Andraka Consulting Group
3:50PM Parallel-Beam Backprojection: An FPGA Implementation Optimized 
       for Medical Imaging, Srdjan Coric, Miriam Leeser, Eric Miller, 
       Northeastern University; Marc Trepanier, Mercury Computer Systems
4:10PM A Dynamically Reconfigurable Adaptive Viterbi Decoder, 
       Sriram Swaminathan, Russell Tessier, Dennis Goeckel, 
       Wayne Burleson, University of Massachusetts, Amherst
4:30PM Data Reorganization Engines for the Next Generation of
       System-On-a-Chip FPGAs, Pedro Diniz, Joonseok Park, University 
       of Southern California/ISI

4:50PM Closing Remarks,  Martine Schlag, Steve Trimberger

Article: 39856
Subject: Re: Do I need to install software in order to use Multilinx?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Feb 2002 14:57:45 GMT
Links: << >>  << T >>  << A >>
They replaced it with something called "iMPACT".  I haven't used it yet, so I
can't tell you how good/bad it is.  It does still require you to do a full
xilinx install to be able to download devices :-(

Rick Filipkiewicz wrote:

> Ray Andraka wrote:
>
> <snip>
>
> > load up the device programmer (in those days hardware debugger) without
> >
>
> <end snip>
>
> It appears that the hardware debugger has vanished from 4.1i. Have Xilinx
> abandoned it in favour of JBits and/or ChipScope ?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39857
Subject: Re: Virtex-E BRAM timing
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Feb 2002 15:02:03 GMT
Links: << >>  << T >>  << A >>


Jay wrote:

> I'm not sure if I understand what you are trying to accomplish but
> I'll take a SWAG at answering your question:
>
> Step 1) Use the BRAM in synchronous mode

You have no choice in this matter.  BRAM is synchronous regardless of what you do to it.

The input setup times are relative to the BRAM clock.  The BRAM clock should generally be
the same free-running clock that is used in the logic associated with the BRAM port (eg, the
address counters, enable logic etc).  If you do that, even the relatively slow ena and we
setup times are easily met at a 77 MHz system clock speed.

>
> Step 2) Drive the inputs to the BRAM with F/F's clocked with the same
> clock as the BRAM
> Step 3) Let the P&R tool worry about metting set/hold issues after
> you've selected a topology that is easily handled by the tool set.
>
> Regards!
>
> "H.L" <alphaboran@yahoo.com> wrote in message news:<a4t9p2$hog$1@ulysses.noc.ntua.gr>...
> > Hello all,
> > I know that this issue is well discussed in this newsgroup but still I have
> > some questions.
> > In a Virtex-E FPGA the setup time for the EN,WE signals are 2.5 ns and 2.2ns
> > (plz confirm) but the setup time for the address,data is about 1.1ns (plz
> > confirm). I want to use 3 BRAMs 128x32  in a Virtex-E 600 (speed grade 6) @
> > 77 MHz (or clock period=12ns), do I have to keep the "input" signals stable
> > for 2 clock periods to succeed a correct timing in the read/write operations
> > or is it totally wrong (except for too slow)?
> >
> > Best Regards,
> > Harris

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39858
Subject: Re: CLKDLL x4 problem
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Feb 2002 15:05:25 GMT
Links: << >>  << T >>  << A >>
You need to be careful attempting this.  Peter's circuit can easily have
jitter which is well outside of the acceptable jitter spec for the DLL.   In
order to have even a small chance of success, the 10 MHz clock has to be
exactly 50% duty cycle, which is very hard to achieve with a single ended
clock input.

David Bishop wrote:

> Tim wrote:
> >
> > Starting from a 10MHz clock, you can use Peter's circuit to double
> > to 20MHz, then run the faster clock through the DLL.  Still outside
> > limits, but will almost certainly work on the bench - stick to
> > 25MHz in shipping product.
>
> It turns out that the ES parts will lock on less than 20 MHz, with
> a special "tweek" from Xilinx.  Supposedly there will be a tactical
> patch for this.  Also, look at the erratta sheets!  Some of the ES
> parts have problems locking on the FX output of a DCM.
>
> --
> NAME:     David W. Bishop           INTERNET: dbishop@vhdl.org  (  \  )
> US MAIL:  Hilton NY                 A Long time ago,             \__\/
> PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
> For Supernova info:  http://www.RochesterAstronomy.org/snimages/  | |
> For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
> All standard disclaimers apply.                                [_______]

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39859
Subject: Re: SRL16E Initialization
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Feb 2002 15:10:00 GMT
Links: << >>  << T >>  << A >>
You need to initialize these twice.  Once with a generic for the
simulation, and once with an INIT= attribute for the back end tools.
The generic has to be ignored during synthesis, which means it must be
surrounded by translate_off/on pragmas.  Note that the format for the
generic is different than that for the attribute.  In the example
below, itoh is an integer to hex string conversion, and int2bit_vec is
an integer to bit_vector conversion.  These are used to get the
correct formats for the two init strings.

 attribute INIT   of U1 : label is itoh(lut_init);--INIT= attribute to
pass to PAR through synplicity
 begin
 U1: SRL16E
  --synthesis translate_off
  generic map ( -- init generic is for simulation model, not seen by
Synplicity or PAR
   INIT => int2bit_vec(lut_init,16))
  --synthesis translate_on
  port map (
   Q  => y,
   A0 => tap(0),
   A1 => tap(1),
   A2 => tap(2),
   A3 => tap(3),
   D  => ldi(i),
   CLK => clk,
   CE => we );


AT wrote:

> Hallo,
>
> I would like to make divider by 32 from SRL16E of SpartanII, but
> translate occurs this error (WebPack 4.1):
>     "logical block 'divog' with type 'srl16e0' is unexpanded"
>
>  divG: SRL16E
>     generic map(INIT => X"8000")
>     port map ( D => inter(1), CE => Enable, CLK => Clock,
>        A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3),
>        Q => inter(0));
>
>  divoG: SRL16E
>    generic map(INIT => X"0000")
>    port map ( D => inter(0), CE => Enable, CLK => Clock,
>       A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3),
>       Q => inter(1));
>
> Is it impossible initialize SRL16Es by different values?
> Thanks.
> AT

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 39860
Subject: Re: CLKDLL x4 problem
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 21 Feb 2002 15:18:54 GMT
Links: << >>  << T >>  << A >>
Since my name was used, I must state that I strongly agree with Ray: "My"
frequency doubler differentiates the two clock edges, and will thus be the
victim of any non-50% duty cycle variation on the input. And the DLL or DCM
does not like that...

Peter Alfke, Xilinx Applications
=================================
Ray Andraka wrote:

> You need to be careful attempting this.  Peter's circuit can easily have
> jitter which is well outside of the acceptable jitter spec for the DLL.   In
> order to have even a small chance of success, the 10 MHz clock has to be
> exactly 50% duty cycle, which is very hard to achieve with a single ended
> clock input.
>
> David Bishop wrote:
>
> > Tim wrote:
> > >
> > > Starting from a 10MHz clock, you can use Peter's circuit to double
> > > to 20MHz, then run the faster clock through the DLL.  Still outside
> > > limits, but will almost certainly work on the bench - stick to
> > > 25MHz in shipping product.
> >
> > It turns out that the ES parts will lock on less than 20 MHz, with
> > a special "tweek" from Xilinx.  Supposedly there will be a tactical
> > patch for this.  Also, look at the erratta sheets!  Some of the ES
> > parts have problems locking on the FX output of a DCM.
> >
> > --
> > NAME:     David W. Bishop           INTERNET: dbishop@vhdl.org  (  \  )
> > US MAIL:  Hilton NY                 A Long time ago,             \__\/
> > PHYSICAL: 43:17:17N 77:47:37W 281'  In a Galaxy far, far away...  | |
> > For Supernova info:  http://www.RochesterAstronomy.org/snimages/  | |
> > For VHDL/Synthesis info:  http://www.vhdl.org/siwg              _/___\_
> > All standard disclaimers apply.                                [_______]
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759


Article: 39861
Subject: Here is an argument and can anyone help me out
From: "Madhu" <pp_madhavi@yahoo.com>
Date: Thu, 21 Feb 2002 15:29:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi all,
  here is an argument with one of my friend who is a mechanical engineer
and writing S/W.
  He argues that if the input and output waveforms are given he can
write a tool which generates a digital circuit for those inputs and
outputs. He knows about truth tables and gates.
  He is not convinced when I told all digital circuits are not just
combinational.
  Then I asked him whether he can generate a C program if the inputs and
outputs are given. But he says that it is obsurd that I am comparing a
language with digital design.
  Still he believes in what he says.
  So friends, please do respond.
  Thank you
              Madhu


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 39862
Subject: Re: CLKDLL x4 problem
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Thu, 21 Feb 2002 15:43:55 -0000
Links: << >>  << T >>  << A >>
Yes.  But someone posted that he tried it and it does work well
enough for benchtop debugging.  As I recall, he used this
arrangement in a production design ;-)

For a more reliable patch, find a space on the PCB to epoxy a
PLL chip from ICS (www.icst.com).  The ICS502 will multiply
by 2, 2.5, 3, 3.5, 4, 5.


Peter Alfke wrote
> Since my name was used, I must state that I strongly agree with Ray: "My"
> frequency doubler differentiates the two clock edges, and will thus be the
> victim of any non-50% duty cycle variation on the input. And the DLL or DCM
> does not like that...
>
> Peter Alfke, Xilinx Applications
> =================================
> Ray Andraka wrote:
>
> > You need to be careful attempting this.  Peter's circuit can easily have
> > jitter which is well outside of the acceptable jitter spec for the DLL.   In
> > order to have even a small chance of success, the 10 MHz clock has to be
> > exactly 50% duty cycle, which is very hard to achieve with a single ended
> > clock input.
> >
> > David Bishop wrote:
> >
> > > Tim wrote:
> > > >
> > > > Starting from a 10MHz clock, you can use Peter's circuit to double
> > > > to 20MHz, then run the faster clock through the DLL.  Still outside
> > > > limits, but will almost certainly work on the bench - stick to
> > > > 25MHz in shipping product.
> > >
> > > It turns out that the ES parts will lock on less than 20 MHz, with
> > > a special "tweek" from Xilinx.  Supposedly there will be a tactical
> > > patch for this.  Also, look at the erratta sheets!  Some of the ES
> > > parts have problems locking on the FX output of a DCM.
> > >






Article: 39863
Subject: Re: Here is an argument and can anyone help me out
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 21 Feb 2002 08:23:06 -0800
Links: << >>  << T >>  << A >>
Madhu,
test his skills with the following:
Input = clock
outputs = several outputs from a binary counter driven by that clock.
This is admittedly trivial, but it gets him to think in terms of state machines.

BTW: Given a finite sequence of inputs and outputs, one can obviously generate
the combinatorial and/or sequential logic that generates these outputs.  The
brute-force solution may not be the most elegant one, but there always is a
solution.

Peter Alfke
=====================
Madhu wrote:

> Hi all,
>   here is an argument with one of my friend who is a mechanical engineer
> and writing S/W.
>   He argues that if the input and output waveforms are given he can
> write a tool which generates a digital circuit for those inputs and
> outputs. He knows about truth tables and gates.
>   He is not convinced when I told all digital circuits are not just
> combinational.
>   Then I asked him whether he can generate a C program if the inputs and
> outputs are given. But he says that it is obsurd that I am comparing a
> language with digital design.
>   Still he believes in what he says.
>   So friends, please do respond.
>   Thank you
>               Madhu
>
> --
> Posted via Mailgate.ORG Server - http://www.Mailgate.ORG


Article: 39864
Subject: Re: Here is an argument and can anyone help me out
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Thu, 21 Feb 2002 11:26:58 -0500
Links: << >>  << T >>  << A >>
Madhu,
    Ask your friend just what he thinks runs that C program.  It is a
digital circuit with known inputs and outputs.  (for example, either a
series of numbers, or a keyboard input, etc.)  All of these are ultimately
digital circuits.  There are no analog computers in use anymore (to the best
of my knowledge.)

Theron


"Madhu" <pp_madhavi@yahoo.com> wrote in message
news:c074a7b1c70d79729ac318bbc52aa174.67011@mygate.mailgate.org...
> Hi all,
>   here is an argument with one of my friend who is a mechanical engineer
> and writing S/W.
>   He argues that if the input and output waveforms are given he can
> write a tool which generates a digital circuit for those inputs and
> outputs. He knows about truth tables and gates.
>   He is not convinced when I told all digital circuits are not just
> combinational.
>   Then I asked him whether he can generate a C program if the inputs and
> outputs are given. But he says that it is obsurd that I am comparing a
> language with digital design.
>   Still he believes in what he says.
>   So friends, please do respond.
>   Thank you
>               Madhu
>
>
> --
> Posted via Mailgate.ORG Server - http://www.Mailgate.ORG



Article: 39865
Subject: Xilinx (ise4.1) is screwed up! SCREAM LOUD!!
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Thu, 21 Feb 2002 11:33:45 -0500
Links: << >>  << T >>  << A >>
The problem I initially posted about was the fact that the FIFO from CoreGen
has a major bug in it.  I have since found a work-around using a dual port
ram.  However, in general, I am greatly displeased with ISE4.1.  The only
good thing I can say is that it does handle CoreGen instantiations
seamlessly.  The PAR algorithm does a really poor job of placing parts.  The
manual placer has a major bug.  In short, it appears that Xilinx is using
the customer for beta testing and then making us pay for the software.  I
hope that the next service pack will solve most of these problems.  What
about ISE4.2?  Is it any better?  I am using the Spartan2 series parts.

Perhaps if enough of us scream _really_ loud, Xilinx will get their act
together.

Theron Hicks


"Jonas Weiss" <jweiss@kontronmedical.ch> wrote in message
news:3C6CBFDF.EC64A773@kontronmedical.ch...
> Hello,
> I was just wondering if you got your asynchronous FIFO to work by now. For
some
> days I'm also trying to get my design using one of these to work, without
> success yet (ISE 4.1 & Model Sim XE Starter). I am using continuous read
and
> write clocks with synchronous enables.
> Behavioral simulation works fine, but as soon as I proceed to a post
translate
> simulation I get 'open' select signals of internal fifo-muxes in the
translate
> file.
> P&R works, just the post P&R simulation is not exactly what I expected it
to be,
> as if the behavioral model and the coregen netlist were not consistent.
> Any new ideas yet?
>
> Thanks
>
> Jonas
>
>



Article: 39866
Subject: Using a CoreGen component
From: "Dave Brown" <dbrown12@shaw.ca>
Date: Thu, 21 Feb 2002 10:08:24 -0700
Links: << >>  << T >>  << A >>
I have a project written in VHDL that I'm trying to synthesize using XST and
ISE 4. Part of the project uses a dual port ram block that was created using
CoreGen. When I try and place and route the design, I get errors that say
the dual port ram block is unexpanded. I have included the .xco file for the
ram block inb the project files, what more do I need to do to get place and
route to work? The component that uses the RAM has the correct component
declartions from the CoreGen generated template file. Any help would be
great.
Thanks,
Dave




Article: 39867
Subject: Re: Here is an argument and can anyone help me out
From: Christopher.Saunter@durham.ac.uk (Christopher Saunter)
Date: Thu, 21 Feb 2002 17:15:39 +0000 (UTC)
Links: << >>  << T >>  << A >>
Theron Hicks (hicksthe@egr.msu.edu) wrote:
: Madhu,
:     Ask your friend just what he thinks runs that C program.  It is a
: digital circuit with known inputs and outputs.  (for example, either a
: series of numbers, or a keyboard input, etc.)  All of these are ultimately
: digital circuits.  There are no analog computers in use anymore (to the best
: of my knowledge.)

I read this and it set me thinking:
I am sure I have come across references to a NASA Analogue computer that
calculates balistics etc. for space missions, as it is a somewhat more
cost effective solution than solving analytically all the equations.  I
tried to find a link to this and failed, but I found another one
instead...

http://www.simlabs.arc.nasa.gov/vms/controls.html

I guess the undergrad lab session I had on analogue computers wasn't
wasted after all...

Chris Saunter

Article: 39868
Subject: Re: Do I need to install software in order to use Multilinx?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 21 Feb 2002 18:32:27 +0100
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
news:3C750BE8.DE42CE4C@andraka.com...
> They replaced it with something called "iMPACT".  I haven't used it yet,
so I
> can't tell you how good/bad it is.  It does still require you to do a full
> xilinx install to be able to download devices :-(

If you want to use only the commercial version, then YES.
But there is also the WEBPACK version of IMPACT, which is AFAIK identical to
the commercial version.
So you jst need to install IMPACT (WEBPACK)

--
MfG
Falk





Article: 39869
Subject: Re: Need largest CPLD devices?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 21 Feb 2002 18:36:40 +0100
Links: << >>  << T >>  << A >>
"X. Q." <qijun@okigrp.com.sg> schrieb im Newsbeitrag
news:3c746c0c@news.starhub.net.sg...
> I built my design with Spartan-II. Now the research centre in another
> country
> needs my design. Let's pressume they don't have any expertise in FPGA and

So why dont you send

a) the HDL code
b) the netlist

?? So they can use it.

> such, while they want my design. How can I transport my design to them? My
> design is 10K gates in ASIC. Can I get any CPLD which can hold this
design?

AFAIK there is no such big CPLD around. 1024 macrocells is the maximum.

> I understand FPGA dies after I unplug the power.

They dont ;-), They just lose their configuration, because it is stored in
SRAM. But ACTEL sells FLASH and Antifuse based devices, they keep their
programming after power OFF.
Anyway, I dont quite see your problem. IF the "other" gus have a board with
a FPGA, (maybe same familie as you have) then they can easyly recompile the
code and are done.

--
MfG
Falk





Article: 39870
Subject: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 21 Feb 2002 18:37:45 +0100
Links: << >>  << T >>  << A >>
"Kumar" <yatiks@yahoo.com> schrieb im Newsbeitrag
news:b479edf8.0202202254.58dbda7e@posting.google.com...

> Then I connected the same Board to other PC with less speed( config
> --366 Mhz Celeron ) I have not faced any problem in programming the
> FPGA ( XC2s200-5PQ208 ) through JTAG with same cable (length = appr 5
> feet).
>
>   Can anybody tell what is causing the problem (is the speed of the PC
> or something else)  and also how can I solve this problem ????????

Looks like a driver problem.

--
MfG
Falk





Article: 39871
Subject: Re: Using a CoreGen component
From: Kamal Patel <kamal.patel@xilinx.com>
Date: Thu, 21 Feb 2002 10:37:51 -0700
Links: << >>  << T >>  << A >>
Dave,

Make sure the netlist for the core (.edn) is in the project
directory or macro search path, and that the core is named
correctly.

Regards,
Kamal

Dave Brown wrote:

> I have a project written in VHDL that I'm trying to synthesize using XST and
> ISE 4. Part of the project uses a dual port ram block that was created using
> CoreGen. When I try and place and route the design, I get errors that say
> the dual port ram block is unexpanded. I have included the .xco file for the
> ram block inb the project files, what more do I need to do to get place and
> route to work? The component that uses the RAM has the correct component
> declartions from the CoreGen generated template file. Any help would be
> great.
> Thanks,
> Dave


Article: 39872
Subject: Re: Here is an argument and can anyone help me out
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Thu, 21 Feb 2002 12:39:33 -0500
Links: << >>  << T >>  << A >>

"Christopher Saunter" <Christopher.Saunter@durham.ac.uk> wrote in message
news:a539vr$32i$1@sirius.dur.ac.uk...
> Theron Hicks (hicksthe@egr.msu.edu) wrote:
> : Madhu,
> :     Ask your friend just what he thinks runs that C program.  It is a
> : digital circuit with known inputs and outputs.  (for example, either a
> : series of numbers, or a keyboard input, etc.)  All of these are
ultimately
> : digital circuits.  There are no analog computers in use anymore (to the
best
> : of my knowledge.)
>
> I read this and it set me thinking:
> I am sure I have come across references to a NASA Analogue computer that
> calculates balistics etc. for space missions, as it is a somewhat more
> cost effective solution than solving analytically all the equations.  I
> tried to find a link to this and failed, but I found another one
> instead...
>
> http://www.simlabs.arc.nasa.gov/vms/controls.html
>
> I guess the undergrad lab session I had on analogue computers wasn't
> wasted after all...
>
> Chris Saunter

Chris,
I think I had the same lab back in the 70's.  I guess we are both showing
our ages.

Theron




Article: 39873
Subject: EDIF IN A VHDL PROJECT (kcpsm.edn) in ISE4.1
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Thu, 21 Feb 2002 12:42:39 -0500
Links: << >>  << T >>  << A >>
I am trying to use the KCPSM microcontroller in a VHDL design in ISE 4.1.
4.1 does not appear to recognize the EDIF file in a VHDL project.  (ISE3.3
does seem to work OK.)

I get the following messages...

EDIF source are not supported for the selected device and flow. Import file
kcpsm.EDN?

This design contains sources that are not supported by the current device
and flow. You may view these sources, but not process them. These are :
kcpsm.EDN

Am I missing something obvious?




Article: 39874
Subject: Re: Using a CoreGen component
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Thu, 21 Feb 2002 12:45:09 -0500
Links: << >>  << T >>  << A >>

"Dave Brown" <dbrown12@shaw.ca> wrote in message
news:a539he$9b4$1@pallas.novatel.ca...
> I have a project written in VHDL that I'm trying to synthesize using XST
and
> ISE 4. Part of the project uses a dual port ram block that was created
using
> CoreGen. When I try and place and route the design, I get errors that say
> the dual port ram block is unexpanded. I have included the .xco file for
the
> ram block inb the project files, what more do I need to do to get place
and
> route to work? The component that uses the RAM has the correct component
> declartions from the CoreGen generated template file. Any help would be
> great.
> Thanks,
> Dave
>
>
>

Dave,
    Did you include the library?

-- synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synopsys translate_on

Theron







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