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Messages from 40550

Article: 40550
Subject: Re: Xilinx ISE 4.1
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Sat, 09 Mar 2002 21:45:05 +0200
Links: << >>  << T >>  << A >>

Salman, I haven't used M4.1i but the warning coming from MAP
is the same I get from MAP M3.1i SP8. This warning means that
your synthesizer created LD* element for your Xilinx FPGA from
your RTL code. LD primitive is implemented in flipflop portion
of the slice, therefore you obtain warnings that include the
word "flipflop". The enable pin of LD* primitive is using gated clock
input resource of the slice. If you want to create latches, you
can safely ignore these warnings.

Utku

Salman Sheikh wrote:

> Hello,
>
> WARNING: DesignRules: 372 [snip]


Article: 40551
Subject: Re: Xilinx ISE 4.1
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Sat, 09 Mar 2002 21:48:10 +0200
Links: << >>  << T >>  << A >>

By the way, why don't you use Core Generator that can create
binary decoder to decode the address vector for you, to be used
in your CPU Interface? It is also area/speed optimized. No latches
any more.

Utku



Article: 40552
Subject: Re: exceeding 2GB limits in xilinx
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: Sat, 09 Mar 2002 23:04:27 GMT
Links: << >>  << T >>  << A >>
"B. Joshua Rosen" <bjrosen@polybus.com> writes:

> In <87y9h2w2rr.fsf@filestore.home.gustad.com>, Petter Gustad wrote:
> 
> > "B. Joshua Rosen" <bjrosen@polybus.com> writes:
> > 
> >> The current generation of Xilinx tools is unrelated to XACT. Xilinx
> >> bought a company (who's name escapes me now) in the mid-90s that had a
> >> place and route tool that is the ancestor of the current tools. My
> > 
> > Thank you for the clarification. I was wrong when I assumed XACT was the
> > ancestor of Alliance/ISE/etc.
> > 
> >> understanding is that the Xilinx tools are developed on Unix and then
> >> ported to Windows. The reason that the Xilinx tools run so well under
> > 
> > This what I've heard to. Hence I was a little surprised that Xilinx is
> > supporting the Windows version under WINE in the 4.2 release rather than
> > porting their native UNIX (Solaris/HP-UX) version to Linux.
> > 
> > Petter
> It's the GUI part of the product that they needed Wine for. The Xilinx
> tools have been running for years under wine so all they had to do was
> package them up and announce that they are supporting the Linux

But the GUI stuff should be easily ported from Solaris/HP-UX to Linux.
I thought it was written in Java since it's so sluggish. BTW: I don't
use any of the GUI programs besides the floorplanner and the
installation programs (which are soooo sloooow).

> environment. I read a mention somewhere, either here or in the wine
> group, that they intend to have a fully native version next year. The
> GUIs are written using a tool that puts out both Windows and Unix code, I
> think they are waiting for that tool to support Linux.

That explains a lot, i.e. that they have to wait for a third party
provider to make a Linux release.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 40553
Subject: 32-taps FIR !
From: "Flora Cathy" <floreq10@hotmail.com>
Date: Sun, 10 Mar 2002 00:45:56 +0000 (UTC)
Links: << >>  << T >>  << A >>
heya
for case study, i am looking for a symmetric filter of 32 taps or MORE
i want a real applicable FIR. looking for the FIR coefficients

anticpated thanks

~CATHY


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 40554
Subject: Audio project with an FPGA?
From: "David Lamb" <david.lamb@videotron.ca>
Date: Sat, 9 Mar 2002 20:46:44 -0500
Links: << >>  << T >>  << A >>
Hi!
I'm a third year student in electrical engineering and in one of my class we
have to design something with an FPGA (from altera).
------
'For your term project you are to choose an interesting digital system,
design the system in VHDL, synthesize it for the Altera family of FPGAs and
gather statistics. Your project should use between 5,000 to 200,000 logic
gates and can use multiple FPGAs.
------

I don't really know what can be done with FPGAs but I'd like to do something
related to audio (music). I know groups from past years designed an mp3
decoder. This would have been interesting a couple of years ago but now I
think it is over-used.
Any ideas are really welcome
Btw, this is for a 3 credit class so it is not an 'End of degree project'.
Thanks a lot
David

Here are some proposed subject by the instructor...they don't look really
attractive to me!!

  1.. Error detecting-correcting modules. Some of the more advanced
n-out-of-m error correcting codes (other than the Hamming codes) would be
very interesting topics.

  2.. Various communication network protocols including ATM, SONET,
Ethernet, FDDI, DBDQ, IBM token ring, high speed serial links or any recent
development.

  3.. Digital neural networks and fuzzy logic systems to recognize patterns
or perform processing.

  4.. A digital system including MPEG, JPEG, speech/image or video
compression and decompression systems, etc. Voice sub-band coding is one
example; it can compress a 64 Kbit/s voice stream to about 8Kbit/s.

  5.. RISC CPU, DSP and computer subsystems, for example, cache controller,
schedulers, PCI bus interface.

  6.. A hardware encryption/decryption units. The RSA, PGP, and DES
algorithms are currently among the most popular.

  7.. Fast designs for performing computer arithmetic algorithms, i.e.,
multiplication, division, square roots etc., including transform function
such as FFT, DCT, and Hadamard Transform.

  8.. Image processing systems: hardware to perform image manipulations,
i.e. moving the view to the left or right, zooming in or out, rendering,
hidden line removal, etc. The fields of computer graphics or Virtual Reality
are full of interesting things to do with images.

  9.. Any interesting system you can think of. Search the FPGA
manufacturer's "Application Notes" to get good ideas, and discussions of how
to implement the systems on FPGA. You can implement a system or sub-system
that is described in an Altera or Xilinx Application Note. Proceedings of
the Canadian Conference on Programmable Logic Devices describe some of the
research projects undertaken at other universities. There are also
international conference on the subject, whcih can give you ideas.

  10.. You can also construct smaller sub-systems of a larger system. For
example, MPEG and JPEG compression systems often use 8x8 Discrete Cosine
Transforms. You could just implement the DCT, which is a sub-system of the
MPEG/JPEG systems.

  11.. FPGAs have been proposed for use in DNA pattern matchers, where they
apparently outperform supercomputers. They have been proposed in Nuclear
Magnetic Resonance (NMR) medical machines, where they perform digital signal
processing to create a 3D image of the human brain.





Article: 40555
Subject: Re: Audio project with an FPGA?
From: leotran@_*worldnet.att.net (Loi Tran)
Date: Sun, 10 Mar 2002 04:28:59 GMT
Links: << >>  << T >>  << A >>
Decoding MP3 as you have said has been done pretty much by everyone, but have 
you considered encoding.  That's a lot more challenging, I think.

LT

In article <8Wyi8.31508$Fh4.854992@weber.videotron.net>, "David Lamb" 
<david.lamb@videotron.ca> wrote:
>Hi!
>I'm a third year student in electrical engineering and in one of my class we
>have to design something with an FPGA (from altera).
>------
>'For your term project you are to choose an interesting digital system,
>design the system in VHDL, synthesize it for the Altera family of FPGAs and
>gather statistics. Your project should use between 5,000 to 200,000 logic
>gates and can use multiple FPGAs.
>------
>
>I don't really know what can be done with FPGAs but I'd like to do something
>related to audio (music). I know groups from past years designed an mp3
>decoder. This would have been interesting a couple of years ago but now I
>think it is over-used.
>Any ideas are really welcome
>Btw, this is for a 3 credit class so it is not an 'End of degree project'.
>Thanks a lot
>David
>
>Here are some proposed subject by the instructor...they don't look really
>attractive to me!!
>
>  1.. Error detecting-correcting modules. Some of the more advanced
>n-out-of-m error correcting codes (other than the Hamming codes) would be
>very interesting topics.
>
>  2.. Various communication network protocols including ATM, SONET,
>Ethernet, FDDI, DBDQ, IBM token ring, high speed serial links or any recent
>development.
>
>  3.. Digital neural networks and fuzzy logic systems to recognize patterns
>or perform processing.
>
>  4.. A digital system including MPEG, JPEG, speech/image or video
>compression and decompression systems, etc. Voice sub-band coding is one
>example; it can compress a 64 Kbit/s voice stream to about 8Kbit/s.
>
>  5.. RISC CPU, DSP and computer subsystems, for example, cache controller,
>schedulers, PCI bus interface.
>
>  6.. A hardware encryption/decryption units. The RSA, PGP, and DES
>algorithms are currently among the most popular.
>
>  7.. Fast designs for performing computer arithmetic algorithms, i.e.,
>multiplication, division, square roots etc., including transform function
>such as FFT, DCT, and Hadamard Transform.
>
>  8.. Image processing systems: hardware to perform image manipulations,
>i.e. moving the view to the left or right, zooming in or out, rendering,
>hidden line removal, etc. The fields of computer graphics or Virtual Reality
>are full of interesting things to do with images.
>
>  9.. Any interesting system you can think of. Search the FPGA
>manufacturer's "Application Notes" to get good ideas, and discussions of how
>to implement the systems on FPGA. You can implement a system or sub-system
>that is described in an Altera or Xilinx Application Note. Proceedings of
>the Canadian Conference on Programmable Logic Devices describe some of the
>research projects undertaken at other universities. There are also
>international conference on the subject, whcih can give you ideas.
>
>  10.. You can also construct smaller sub-systems of a larger system. For
>example, MPEG and JPEG compression systems often use 8x8 Discrete Cosine
>Transforms. You could just implement the DCT, which is a sub-system of the
>MPEG/JPEG systems.
>
>  11.. FPGAs have been proposed for use in DNA pattern matchers, where they
>apparently outperform supercomputers. They have been proposed in Nuclear
>Magnetic Resonance (NMR) medical machines, where they perform digital signal
>processing to create a 3D image of the human brain.
>
>
>
>

Article: 40556
Subject: FPGA Synthesis ...new methodology
From: anbarasu1234@lycos.com (Anbarasu)
Date: 9 Mar 2002 23:24:11 -0800
Links: << >>  << T >>  << A >>
I read about the mentor's new precision synthesis announcement. can
the fpga experts out here comment on how does this change from
previous version of Leonardo? how does sopc support be enhanced as
claimed in sythesis front, when the embedded processors really do not
use any HDL? correct me if my understanding is wrong.

-anbarasu

Article: 40557
Subject: Re: exceeding 2GB limits in xilinx
From: hamish@cloud.net.au
Date: 10 Mar 2002 13:30:14 GMT
Links: << >>  << T >>  << A >>
B. Joshua Rosen <bjrosen@polybus.com> wrote:
> environment. I read a mention somewhere, either here or in the wine
> group, that they intend to have a fully native version next year. The
> GUIs are written using a tool that puts out both Windows and Unix code, I
> think they are waiting for that tool to support Linux.

UNIX GUIs (ie X11) will already work on Linux - no changes required.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 40558
Subject: Re: DPRAM implementation in altera
From: giga_super_man <super@man.com>
Date: Sun, 10 Mar 2002 06:37:02 -0800
Links: << >>  << T >>  << A >>
why dont you just use the megawizard provided by Max+2 or quartus 2 to create the same functionality a being provided by RAMB4_S16_S16. If you need special functionality as write_first etc. this is not possible with current implementation of altdprame etc.

Article: 40559
Subject: Re: How can I install Xilinx ISE 4.1i under Linux?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Sun, 10 Mar 2002 19:33:54 +0200
Links: << >>  << T >>  << A >>
Peter Ormsby wrote:

> newman <newman5382@aol.com> wrote in message
> news:e6038423.0203071338.2e220f61@posting.google.com...
> > I saw on the Xilinx Web site that ISE4.2 is now supported on RedHat7.2
> >
> > Newman
>
> Newman,
>
> This is slightly misleading.  See this post:
>
> http://groups.google.com/groups?hl=en&scoring=d&selm=D9Bh8.13448%24Or3.14935
> 91%40typhoon.mn.ipsvc.net
>
> -Pete-

Google: Unable to retrieve article. (I also tried to concatenate wrapped lines,
doesn't go either)

Utku



Article: 40560
Subject: Re: Audio project with an FPGA?
From: "Joey Nelson" <highfreq@micron.net>
Date: Sun, 10 Mar 2002 10:38:47 -0800
Links: << >>  << T >>  << A >>

I've always though that a analog style synthesizer would be fun.  With the
fpga you could do the actual synthesis at MHz sample rates allowing the use
of much more analog style filters (at 44.1kHz the aliasing requires pretty
fancy dsp gymnastics to get good sounding filters) and then digital lowpass
filter it before going to the DAC.

Joey
"David Lamb" <david.lamb@videotron.ca> wrote in message
news:8Wyi8.31508$Fh4.854992@weber.videotron.net...
> Hi!
> I'm a third year student in electrical engineering and in one of my class
we
> have to design something with an FPGA (from altera).
> ------
> 'For your term project you are to choose an interesting digital system,
> design the system in VHDL, synthesize it for the Altera family of FPGAs
and
> gather statistics. Your project should use between 5,000 to 200,000 logic
> gates and can use multiple FPGAs.
> ------
>
> I don't really know what can be done with FPGAs but I'd like to do
something
> related to audio (music). I know groups from past years designed an mp3
> decoder. This would have been interesting a couple of years ago but now I
> think it is over-used.
> Any ideas are really welcome
> Btw, this is for a 3 credit class so it is not an 'End of degree project'.
> Thanks a lot
> David
>
> Here are some proposed subject by the instructor...they don't look really
> attractive to me!!
>
>   1.. Error detecting-correcting modules. Some of the more advanced
> n-out-of-m error correcting codes (other than the Hamming codes) would be
> very interesting topics.
>
>   2.. Various communication network protocols including ATM, SONET,
> Ethernet, FDDI, DBDQ, IBM token ring, high speed serial links or any
recent
> development.
>
>   3.. Digital neural networks and fuzzy logic systems to recognize
patterns
> or perform processing.
>
>   4.. A digital system including MPEG, JPEG, speech/image or video
> compression and decompression systems, etc. Voice sub-band coding is one
> example; it can compress a 64 Kbit/s voice stream to about 8Kbit/s.
>
>   5.. RISC CPU, DSP and computer subsystems, for example, cache
controller,
> schedulers, PCI bus interface.
>
>   6.. A hardware encryption/decryption units. The RSA, PGP, and DES
> algorithms are currently among the most popular.
>
>   7.. Fast designs for performing computer arithmetic algorithms, i.e.,
> multiplication, division, square roots etc., including transform function
> such as FFT, DCT, and Hadamard Transform.
>
>   8.. Image processing systems: hardware to perform image manipulations,
> i.e. moving the view to the left or right, zooming in or out, rendering,
> hidden line removal, etc. The fields of computer graphics or Virtual
Reality
> are full of interesting things to do with images.
>
>   9.. Any interesting system you can think of. Search the FPGA
> manufacturer's "Application Notes" to get good ideas, and discussions of
how
> to implement the systems on FPGA. You can implement a system or sub-system
> that is described in an Altera or Xilinx Application Note. Proceedings of
> the Canadian Conference on Programmable Logic Devices describe some of the
> research projects undertaken at other universities. There are also
> international conference on the subject, whcih can give you ideas.
>
>   10.. You can also construct smaller sub-systems of a larger system. For
> example, MPEG and JPEG compression systems often use 8x8 Discrete Cosine
> Transforms. You could just implement the DCT, which is a sub-system of the
> MPEG/JPEG systems.
>
>   11.. FPGAs have been proposed for use in DNA pattern matchers, where
they
> apparently outperform supercomputers. They have been proposed in Nuclear
> Magnetic Resonance (NMR) medical machines, where they perform digital
signal
> processing to create a 3D image of the human brain.
>
>
>
>



Article: 40561
Subject: Re: Xilinx Download Cable Connectors
From: "Jim Kearney" <jim@no.spam.please.com>
Date: Sun, 10 Mar 2002 23:18:19 GMT
Links: << >>  << T >>  << A >>

"Tim" <tim@rockylogic.com.nooospam.com> wrote in message
news:1015642799.2102.0.nnrp-12.9e9832fa@news.demon.co.uk...
> I feel really, really stupid at having to ask this...
>
> What is the name of the connectors on the end of the wires
> on Xilinx download cables?  I mean the socket thingies
> which fit over 0.025" posts - I think they crimp onto the
> fairly thick wires.
>
> They may be in the DigiKey Catalog, but I cannot find
> them ;)

I had a need for these too, but Digi-key doesn't have quite the right parts.
But I think you'll find what you want on pg. 215 of the Mouser catalog, e.g.
part # 571-7874992 and its associated snap-in receptacles.

Jim




Article: 40562
Subject: How to Align 7x DDR Data Input to a XC2V6000-5?
From: Mark <mark@pac.net>
Date: Mon, 11 Mar 2002 03:25:56 GMT
Links: << >>  << T >>  << A >>
Hello,

I'm trying to align an input "receiver" to ddr data in an XC2V6000-5.
The ddr data rate is 7x the 1x "system" clock.

(The following are waveforms that are best viewed with a
non-proportional/fixed-width font.)
             ______        ______        __
clk10x     _/      \______/      \______/
             _   _   _   _   _   _   _   _
clk35x_p   _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
              _____________________________
locked     __/

            _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ddr_data   X6X0X1X2X3X4X5X6X0X1X2X3X4X5X6X0
            - - - - - - - - - - - - - - - -
             ______        ______        __
clk10x     _/      \______/      \______/
           _   _   _   _   _   _   _   _
clk35x_p    \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
              _____________________________
locked (2) __/

- clk10x and clk35x_p are phase-locked and clk10x rising edges are
"aligned" with clk35x_p's every 7 3.5x clock cycles.
- locked is synchronous to clk10x.  It could be made synchronous to
clk35x_n.
- clk35x_n is also available.  It is 180 deg phase locked/shifted from
clk35x_p.
- ddr_data is input to the ddr register.  Its output is every other ddr
data at the 3.5x rate.

- Using clk35x_p after locked goes high, the output of the ddr register
is 1,3,5,0,2,4,6,....
- Using clk35x_p after locked (2) goes high, the output is
0,2,4,6,1,3,5,0,....
- This difference is due to an odd number, 7, of 3.5x clock cycles
occurring in two 1.0x clock cycles.

The approach I've been trying is to align a state machine to the data by
determining which data, 1 or 0, is "first", using bits that toggle at
the different clock rates.

I think I've been staring at this too long and need to get out of my
"box" to find a solution.  I would greatly appreciate any thoughts.

Thank you,
Mark


Article: 40563
Subject: Re: digital video PLL
From: "Christopher Holmes" <gomiboy@sdf.lonestar.org>
Date: Sun, 10 Mar 2002 23:15:53 -0500
Links: << >>  << T >>  << A >>
I'm now working on a design that uses an external PLL to generate a pixel
clock of 10MHz.from NTSC HSYNC.  The chip I'm using is ICS 673-01
(http://www.icst.com/products/pdf/ics67301.pdf).  I use some spare space in
the FPGA to divide the feedback clock.

Chris

"Guy Eschemann" <geschem@surfeu.de> wrote in message
news:3C84E900.455F5BF0@surfeu.de...
> Hi,
> I need to design a digital PLL to fit in a small FPGA or CPLD.
> This PLL should lock on a video H-sync which has a period of 64us.
> Could anyone please give me some hints on how to get started with it ?
> Many thanks,
> Guy.
>
>



Article: 40564
Subject: Spartan II E output voltage characteristics
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 11 Mar 2002 01:10:35 -0500
Links: << >>  << T >>  << A >>
I need to drive a CMOS device with a Spartan II E chip.  The data sheet
only guarantees 2.4 volts on the output at 24 mA.  Nothing is said about
lighter loads, for example a CMOS input.  Working with an odd Vdd on the
CMOS device of 3.8 volts, I get a Vih of 2.66 volts.  Is it safe to
assume that the Spartan device will pull fully to 3.3 volts (or very
near) with such a light load?  The input current on the CMOS device is
<10 uA.  Or should I use pullups?  In spite of the data sheet note
saying that the internal pullups should not be used to pull external
signals, will they be sufficient to provide sufficient pullup with such
a light load?  I am not even sure if you can enable the pullups on pin
used as outputs.  Anyone have experience with this?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40565
Subject: First steps with clock enable constraining
From: dottavio@ised.it (Antonio)
Date: 10 Mar 2002 23:21:33 -0800
Links: << >>  << T >>  << A >>
for the following circuit I need a clock divided by 4, to obtain it I
used a
cascade of 2 FFT , the output of the first FFT is an enable for the
second

these are the constrain I used :

FFTNET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 6 ns HIGH 50 %;

NET "out_fft_1" TNM_NET = "out_fft_1_net";
TIMESPEC "TS_out_fft_1_net" = FROM "out_fft_1_net"  TO "out_fft_1_net"
"TS_clk" * 2;

The result is just 100MHz while using a counter modulo 4 I can obtain
124MHz always on V1000,
how I can obtain better results ?? Are the constrain well setted ??




library	ieee;
use ieee.std_logic_1164.all;						
use ieee.std_logic_signed.all;

entity mult_C2_adder is
	port(in_mca :	in std_logic_vector(11 downto 0);	
		reset   :   in  std_logic ;
		clk     :   in  std_logic ;
		out_mca	:	out std_logic_vector(11 downto 0));
end mult_C2_adder;

architecture mult_C2_adder_arch of mult_C2_adder is
	signal out_fft_1 	: std_logic;
	signal out_fft_2 	: std_logic;
begin				  

	process(clk, reset)
	begin
		if reset = '1' then
			out_fft_1 <= '1';   
		elsif rising_edge(clk) then
			out_fft_1  <= not out_fft_1;
		end if;
	end process;

	process(clk, out_fft_1, reset)
	begin					
		if reset = '1' then
			out_fft_2 <= '1';   		
		elsif rising_edge(clk) then
			if out_fft_1 = '1' then
		   		out_fft_2  <= not out_fft_2;
			end if;
		end if;
	end process;
	
	process(clk, reset, out_fft_2, in_mca)
	begin
		if reset = '1' then
			out_mca <= x"000" ;
		elsif rising_edge(clk) then
			out_mca <= in_mca ;
			if out_fft_2 = '1' then
				out_mca <= ( not in_mca) + 1 ;
			end if;
		end if;
	end process;
	
end mult_C2_adder_arch ;

Article: 40566
Subject: floating pins
From: dottavio@ised.it (Antonio)
Date: 10 Mar 2002 23:22:30 -0800
Links: << >>  << T >>  << A >>
Using the cores there could be some pins that are not used in my
design, I would want to know if is better to let them be floating or
what else.

Article: 40567
Subject: MPPR question
From: dottavio@ised.it (Antonio)
Date: 10 Mar 2002 23:23:00 -0800
Links: << >>  << T >>  << A >>
I had run a multipass P&R with the following results (not so good but
it's just a test op MPPR)
according to TechXclusive article on Timing Closure I've choose a
number of routing passes of 1,
now I want to finish the routing on the best result , the 5_5_4 .
I setted the following option in ISE 4.1 GUI but I've always an error
0004, why ???

PAR effortr level 		-> Highest
Extra Effort			-> 2
Starting Placer Cost Table 	-> 4
Number of routing passes        -> 0
Cost-based clean up passes	-> 5
Delay-based clean up passes	-> 5
PAR mode			-> reentrant routing
Use Guide design file		->
C:\Tesi\Aggiunte_04_05_2002\ThinModulator_80MHz_RAM\Xilinx\mppr_result.dir\fifo_ram_thinmodulator_5_5_4\fifo_ram_thinmodulator.ncd
Guide mode			-> exact
Use timing Constrain		-> v







Release 4.1.03i - Par E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Sat Mar 09 21:25:04 2002

par.exe -f __mppr.opt


Constraints file: fifo_ram_thinmodulator.pcf

Level/      Design      Timing      Number      Run         NCD
Cost [ncd]  Score       Score       Unrouted    Time        Status
----------  ------      --------    --------    -----      
------------
5_5_4   *   176693      310202      0           36:00       Complete
5_5_1   *   177866      318440      0           52:03       Complete
5_5_5   *   178778      314719      0           35:26       Complete
5_5_2       181789      315306      0           27:11       Complete
5_5_10      182960      323646      0           38:49       Complete
5_5_3       185785      314363      0           45:39       Complete
5_5_9       185865      318533      0           34:13       Complete
5_5_12      186046      326917      0           28:41       Complete
5_5_7       186256      338809      0           35:28       Complete
5_5_6       186721      311097      0           45:19       Complete
5_5_8       195737      311476      0           46:01       Complete
5_5_11      205195      334650      0           48:23       Complete


* : Design saved.

PAR done.

Article: 40568
Subject: Re: Audio project with an FPGA?
From: Andy Main <andymain@blueyonder.co.uk>
Date: Mon, 11 Mar 2002 07:23:29 GMT
Links: << >>  << T >>  << A >>
Get into embedded systems, it'll be worth your while to get experiance with
custom CPU's and subcircuits

Andy

Joey Nelson wrote:

> I've always though that a analog style synthesizer would be fun.  With the
> fpga you could do the actual synthesis at MHz sample rates allowing the use
> of much more analog style filters (at 44.1kHz the aliasing requires pretty
> fancy dsp gymnastics to get good sounding filters) and then digital lowpass
> filter it before going to the DAC.
>
> Joey
> "David Lamb" <david.lamb@videotron.ca> wrote in message
> news:8Wyi8.31508$Fh4.854992@weber.videotron.net...
> > Hi!
> > I'm a third year student in electrical engineering and in one of my class
> we
> > have to design something with an FPGA (from altera).
> > ------
> > 'For your term project you are to choose an interesting digital system,
> > design the system in VHDL, synthesize it for the Altera family of FPGAs
> and
> > gather statistics. Your project should use between 5,000 to 200,000 logic
> > gates and can use multiple FPGAs.
> > ------
> >
> > I don't really know what can be done with FPGAs but I'd like to do
> something
> > related to audio (music). I know groups from past years designed an mp3
> > decoder. This would have been interesting a couple of years ago but now I
> > think it is over-used.
> > Any ideas are really welcome
> > Btw, this is for a 3 credit class so it is not an 'End of degree project'.
> > Thanks a lot
> > David
> >
> > Here are some proposed subject by the instructor...they don't look really
> > attractive to me!!
> >
> >   1.. Error detecting-correcting modules. Some of the more advanced
> > n-out-of-m error correcting codes (other than the Hamming codes) would be
> > very interesting topics.
> >
> >   2.. Various communication network protocols including ATM, SONET,
> > Ethernet, FDDI, DBDQ, IBM token ring, high speed serial links or any
> recent
> > development.
> >
> >   3.. Digital neural networks and fuzzy logic systems to recognize
> patterns
> > or perform processing.
> >
> >   4.. A digital system including MPEG, JPEG, speech/image or video
> > compression and decompression systems, etc. Voice sub-band coding is one
> > example; it can compress a 64 Kbit/s voice stream to about 8Kbit/s.
> >
> >   5.. RISC CPU, DSP and computer subsystems, for example, cache
> controller,
> > schedulers, PCI bus interface.
> >
> >   6.. A hardware encryption/decryption units. The RSA, PGP, and DES
> > algorithms are currently among the most popular.
> >
> >   7.. Fast designs for performing computer arithmetic algorithms, i.e.,
> > multiplication, division, square roots etc., including transform function
> > such as FFT, DCT, and Hadamard Transform.
> >
> >   8.. Image processing systems: hardware to perform image manipulations,
> > i.e. moving the view to the left or right, zooming in or out, rendering,
> > hidden line removal, etc. The fields of computer graphics or Virtual
> Reality
> > are full of interesting things to do with images.
> >
> >   9.. Any interesting system you can think of. Search the FPGA
> > manufacturer's "Application Notes" to get good ideas, and discussions of
> how
> > to implement the systems on FPGA. You can implement a system or sub-system
> > that is described in an Altera or Xilinx Application Note. Proceedings of
> > the Canadian Conference on Programmable Logic Devices describe some of the
> > research projects undertaken at other universities. There are also
> > international conference on the subject, whcih can give you ideas.
> >
> >   10.. You can also construct smaller sub-systems of a larger system. For
> > example, MPEG and JPEG compression systems often use 8x8 Discrete Cosine
> > Transforms. You could just implement the DCT, which is a sub-system of the
> > MPEG/JPEG systems.
> >
> >   11.. FPGAs have been proposed for use in DNA pattern matchers, where
> they
> > apparently outperform supercomputers. They have been proposed in Nuclear
> > Magnetic Resonance (NMR) medical machines, where they perform digital
> signal
> > processing to create a 3D image of the human brain.
> >
> >
> >
> >


Article: 40569
Subject: Cannot access header information - Modelsim Error with XilinxCoreLib ?
From: google@rauschert-online.de (Peter Rauschert)
Date: 11 Mar 2002 00:07:19 -0800
Links: << >>  << T >>  << A >>
Hi there,

I am using FPGA Advantage 5.2 with Xilinx 4.1 and trying to implement
a simple (?) 32 point FFT into my HDL Design.

When starting Modelsim an error appears in the Logfile :

--
Error: Diagram XilinxCoreLib.vfft32_v2_0.behavioral : Cannot access
header information
--

While speaking to other persons working with the same configuration I
heard, that they get the same error message using other models from
Xilinx CoreGen. But nevertheless the behavioral simulation is working
well.

The libraries are compiled and mapped correctly into HDL Designer, so
I don't know where to look for the error causing failure.

Does anybody have the same problem or even a solution ?

Thanks,

Peter Rauschert

Article: 40570
Subject: JTAG & CPLD
From: AT <antonin.hegar@tescan.cz>
Date: Mon, 11 Mar 2002 00:23:17 -0800
Links: << >>  << T >>  << A >>
Hi.

How can i use JTAG commands (as SAMPLE/PRELOAD, INTEST, ...) by CPLD CoolRunner XPLA3? 
Does exist any free utils for this purpose?

Regards
AT

Article: 40571
Subject: MP3 decoder.
From: "X. Q." <qijun@okigrp.com.sg>
Date: Mon, 11 Mar 2002 16:24:15 +0800
Links: << >>  << T >>  << A >>
Hi:

I want to know whether it's ok to fit an MP3 decoder with 32MB RAM(external)
in a 60K FPGA device?

--
Best Regards,





Article: 40572
Subject: promgen: unused area in with different values produce same checksum
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 11 Mar 2002 11:04:55 +0200
Links: << >>  << T >>  << A >>

PROMGEN seems to produce exactly the same MCS file content, although I set
different values for -c option.

I'm using M3.1i SP8 for Sun Solaris 2.6.

I have an XC17S200A to program 2 Spartan-II XC2S50-5-FG256C FPGAs.
2 XC2S50 partially fill the device. Therefore I have to set the content unused
parts. PROMGEN allows this with -c option.

I have tried

promgen -c FF
promgen -c 00

but both have the same checksum. Is that possible?? Data I/O Programmer 3980
shows the same checksum when loading MCS files into User RAM.

3980 says that unused parts of XC17S00A RAMs must be filled with FF.

Utku



Article: 40573
Subject: Re: Audio project with an FPGA?
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Mon, 11 Mar 2002 10:47:37 +0100
Links: << >>  << T >>  << A >>
David,

if you're looking for a platform for you project check out our DIGILAB
1Kx208. It has an EP1K100QC208-1 together with an audio codec from TI.
(On-board 18-bit stereo AC97 DSP Codec, 2 ADCs and 4 DACs)

http://www.elca.de/Products/prod%20d1kx208e.html

- Wolfgang


"David Lamb" <david.lamb@videotron.ca> schrieb im Newsbeitrag
news:8Wyi8.31508$Fh4.854992@weber.videotron.net...
> Hi!
> I'm a third year student in electrical engineering and in one of my class
we
> have to design something with an FPGA (from altera).
> ------
> 'For your term project you are to choose an interesting digital system,
> design the system in VHDL, synthesize it for the Altera family of FPGAs
and
> gather statistics. Your project should use between 5,000 to 200,000 logic
> gates and can use multiple FPGAs.
> ------
>
> I don't really know what can be done with FPGAs but I'd like to do
something
> related to audio (music). I know groups from past years designed an mp3
> decoder. This would have been interesting a couple of years ago but now I
> think it is over-used.
> Any ideas are really welcome
> Btw, this is for a 3 credit class so it is not an 'End of degree project'.
> Thanks a lot
> David
>
> Here are some proposed subject by the instructor...they don't look really
> attractive to me!!
>
>   1.. Error detecting-correcting modules. Some of the more advanced
> n-out-of-m error correcting codes (other than the Hamming codes) would be
> very interesting topics.
>
>   2.. Various communication network protocols including ATM, SONET,
> Ethernet, FDDI, DBDQ, IBM token ring, high speed serial links or any
recent
> development.
>
>   3.. Digital neural networks and fuzzy logic systems to recognize
patterns
> or perform processing.
>
>   4.. A digital system including MPEG, JPEG, speech/image or video
> compression and decompression systems, etc. Voice sub-band coding is one
> example; it can compress a 64 Kbit/s voice stream to about 8Kbit/s.
>
>   5.. RISC CPU, DSP and computer subsystems, for example, cache
controller,
> schedulers, PCI bus interface.
>
>   6.. A hardware encryption/decryption units. The RSA, PGP, and DES
> algorithms are currently among the most popular.
>
>   7.. Fast designs for performing computer arithmetic algorithms, i.e.,
> multiplication, division, square roots etc., including transform function
> such as FFT, DCT, and Hadamard Transform.
>
>   8.. Image processing systems: hardware to perform image manipulations,
> i.e. moving the view to the left or right, zooming in or out, rendering,
> hidden line removal, etc. The fields of computer graphics or Virtual
Reality
> are full of interesting things to do with images.
>
>   9.. Any interesting system you can think of. Search the FPGA
> manufacturer's "Application Notes" to get good ideas, and discussions of
how
> to implement the systems on FPGA. You can implement a system or sub-system
> that is described in an Altera or Xilinx Application Note. Proceedings of
> the Canadian Conference on Programmable Logic Devices describe some of the
> research projects undertaken at other universities. There are also
> international conference on the subject, whcih can give you ideas.
>
>   10.. You can also construct smaller sub-systems of a larger system. For
> example, MPEG and JPEG compression systems often use 8x8 Discrete Cosine
> Transforms. You could just implement the DCT, which is a sub-system of the
> MPEG/JPEG systems.
>
>   11.. FPGAs have been proposed for use in DNA pattern matchers, where
they
> apparently outperform supercomputers. They have been proposed in Nuclear
> Magnetic Resonance (NMR) medical machines, where they perform digital
signal
> processing to create a 3D image of the human brain.
>
>
>
>



Article: 40574
Subject: Re: exceeding 2GB limits in xilinx
From: Erwin Rol <Erwin.Rol_nospam_@Q-Soft-Engineering.com>
Date: Mon, 11 Mar 2002 11:30:00 +0100
Links: << >>  << T >>  << A >>
hamish@cloud.net.au wrote:
> B. Joshua Rosen <bjrosen@polybus.com> wrote:
> 
>>environment. I read a mention somewhere, either here or in the wine
>>group, that they intend to have a fully native version next year. The
>>GUIs are written using a tool that puts out both Windows and Unix code, I
>>think they are waiting for that tool to support Linux.
>>
> 
> UNIX GUIs (ie X11) will already work on Linux - no changes required.
> 

Well it is unlikely they use bare X11, it is more likely they use 
Motif/CDE under HP-UX and Solaris. And Motif 2.x and CDE are poorly 
supported under Linux (unless you buy a commercial version, which will 
cost you additional money). So Wine might be the easier (and cheaper) 
solution here.

- Erwin




> Hamish
> 





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