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Messages from 40750

Article: 40750
Subject: Re: Virtex BUFGDLL
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 14 Mar 2002 19:39:49 +0100
Links: << >>  << T >>  << A >>
"H.L" <alphaboran@yahoo.com> schrieb im Newsbeitrag
news:a6pkdl$2fh6$1@ulysses.noc.ntua.gr...
> Hello all,
> I use a BUFGDLL in a Virtex-E FPGA to succeed a proper distribution of a
> clock (155MHz). I instantiate BUFGDLL in my code and I did the port map.
In
> this way I have not access to the RST pin of the DLL (I want to set it '0'
> as xilinx suggests). I checked that DLL's CLKIN,CLKFB and CLK0 pins are OK
> but I cant check if the RST pin is '0' by default. How can I check if the
> RST pin is grounded or not?

Have a look at the design in FPGA editor. OR just instanciate the DLL and
BUFG seperately, which is saver, since it gives you access to the reset
(just in case)

--
MfG
Falk





Article: 40751
Subject: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 14 Mar 2002 19:42:23 +0100
Links: << >>  << T >>  << A >>
"Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag
news:aaaee51b.0203132355.60183b6b@posting.google.com...
> Hi all,
>
> on the Xilinx documentation I do find, that the bitstream
> format has a minimum of 8 '1' at the very beginning of
> the serial bitstream. Is it possible to extend the minimum
> 8 of '1' to any higher number before the start-pattern
> is being applied?

I dont know at all. Why do you want to do this? The SpartanXL are known to
be a little bit more sensitive on configuration data clocking, since the use
a length counter encoded into the first bits of the datastream.
Spartan-II(E) are much easier to use, since the configuration is much
simplified.

--
MfG
Falk





Article: 40752
Subject: Re: Xilinix FPGA width 5V IO
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 14 Mar 2002 19:44:47 +0100
Links: << >>  << T >>  << A >>
"Martin Sauer" <msauer@gmx.net> schrieb im Newsbeitrag
news:a6pqk7$cpa$06$1@news.t-online.com...
> Hello,
>
> one question: Is it possible to connect a 5V IO Device direct to the
Xilinx
> Virtex FPGA series?

Yes.
The Virtex inputs (as well as Spartan-II) are 5V tolerant. You can also
drive a 5V device with the 3.3V IO of the Virtex, when the 5V device has TTL
inputs (1.4V switching level)

Virtex-E/Spartan-IIE/Virtex-II are NOT 5V tolerant. But you can add
tolerance using a 100Ohm series resistor. But this will influence timing.

--
MfG
Falk






Article: 40753
Subject: Re: Synthesis tools comparison?
From: kayrock66@yahoo.com (Jay)
Date: 14 Mar 2002 10:47:14 -0800
Links: << >>  << T >>  << A >>
A first order observation is that the tool results are pretty close;
you know they try each others sythesizers ou and see what they produce
so the battle goes back and forth.

For your benchmarking, one thing to make sure of, is that you run the
FPGA vendor P&R tools on the EDIF output from the sythesizers and
compare the final P&R numbers.  I've found HUGE differences pre and
post place and route circuit speeds.  I can understand the marketing
reasons for doing this but still think is an underhanded method of
wooing potential customers.

Then report your results anonymously on this newgroup for everyone to
see.  This non-compete stuff is highly questionable in my view; of
course I've never done this, but occasionally an anonymous poster
comes on here and does.

Regards

"Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:<3c907f23$1@epflnews.epfl.ch>...
> hmmmmmmmm, quite strange! It can explain why I could not find any useful
> benchmark on the web for the recent verstions of these tools....
> 
> But the question remains, and it's that if there is no benchmark
> comparision, how would one choose one tool over another one? Just looking at
> the feature list and vendor claims does not look like the best way...
> 
> A year ago, I used one of my big DSP designs as benchmark for these tools
> and at that time Synplify outperformed both Leonardo and FPGA compiler for a
> Flex10K target. But today? Who knows how these tools compete against each
> other?
> 
> Should I try to downlaod the trial version of the tools, and run all of them
> on my latest designs to choose one? For each new design? :) I don't think
> so...
> 
> Regards
> Arash
> 
> 
> "S. Ramirez" <sramirez@cfl.rr.com> wrote in message
> news:H3Rj8.118337$Dl4.13204394@typhoon.tampabay.rr.com...
> > "Arash Salarian" <arash.salarian@epfl.ch> wrote in message
> > news:3c8f4cb7$1@epflnews.epfl.ch...
> > > Hello,
> > >
> > > Do you know of any recent review/benchmark comparision of major
>  synthesis
> > > tools for the FPGA? I'm interested in such a comparision between
>  Synplify,
> > > LeonardoSpectrum and FPGA compiler. And is there any major perfromance
> > > difference between these tools when targetting different FPGAs from
>  Xilinx
> > > and Altera?
> > >
> > > Best Regards
> > > Arash
> >
> >    You will be hard pressed to find these comparisons, since the license
> > agreements of these vendors say something close to "Licensee shall not ..
> > disclose the results of any benchmarking of the SOFTWARE, or use such
> > results for its own competing software development activities, without the
> > prior written permission of Blah Blah."
> >    Don't blame me, I'm just the messenger!
> > Simon Ramirez, Consultant
> > Synchronous Design, Inc.
> > Oviedo, FL  USA
> >
> >

Article: 40754
Subject: Re: Difference between Virtex-II(E) und Virtex-E
From: kayrock66@yahoo.com (Jay)
Date: 14 Mar 2002 10:54:22 -0800
Links: << >>  << T >>  << A >>
Vertex 2 came after Vertex E.  In general, FPGA families follow steps
in CMOS fab process technology.  Each new process seems to spawn a new
family.  The previous process technology becomes the "value" product
line (Spartan).

To the end user, the Vertex 2 line gives (over the Vertex E) you
higher densities, higher speeds (20% in my application), lots more on
chip ram, hardwired multipliers and new tools to debug.

Regards

Martin Sauer <msauer@gmx.net> wrote in message news:<3C904A7E.5010304@gmx.net>...
> Hi,
> 
> can you tell me the difference between the Xilinix Virtex-II and the 
> Virtex-E Series?
> Thanks for your answer.
> 
> bye
> 
> martin

Article: 40755
Subject: Re: use virtex2 DCM as delay line
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Thu, 14 Mar 2002 20:27:01 +0100
Links: << >>  << T >>  << A >>
Hi Nahum,

please tell more about the "hidden features"
of the Virtex-II chip.

-Manfred Kraus

>.......... Like most
> designs, there are a lot of hidden features that we placed in there for
> test, but may be useful for some applications.
> .........




Article: 40756
Subject: Re: Xilinix FPGA width 5V IO
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Thu, 14 Mar 2002 20:33:32 +0100
Links: << >>  << T >>  << A >>
XILINX Answer # 10835 says: 175 Ohm

-Manfred Kraus

Falk Brunner <Falk.Brunner@gmx.de> schrieb in im Newsbeitrag:
a6qsl1$gikto$4@ID-84877.news.dfncis.de...
> "Martin Sauer" <msauer@gmx.net> schrieb im Newsbeitrag
> news:a6pqk7$cpa$06$1@news.t-online.com...
> > Hello,
> >
> > one question: Is it possible to connect a 5V IO Device direct to the
> Xilinx
> > Virtex FPGA series?
>
> Yes.
> The Virtex inputs (as well as Spartan-II) are 5V tolerant. You can also
> drive a 5V device with the 3.3V IO of the Virtex, when the 5V device has
TTL
> inputs (1.4V switching level)
>
> Virtex-E/Spartan-IIE/Virtex-II are NOT 5V tolerant. But you can add
> tolerance using a 100Ohm series resistor. But this will influence timing.
>
> --
> MfG
> Falk
>
>
>
>
>



Article: 40757
Subject: Re: Proto boards for labs
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Thu, 14 Mar 2002 21:16:25 +0100
Links: << >>  << T >>  << A >>
Have you checked the Cesys FPGA boards ?
Click on "Products" at  www.cesys.com
There is a USB and a PCI Version available.
If you dont like to use the interfaces to
transmit data between a PC software and the FPGA
you can simply treat them as a "configuration
download channel".
Doubleclick on the Bit or EXO file that is
generated by the Xilinx WebPack and it will be
downloaded.
There is an discount for educational institutions,
just ask.

Sorry for making advertisment in this NG.
I couldnt resist.

Manfred Kraus
CESYS GmbH




Article: 40758
Subject: Re: Xilinix FPGA width 5V IO
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 14 Mar 2002 21:28:42 +0100
Links: << >>  << T >>  << A >>
"Manfred Kraus" <newsreply@cesys.com> schrieb im Newsbeitrag
news:a6qtja$gg5ad$1@ID-22088.news.dfncis.de...

> XILINX Answer # 10835 says: 175 Ohm

Hmm, not sure. I remember to read somewhere about 100 Ohm.

--
MfG
Falk





Article: 40759
Subject: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
From: Larry McKeogh <lmckeogh@xilinx.com>
Date: Thu, 14 Mar 2002 14:17:21 -0700
Links: << >>  << T >>  << A >>

--------------E64C3234107AE28A006C100A
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



David Brown wrote:

> Just when I think I am getting somewhere about the languages, I find out
> more and end up changing my mind yet again...
>
> Am I right in thinking that ABEL is only supported by a few vendors?

Yes - Xilinx and Lattice.  ABEL used to be owned by Data I/O.  They were
acquired by Minc Synario.  Minc Synario was acquired by Xilinx.  (If my memory
serves me correctly).  At the time of the Minc Synario acquisition Lattice
bought the source code for ABEL and the Xilinx bought the source code along with
the rights.  Xilinx has since improved the language and brought many new
features to it such as bus support and HDL simulation.

>  I have
> had a brief look at information on tools from Altera, Atmel and Xilinx, and
> none of them appear to support ABEL as far as I can see.  While this is
> going to be a Lattice/Mach project, it would be silly to spend a lot of
> effort learning a language that I can't otherwise use for other designs.

I have a fondness for ABEL because of its simplicity and direct mapping to the
device architecture.  However, I do understand the quandary you are in.  Just
providing the facts though, VHDL and Verilog do seem to be the dominant HDL
languages of the day.  It does allow easy migration between device families,
vendors, and architectures.  From a language standpoint my impressions are that
VHDL leads with about 50% of the designs being done in this format and 35% in
Verilog and about 15% in ABEL.

All of these languages are supported by the ISE WebPACK available for free from
Xilinx.  The ISE WebPACK does support HDL conversion as well.  If you have an
ABEL source and would like to convert it to either VHDL or Verilog this can be
done easily enough.  Since you have an existing design, this conversion process
may allow you to get a preview how the various languages appear.  This should be
taken as a rough preview since it is machine generated code.  While it may be
functional, it probably is not as elegant as the code could be written from
scratch.

My thoughts on this topic.
Regards,
Larry




Article: 40760
Subject: Re: XST duplicates unnecessary IOB OE FFs
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Thu, 14 Mar 2002 16:23:28 -0600
Links: << >>  << T >>  << A >>
Yes, I am already aware that a Xilinx Spartan-II IOB tri-state buffer is
active low (Took a lot of time to figure out the IOB merging rules.), so
my design already handles that part fine.
Following your suggestion, I attached "keep" attribute to tell synthesis
tool not to tinker with the only OE FF for AD[31:0] and the only OE FF
for C/BE#[3:0], but XST ignored the "keep" attribute anyway, and
duplicated them.
Just as an experiment, I attached "keep" attribute to the output FFs of
AD[31:0] and C/BE#[3:0] which I don't normally do (Because that way the
PCI IP core won't meet Tco (Tval) of 11ns.), but XST overdid that, too,
probably because Pack I/O Registers into IOBs option has some kind of
precedence over the "keep" attribute.




Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)



Brian Drummond wrote:
> 
> I had the opposite problem for a long time, until I realised the OE
> signal _into_ the ENBFFs has to be active low (mine was active high).
> Maybe changing the polarity of your OE signal would prevent this
> "optimisation"?
> 
> Or, check if your tool chain supports "dont_touch" or "preserve_signal"
> attributes on specific signals?
> 
> - Brian

Article: 40761
Subject: Re: Newbie choosing a language - Verilog, VHDL, or ABEL/CUPL
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 15 Mar 2002 12:17:33 +1300
Links: << >>  << T >>  << A >>
Larry McKeogh wrote:
> 
> 
> 
> David Brown wrote:
> 
>      Just when I think I am getting somewhere about the
>      languages, I find out
>      more and end up changing my mind yet again...
> 
>      Am I right in thinking that ABEL is only supported by a few
>      vendors?
> 
> Yes - Xilinx and Lattice.  ABEL used to be owned by Data I/O.  They
> were acquired by Minc Synario.  Minc Synario was acquired by Xilinx.
> (If my memory serves me correctly).  At the time of the Minc Synario
> acquisition Lattice bought the source code for ABEL and the Xilinx
> bought the source code along with the rights.  Xilinx has since
> improved the language and brought many new features to it such as bus
> support and HDL simulation.

The PHDL used in XPLA Coolrunner tools, bought by Xilinx, was also
an ABEL-variant.

Altera's AHDL language is also an ABEL derivative. 

Atmel offers ABEL and CUPL flows, tho ABEL is being phased out.

I would call ABEL and CUPL Tier1 HDLs, and most vendors do have
a Tier1 offering. Code porting across these Tier1 languages is not
transparent, but a lot easier than porting Assembler :)

Many of the report files, from the Fitters reading EDIF files, 
are in Tier1 language formats.

> 
>    I have  had a brief look at information on tools from Altera, Atmel
>    and Xilinx, and
>    none of them appear to support ABEL as far as I can see.
>    While this is
>    going to be a Lattice/Mach project, it would be silly to
>    spend a lot of
>    effort learning a language that I can't otherwise use for
>    other designs.
> 
> I have a fondness for ABEL because of its simplicity and direct
> mapping to the device architecture.
<snip>

 Check the devices you expect to target in future, as well as this
project:

 The higher HDLs like VHDL and Verilog do not map universally onto
the SPLDs ( mostly, they expect a EDIF import fitter ).
 They also have detail control issues that become more imporant
on the smaller devices.

 Also, ABEL and CUPL can create Test vectors, allowing hardware test in
programmers, expecially usefull on the smaller packages viz 20-44 pins.

-jg

Article: 40762
Subject: Re: Error in Foundation 4.1i
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Thu, 14 Mar 2002 17:39:53 -0600
Links: << >>  << T >>  << A >>
Peter Waldeck wrote:

> Hi,
> I'm trying to do a design for a VirtexII using ISE 4.1i and I can't
> understand the synthesis errors I'm getting.  (I am fairly new to FPGA's as
> well...)  I have two .vhd files - both of which are included in the work
> library.  The first, mygpio.vhd, tries to instantiate an entity from the
> second - pselect.vhd.  Within pselect, an architecture imp is declared.  But
> the synthesis tool doesn't like it -
>
> ERROR:HDLParsers:3281 - C:\Peripheral\peripheral/mygpio.vhd Line 81. imp is
> not an architecture body for pselect in library work.
>
> I don't understand it - are there some path settings that are wrong?  Or do
> I have to do things in a specific order?

Those slashes going both ways sure looks like something is configured
wrong, or a path was entered wrong.  If this is on a Windows PC, then
all slashes should be the "\" kind.

Jon


Article: 40763
Subject: Re: How can I install Xilinx ISE 4.1i under Linux?
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Thu, 14 Mar 2002 17:47:07 -0600
Links: << >>  << T >>  << A >>
Utku Ozcan wrote:

> Peter Ormsby wrote:
>
> > newman <newman5382@aol.com> wrote in message
> > news:e6038423.0203071338.2e220f61@posting.google.com...
> > > I saw on the Xilinx Web site that ISE4.2 is now supported on RedHat7.2
> > >
> > > Newman
> >
> > Newman,
> >
> > This is slightly misleading.  See this post:
> >
> > http://groups.google.com/groups?hl=en&scoring=d&selm=D9Bh8.13448%24Or3.14935
> > 91%40typhoon.mn.ipsvc.net
> >
> > -Pete-
>
> Google: Unable to retrieve article. (I also tried to concatenate wrapped lines,
> doesn't go either)

Worked for me.  But the gist is :
Just to be clear here, the Xilinx Linux solution is currently limited to
command-line only on WINE.

Yuck!  command line only?  How do you do schematics, floorplanner, FPGA
editor, etc.?

I have VmWare installed with Windows 2000 under Mandrake 8.1, and it is a dream.
VmWare is commercial software, but it is very cheap to educational institutions.
I think it is affordable, even to everyone else.  They do have a demo version.
My Linux/Win 2000 system has been up 97 days!  Vmware is www.vmware.com

Jon



Article: 40764
Subject: Re: high active and low active reset signal mixed in a design
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Thu, 14 Mar 2002 17:49:48 -0600
Links: << >>  << T >>  << A >>
ssy wrote:

> Hi everyone
>
> in my design, some module use high active reset, and other use low
> active reset, and the global reset is low active, so all high active
> reset is generate by pass global reset through an inverter, if this
> will cause any problem?

At least in most Xilinx parts, although you may SPECIFY an
inverter, the reset inputs to the FFs actually have a mux to select
either polarity of the reset signal, so it is actually done at each
FF separately, and the time should be the same through either
path.

Jon


Article: 40765
Subject: Re: Virtex-II : Temperature Sensing Diodes
From: Jon Elson <jmelson@artsci.wustl.edu>
Date: Thu, 14 Mar 2002 17:51:56 -0600
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> Jay,
>
> It is intended to be exactly equivalent to a 1N914 diode.

But, it is not a separate diode floating in space.  It is built on the
same substrate as the rest of the chip, and may well have protection
diodes to the Vss and Vdd, as well, so you'd need to keep those
reverse biased to properly sense the diode.

Jon


Article: 40766
Subject: Re: 32-taps FIR !
From: philippemls@hotmail.com (Philippe)
Date: 14 Mar 2002 16:37:53 -0800
Links: << >>  << T >>  << A >>
Hi

Another option is to look at the Altera FIR Compiler after downloading
the free eval to evaluate real FIR filters.

http://www.altera.com/products/ip/altera/m-alt-fir-compiler.html
or
http://www.altera.com/products/ip/altera/m-alt-iircompiler.html

--Philippe

Jacky Renaux <renaux.jacky@wanadoo.fr> wrote in message news:<2002312-184818-183279@foorum.com>...
> Hi 
> I would recommand you to look into www.andraka.com there is a 
> great tutorial on fir filter using distributed arithmetic 
> 
> I am sur It will help you 
> jacky

Article: 40767
Subject: Re: Virtex-II : Temperature Sensing Diodes
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 14 Mar 2002 16:54:55 -0800
Links: << >>  << T >>  << A >>
Jon,

Exactly correct.  There are parasitics present that require the voltages
on the diode pins stay with the limits of the power supply to the chip.

Austin

Jon Elson wrote:

> Austin Lesea wrote:
>
> > Jay,
> >
> > It is intended to be exactly equivalent to a 1N914 diode.
>
> But, it is not a separate diode floating in space.  It is built on the
> same substrate as the rest of the chip, and may well have protection
> diodes to the Vss and Vdd, as well, so you'd need to keep those
> reverse biased to properly sense the diode.
>
> Jon


Article: 40768
Subject: Re: where to start with constraining..
From: "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
Date: Thu, 14 Mar 2002 20:16:31 -0800
Links: << >>  << T >>  << A >>
thanks, Ray.  I'll do that.  Has anyone got a good, beginner-level resource
for the best way to go about assigning groups / constraining paths?

a note: I'm observing speeds over 120% faster than reported, on a well-used
device and with a really lousy clock signal; surely more accurate numbers
are possible from the tools.

JP


"Ray Andraka" <ray@andraka.com> wrote in message
news:3C90D449.992B9266@andraka.com...
> The old 4000 series stuff seemed to be pretty conservatively timed.  It
was not
> unusual to be able to clock something at 50% faster than the timing report
> stated in the lab under ideal conditions, however I would not put such an
> overclocked design into production unless you like spending your career
fixing
> production problems.  The numbers reported by the timing analysis are
worst
> case over voltage, temperature and process.  Chances are in the lab you
will
> not hit the worst case on any of the three much less all of the three.
>
> For the timing, run the static timing analyzer and set it to report paths
> failing timing.  Those are sorted so that the worst paths show up first.
From
> that report, you'll be able to see what CLBs the worst paths go through,
so
> you'll have an idea where to look.
>
> Josh Pfrimmer wrote:
>
> > Hi all,
> >     For a class (calmer down.. I'm not looking for answers to my
homework)
> > I've designed an 8-bit CPU.  Fifteen instructions, pre-fetching, branch
> > predicting, load-store, etc. etc.  So far, it cruises along at ~50MHz on
an
> > XC4010XL-3.  This is better than what's necessary for the class, but I'd
> > like to push it further.
> >
> >     Now that I have a ballpark speed, what's the best way to get started
> > specifying constraints in a .ucf?  How do I get the (old, old, old)
> > Foundation 3.1 software in the labs to tell me what the worst paths are,
so
> > that I can start picking out false paths, etc.
> >
> >     Incidentally, the post-layout timing report gives a figure of ~20MHz
fo
> > the maximum clock speed, but on the board, I'm well over 45.. is this
> > typical?  How can I get more accurate numbers out of the reports?
> >
> > Thanks for your attention
> > JoshP
>



Article: 40769
Subject: Re: Difference between Virtex-II(E) und Virtex-E
From: "Pete Fraser" <pfraser@covad.net>
Date: Thu, 14 Mar 2002 21:28:13 -0800
Links: << >>  << T >>  << A >>

"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3C90C799.E64C72C2@xilinx.com...

> Virtex E was a shrink to 0.18u of the classic Virtex architecture and
> circuitry.  Virtex E added LVDS input buffers to the original Virtex
> design, but little else was changed.
>
> Virtex II was a complete redesign in 0.15u at 1.5V for the core, that
> extended the reach of the interconnect, and buffered virtually all paths
> to reduce loading effects.  The CLB had more features added (more LUT
> RAM modes, SRL modes), as well as the horizontal carry (useful for
> p-terms).  The block RAMS got bigger, and there are more of them (4K vs
> 18K), as well as having three read/write modes instead of one in
> addition to a 18X18 multiplier in each BRAM block.

Hi Austin.

The multipliers were hella fast when the spec first came out,
and have gradually crept down in speed as new "improved"
speed files have been issued. Are you working on getting
the multipliers back to their original hoped-for speed, or will
we have to wait for the next family?



Article: 40770
Subject: Re: Proto boards for labs
From: jason.moore@xilinx.com (Jason Moore)
Date: 14 Mar 2002 23:06:51 -0800
Links: << >>  << T >>  << A >>
Nitin,
If you are a member of the university staff (meaning professor,
associate professor, a.k.a non-student) I would suggest you contact
the Xilinx University Program.  Let them know your course objectives
and how you want to use the demo boards.  Under the right
circumstances you may be able to get your demo boards and software at
no cost, or at least significantly reduced cost.  (This has been my
experience with two universities in my area).

Regarding the development board you definitely want to stay away from
the SpartanXL and get into the SpartanII for your application.

Regards,
Jason

Article: 40771
Subject: Re: minimum value for clock to output
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 15 Mar 2002 07:25:27 +0000
Links: << >>  << T >>  << A >>


Nahum Barnea wrote:

> Hi.
> Xilinx tradionally publish only max values for the clock to out
> delays.
>

This isn't quite correct. Although quite often the early datasheets don't
publish min delays when a part family matures a little they do tend to
appear. Its even possible to do a min timing simulation.

>
> I remember that there is an application note that say that the min clock
> to out value can be taken as 1/3 'rd of the max value (or 1/4 'th if
> you are a conservative person).
>

Check out the `SPEEDPRINT' utility. There's a min timing flag and it will
tell you either the min timings or a message saying they are not available.

Its some time since I dumped the min & max timings and did a comparison but
IIRC the ratio for the 1000001 timing values for original Virtex  was,
overall, about  ~ 1/3.


Article: 40772
Subject: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 15 Mar 2002 07:35:52 +0000
Links: << >>  << T >>  << A >>


Markus Meng wrote:

> Hi all,
>
> on the Xilinx documentation I do find, that the bitstream
> format has a minimum of 8 '1' at the very beginning of
> the serial bitstream. Is it possible to extend the minimum
> 8 of '1' to any higher number before the start-pattern
> is being applied?
>
> markus

I don't know why you'd want to do this but the answer, for
Virtex/Virtex-E and Spartan2 parts is yes. In fact if you look at the
bit stream produced by the Xilinx s/w for these devices you'll probably
see an initial 32 1's before the sync word.

If you want to delay configuration its probably better to hold INIT~
active until you're ready.



Article: 40773
Subject: Re: Xilinix FPGA width 5V IO
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 15 Mar 2002 07:45:34 +0000
Links: << >>  << T >>  << A >>


Falk Brunner wrote:

> "Martin Sauer" <msauer@gmx.net> schrieb im Newsbeitrag
> news:a6pqk7$cpa$06$1@news.t-online.com...
> > Hello,
> >
> > one question: Is it possible to connect a 5V IO Device direct to the
> Xilinx
> > Virtex FPGA series?
>
> Yes.
> The Virtex inputs (as well as Spartan-II) are 5V tolerant. You can also
> drive a 5V device with the 3.3V IO of the Virtex, when the 5V device has TTL
> inputs (1.4V switching level)
>
> Virtex-E/Spartan-IIE/Virtex-II are NOT 5V tolerant. But you can add
> tolerance using a 100Ohm series resistor. But this will influence timing.
>

Or, if board area and cost permit, use some QuickSwitch style parts to do the
level translation. These are just a bunch of FETs whose on resistance is very
low (5-10R) until the driving signal gets to about 0.7V below its power pin,
when it starts increasing rapidly. I think, for something like PCI, this is much
less intrusive than a bunch of 100Rs.

We tend to still use the QS3245 or Pericom equivalent but with the VCC Zener'ed
down to 3.9V, or even connected to the 3.3V supply.


Article: 40774
Subject: Re: where to start with constraining..
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 15 Mar 2002 08:39:48 +0000
Links: << >>  << T >>  << A >>


Josh Pfrimmer wrote:

> thanks, Ray.  I'll do that.  Has anyone got a good, beginner-level resource
> for the best way to go about assigning groups / constraining paths?
>
> a note: I'm observing speeds over 120% faster than reported, on a well-used
> device and with a really lousy clock signal; surely more accurate numbers
> are possible from the tools.
>

The first and most basic thing to do is very simple. Just put a `PERIOD' time
spec on your clock(s).
If you have only one clock then that's almost good enough on its own.

From then on you are basically into relaxation constraints [or tightening ones
if you've got any clock domain crossings or async input sampling].

I can remember asking a similar question to yours some years ago and getting an
answer - read the manuals. I thought that was a bit unhelpful but for once this
was absolutely the correct reply. The problem with Xil contraints is that
beyond the basic `PERIOD' it rapidly starts getting murky with issues like
contraint priority rearing up.

In contrast with most of the Xilinx tools the contraints documentation is so
poorly written [probably because `Hey we've got a constraints GUI, who needs all
that antique Gutenberg stuff!'] that the even more correct answer is to read it
N times with N >= 4.  I actually allocated a whole, otherwise free, Sunday for
this process and got to about 50% understanding of the most basic timing stuff
at the end of it.

Note that 4.X now has a single Contraints manual instead of dispersing the info
between the Development System Reference Guide, the Libraries Guide, and a few
other places as well but .... in many ways its worse, whoever wrote it had just
been told about hypertext ...

Somebody, somewhere, needs to do the world a service and write `Xilinx Timing
Constraints for Dummies' but AFAIK this magic volume doesn't exist.





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