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Messages from 40925

Article: 40925
Subject: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
From: designeree@yahoo.com (marc Nance)
Date: 18 Mar 2002 06:02:55 -0800
Links: << >>  << T >>  << A >>
The more expensive versions some of the simulators allow you to
compare waveform files, but if your not of a mind to spend the extra
cash or if you dont need to do it that often, then one simple method
is to instantiate the two designs into the same testbench say as UUT1
and UUT2. you may need to duplicate the surrounding ics or have
separate copies of interface lines (as in addrbus1(15 downto 0) and
addressbus2(15 downto 0)).
It may run slower but it is possible to have two complete copies of
the design with two different UUTs burried in them.
If you want to get concerned about differences in operation or timing,
create a portion of the testbench that flags areas where the two dont
match or are different for more than X nS.



Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:<a745ii$bo1$1@newsreader.mailgate.org>...
> I am trying to simulate two designs and compare the waveforms.
> Is there a way to do such a thing?
> So far, I tried running two instances of ModelSim XE-Starter 5.5b, but
> it won't let me run more than one instance of the program.
> Actually, comparing the current waveform result with an already
> simulated one saved to a file is adequate, but I have not been
> successful doing that.
> 
> 
> 
> Thanks,
> 
> 
> 
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)

Article: 40926
Subject: New ASIC prototyping tool
From: Ken McElvain <ken@synplicity.com>
Date: Mon, 18 Mar 2002 14:50:44 GMT
Links: << >>  << T >>  << A >>
We have just released a new version of our Certify ASIC prototyping
software that introduces automatic RTL level partitioning for
off the shelf FPGA prototyping boards.  Basically, it takes the
pre-existing traces on the board into account during the partitioning.
RTL partitioning is much better than gate level because the effect
of design changes can usually be contained to a single FPGA saving
lots of time.  In the event that you run out of pins, TDM (Time Domain
Multiplexing) can be inserted for you to conserve pins.

A variety of off the shelf board descriptions are available via our
web site which allow you to quickly try them until you find one that
fits your application best.  If you know of additional suppliers that
you have had good experiences with, please let me know.

Additional Product Info at:
	http://www.synplicity.com/products/certify.html

I'd be happy to answer any questions not covered by the above link.

Ken McElvain, CTO
Synplicity, Inc.
ken@synplicity.com



Article: 40927
Subject: Re: just bought...
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 18 Mar 2002 10:28:41 -0500
Links: << >>  << T >>  << A >>
But does it automatically add extra space between sentences?  I beieve
that this is frequently done, at least when you are justifying the
text.  The issue here is what the user sees, not what you type in.  That
is why some suggest different solutions for different fonts.  


Noddy wrote:
> 
> My 2c worth...
> 
> If anyone here uses LaTeX, you would know that it does not even allow you to
> type two spaces after a period. Since LaTeX is the generally accepted
> document format for scientific journals (IEEE, I don't know, but certainly
> the Astrophysical Journals and Astronomy Journals), I would think this
> pretty much sums up this argument.
> 
> adrian
> 
> VhdlCohen <vhdlcohen@aol.com> wrote in message
> news:20020317164614.15262.00001512@mb-mh.aol.com...
> > >--My "Webster's Standard American Style Manual" has this to say:
> > >
> > >--In typewritten material, two spaces follow a period that ends a
> > >--sentence.  If the period is followed by a closing bracket, closing
> > >--parenthesis, or quotation marks, the two spaces follow the second
> > >--mark.  In typeset material, only one space follows this period.
> > >
> > >I just checked with a technical writer friend who agrees, and
> > >says that both the Microsoft Style Manual and AP Style Manual
> > >concur. Unfortunately, I couldn't find either on line, so I can't
> > >quote the text.
> > >
> >
> > When looking at the VHDL LRM, it looks like there are two spaces after a
> > period.
> > Whether there are 2 characters spaces in the original text is hard to
> tell, but
> > visually, on printed text, it looks like 2 spaces.  The IEEE reviews all
> specs
> > before publications.
> > Ben
> > --------------------------------------------------------------------------

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40928
Subject: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 18 Mar 2002 07:48:44 -0800
Links: << >>  << T >>  << A >>
Jon,

No mystery.

These set the update rate of the taps.  0xFFH is every 36 clocks in
Virtex II, every 6 clocks in Virtex, Virtex E, Spartan II, Spartan IIE.

It is a two's complement value, so 0xFEH is every 72 clocks, etc.

By setting it to the fastest update rate, the frequency of the jitter is
increased, and the DCM is able to track phase/frequency changes better
(basically no more than ~ 65 ps per every 36 input clocks).

By setting it to the slowest update rate (0x0000H), you have the lowest
frequency jitter.

Jitter magnitude is unchanged (ie the peak to peak value is unaffected,
so the 'filter' part is a bit of a mis-nomer -- it is miss named,
really).

The 0xFFH setting is useful also if tthe output is filtered by a PLL.
PLL's filter better when the jitter is all high in frequency content.

Remember that the jitter histogram is also unchanged, and the jitter is
still random in anturre, as no frequency peaks are discernable when you
do a FFT on the collected jitter time information.

The discouraged from using recommendation is that if set too slow, we
are concerned about increasing phase run out (can't track fast enough).
Setting it too fast seems to have no problems in those cases where we
needed faster tracking.

Austin
FPGA Lab Manager
Xilinx, SJ

"J.Ho" wrote:

> Hi all,
>
> If you push into the DCM block inside Xilinx FPGA Editor, you will
> find a bunch of option boxes.  What does Factory_JF do?
>
> From Xilinx answer database, it is described as jitter filter
> function, but users are discourage to use them.
>
> So...what do they do and what do those values mean?
>
> It would be nice if I can set them to user specific center frequency
> for whatever clock input I have, not just a "high" or "low" option.
>
> Jon Ho


Article: 40929
Subject: laser programmed FPGAs
From: "luigi funes" <fuzzy8888@hotmail.com>
Date: Mon, 18 Mar 2002 18:20:37 +0100
Links: << >>  << T >>  << A >>
In addition to Clear Logic, there are manufacturers
producing laser programmed FPGAs compatible with
Altera or Xilinx? Thanks in advance.

Luigi




Article: 40930
Subject: Re: questions from a newby
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Mon, 18 Mar 2002 17:27:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <%Eil8.66405$q2.7660@sccrnsc01>,
Jimmy Zhang <zhengyu@attbi.com> wrote:
>Got two questions from a beginner here
>
>1. What is the binary format of the bit stream one downloads to  the FPGA
>that
>controls the place and route?

It depends on the vendor and part.  Xilinx has documentation for
virtex, at least.  But it is ugly.

>2. How much effort is needed for me to bypass FPGA vendor's software and
>write my own FSM machine into the binary format as in the previous question?

Use a higher level API, eg Jbits for Xilinx (not sure of altera).
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 40931
Subject: Re: just bought...
From: William Meyer <wmhmeyer@earthlink.net>
Date: Mon, 18 Mar 2002 17:46:02 GMT
Links: << >>  << T >>  << A >>
In article <3C953743.416D4F96@yahoo.com>, spamgoeshere4@yahoo.com 
says...
> 
> Why do you think the NEA and the educators want to teach children
> poorly?  What possible motivation would they have?  Do you have any
> support for your views?  

I don't claim that they *want* to perform poorly, but there is 
substantial evidence that they do perofrm poorly, and that they 
recalibrate testing methods to obfuscate the trends.
 
> BTW, I learned by the old methods, and I would not say that I am a
> poster child for good spelling in spite of the fact that I have a
> Master's degree in engineering and have been writing for the last twenty
> years!  I find that spelling (and sometimes grammar) are difficult
> subjects and I don't see how learning phonetic spelling would be so
> harmful.  In fact, it might be useful if we all tried using it rather
> than promoting this absurdly inconsistent scheme that we have now! 

I also learned by the old methods (including phonics), and had spelling 
drummed into me by my mother, who was herself a teacher. :)

> But then maybe this is not the place to debate this topic.  :)

It's not. I can e-mail some references, if you wish.

Bill

Article: 40932
Subject: Re: Hardware : How to set the RESET signal...
From: John_H <johnhandwork@mail.com>
Date: Mon, 18 Mar 2002 18:01:41 GMT
Links: << >>  << T >>  << A >>
What I plan to do in my first Virtex-II design is to using the global reset resources which don't have visibility for timing analysis but get around the timing problems by gating the
system clock during the reset.  By having all devices except for the delay counters gated off during reset, the ambiguous time to apply and remove reset is masked by the clock gate
delay.  When the delays are done (and reset is inactive for several clock cycles) everything's initialized and ready to go...  clock on!

Up until now I've been using synchronous resets when I've used resets and I try to get around simulation confusion by forcing the reset in the verilog simulator when the initialization is
otherwise confused.


Amar Agnihotri wrote:

> Hi,
> I m using a Virtex II 1M gate device.
> My questions are:
> 1. What is the best way to generate the reset signal for internal logic?
> Presently I m ORing the external reset signal with the LOCKED signals of the 5 DCMs. But this approach gives problem in POST ROUTE simulation, although it works fine in real hardware.
> 2. Can I use the BUFGMUX for this internal RESET signal, so that it will use the GLOBAL ROUTING?
>
> Note: The internal RESET Signal is synchronous RESET, so it should not violate the setup timings of the sequential logic.


Article: 40933
Subject: Re: Difference between Virtex-II(E) und Virtex-E
From: fpgaguy@aedinc.net (Jason Daughenbaugh)
Date: 18 Mar 2002 11:01:11 -0800
Links: << >>  << T >>  << A >>
"Jan Gray" <jsgray@acm.org> wrote in message news:<a73mab$g7o$1@slb7.atl.mindspring.net>...
> "Pete Dudley" wrote:
> > Do you mean SpartanII(E) vs Virtex-E? There is really no such part as a
> > VirtexII(E).
> >
> > If so I think they are exactly the same die. The SpartanII(E) is just
> > marketed to be cheap as possible. I think they accomplish that through the
> > types of packages offered.
> 
> Any '2SxE is most assuredly a different die from its brethren 'VxE, since
> the '2SxE lamentably provides only half the block RAM.
> 
> Jan Gray, Gray Research LLC

Our Xilinx Factory FAE told us that it actually does have as much
block ram as the 'VxE, but they don't make it available.  It _is_ a
'VxE in different "high-volume" packaging.  He explained to me that
testing the block RAM is actually a very significant expense in
manufacturing the chip, and with the goal of "as cheap as possible,"
they cut thier testing in half, thus you can only use half.  - At
least this is what he told us.

I would have been willing to pay a little more for all of the block
RAM, but evidently Xilinx didn't think it was worth it.  I think that
block RAM is one of the most valuable features of the chip, regardless
if if it was removed or simply disabled, it was a mistake.

Jason Daughenbaugh
Design Engineer
Advanced Electronic Designs, Inc.
http://www.aedinc.net

Article: 40934
Subject: All Digital PLL for locking DDS to input clock
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Mon, 18 Mar 2002 19:01:30 GMT
Links: << >>  << T >>  << A >>
I've built an NCO and all digital PLL.  The NCO operates at the rate of
sample_clk, and the digital PLL adjusts the NCO phase increment so the NCO
output, theta, represents the angle of a vector spinning at some ratio M/N
times another clock, data_clk.  Theta is used as the input for an sine
lookup to produce symbol_clk.  So the relationship of the clocks is:

symbol_clk = M/N * data_clk

The phase relationship is not important.  Both symbol_clk and sample_clk can
change frequencies, so the all-digital PLL must continuously track and
change the frequency of symbol_clk so maintain the above relationship.

 Everything seems to be working well, but I want to optimize everything to
increase the spectral purity of symbol_clk.  I would like to know how much
precision I need for the NCO, how to trade off lock time and spectral
purity, and over how long a period I should calculate the frequency error.
Also, should the frequency error be a function of the number of complete
rotations of theta, or also of the fractional part of theta?  Do I need to
dither the least-significant bits of theta?  I have searched, but can find
little information about such loops.  Anyone know of a source of good info?

-Kevin



Article: 40935
Subject: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
From: hdlman@hotmail.com (Tom Loftus)
Date: 18 Mar 2002 11:24:28 -0800
Links: << >>  << T >>  << A >>
Kevin,

The short answer is that there is a way to do that with Modelsim
but not with the limited XE-Starter version.

In the Modelsim SE 5.5a version I am using you can
do a "log" command and create a waveform database which by
default is called vsim.wlf.  This seems to work the same
in the Starter edition.

After you finish your reference simulation, you could rename
this file, say "vsim_ref.wlf".  Then, run a second simulation
and create another "vsim.wlf" file.  Then, use the "Compare"
menu to compare and highlight discrepancies.

However, the XE/Starter edition I have doesn't have the "Compare" 
menu option at all and trying to open a saved waveform file just
gives me a licensing error.

So, I think the other suggestions about trying to do it from
within a single simulation is your only option if all you have
to work with is the Starter version.

(Personally, I think comparing waveforms is a terrible way to
do verification but there seem to be many people who like to
do it.)

Tom


Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:<a745ii$bo1$1@newsreader.mailgate.org>...
> I am trying to simulate two designs and compare the waveforms.
> Is there a way to do such a thing?
> So far, I tried running two instances of ModelSim XE-Starter 5.5b, but
> it won't let me run more than one instance of the program.
> Actually, comparing the current waveform result with an already
> simulated one saved to a file is adequate, but I have not been
> successful doing that.
> 
> 
> 
> Thanks,
> 
> 
> 
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)

Article: 40936
Subject: Xilinx makesrc problem/questions
From: jlewis@nomadics.com (James Lewis)
Date: 18 Mar 2002 11:46:56 -0800
Links: << >>  << T >>  << A >>
Hi all,

I'm trying to use a copy of makesrc from Xilinx (which is no longer
provided by Xilinx) to format a PROM file for inclusion in C code.

Question 1:  Makesrc requires MS-DOS mode when running under Windows
98 (therefore a reboot).  Is this normal behavior?  Seems like a real
pain for a command line utility.

Question 2:  Where can I download this program?  I found it on a
website that is not related to Xilinx at all and am wondering if there
is a different version somewhere.

Thanks for any help.

James

Article: 40937
Subject: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
From: sjmeyer@www.tdl.com (Steve Meyer)
Date: 18 Mar 2002 20:22:17 GMT
Links: << >>  << T >>  << A >>
One way to do the comparing is to add the P1364 standard dumpvars
feature by adding call "$dumpvars" to the design source (preferably at time
0 or if you do not want to compare results until a given time, at the at
that time).  The first simulation will write verilog.dump file. After
simulation runs, copy file to other name and run model to compare again
with added $dumpvars.  Then just use diff command to compare results.
It turns out that a given simulator will produce identical dumpvars file
providing wire declarations in two designs are same.  This does not help
much in isolating differences.  If you want to compare results from
different related designs or two different simulators, you need simple
program to compare dumpvars files.  You can purchase fancy ones or you
can write one quite easily yourself.

Another standard P1364 approach is to use vpi_ and add value change call backs
(vpiValueChange) to signals of interest and have value change call back
routine just print time stamp and new value.  You can then use various
unix tools to compare results.
/Steve

On Mon, 18 Mar 2002 01:47:13 -0600, Kevin Brace
<ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote:
>        I am trying to simulate two designs and compare the waveforms.
>Is there a way to do such a thing?
>So far, I tried running two instances of ModelSim XE-Starter 5.5b, but
>it won't let me run more than one instance of the program.
>Actually, comparing the current waveform result with an already
>simulated one saved to a file is adequate, but I have not been
>successful doing that.
>
>
>
>Thanks,
>
>
>
>Kevin Brace (In general, don't respond to me directly, and respond
>within the newsgroup.)


-- 
Steve Meyer                             Phone: (612) 371-2023
Pragmatic C Software Corp.              email: sjmeyer@pragmatic-c.com
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402

Article: 40938
Subject: Re: questions from a newby
From: Neil Franklin <neil@franklin.ch.remove>
Date: 18 Mar 2002 21:41:54 +0100
Links: << >>  << T >>  << A >>
nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) writes:

> Jimmy Zhang <zhengyu@attbi.com> wrote:
> >Got two questions from a beginner here
> >
> >1. What is the binary format of the bit stream one downloads to  the FPGA
> >that
> >controls the place and route?
>
> It depends on the vendor and part.  Xilinx has documentation for
> virtex, at least.  But it is ugly.

Yes. To give that "ugly" a bit more shape:

In particular XAPP138 (basic bitstream block format), XAPP151
(CLB/IOB/BRAM format and framing as far as FFs/LUTs/BRAMs go) and
the JBits (actual configurable elements and config bits, at symbolic
level) docs.

Even then the actual binary values are not directly written down and
have to be extracted by experiment. So this is definitely _not_
something for beginners.


Contrary to conspiracy-theory myth, Xilinx does not keep it secret
because they dont want anyone to know. Noone less than Peter Alfke
has confirmed to me that they simply dont want the support costs of
people writing their own tools and getting in trouble. So they simply
try to discourage it by not helping. A completely acceptable stance.

But it is possible. And it is not an $mio VC job. More on the $10-30k
size. Well within the reach of an dedicated single person. But not a
beginner.


> >2. How much effort is needed for me to bypass FPGA vendor's software and
> >write my own FSM machine into the binary format as in the previous question?
>
> Use a higher level API, eg Jbits for Xilinx (not sure of altera).

I can only second that one. JBits is the entry into all the low level
stuff, at least for Virtex/Spartan-II (and possibly[1] by extension
Virtex-E/Virtex-EM/Spartan-IIE).

[1] IOBs and DLL may be a problem[2], the rest seems to be OK.
[2] either totally different or possible just the extended features
missing.


Virtex-II is presently off limits, but JBits seems to be going in
direction of including that.


Altera I have never heard of such an tool. They are far more "let the
compiler do it" types.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 40939
Subject: Re: High speed clock routing
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 18 Mar 2002 16:29:09 -0500
Links: << >>  << T >>  << A >>
This is one that I will test in simulation, but I don't hold much hope
for it to work well.  I found an article from Howard Johnson on the web
about designing T routes.  It showed that this could be made to work,
but that it was not easy.  Splitting the trace four ways, would make it
very hard to do.  Just adding a series resistor is not magic.  It is
there to match the source impedance to the trace.  Then where the trace
splits, the outbound traces need to have a higher impedance to prevent a
discontinuity.  

I have not looked up the formula for trace impedances, but HJ made it
sound like they would get pretty narrow to bring the impedance up enough
to match.  In this case it would need to be about 200 Ohms after a four
way split if you had 50 ohms before the split.  I guess I could use a
very small resistor, or no resistor, at the output of the chip.  This
would give me an impedance less than 50 Ohms and would allow the traces
after the split to be somewhat wider.  

Here is the URL http://www.sigcon.com/articles/edn/tee.htm

One problem with any analysis is the lack of good data.  One data point
I am lacking is the rise time of the clock.  In this case I need to know
the minium rise time since this is the worst case.  The maximum is 2 nS,
so it may be reasonable to assume 1 nS as a typical value.  



Pete Dudley wrote:
> 
> I would think about doing the star routing with a source termination
> resistor for each leg of the star, may 20 Ohms each. Make all the legs the
> same length and make sure there are no breaks in the ground return under
> these legs.
> 
> --
> Pete Dudley
> 
> Arroyo Grande Systems
> 
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:3C923297.57531263@yahoo.com...
> > I need to plan a high speed bus that will connect 5 devices.  They will
> > all be very closely spaced so that the lengths of the routes can be kept
> > pretty short.  The clock line is the one I am most concerned about.  It
> > is 100 MHz ECLKOUT from a TI C6711 DSP.  The five devices are an SBSRAM,
> > two SDRAMs (16 bits each for 32 bit memory) and an XC2S200E.
> >
> > The longest as-the-crow-flys run is 1.4" with 1 inch x and 1 inch y if
> > you keep it square (as layout guys like to do).  The other signals are
> > within the box these two points inscribe.
> >
> > Another approach would be to daisy chain them which would make the total
> > run about 3 inches.  What type of termination could I expect to work
> > well with this type of run?
> >
> > With such short runs, I was thinking about using no termination with a
> > star topology.  I am not even sure I need to worry about keeping the net
> > delays equal since the variation will be less than +- 1 inch or about
> > 100 pS of clock skew.
> >
> > Anyone have much experience with running high speed clocks on such short
> > runs?  Can I expect this to work well?
> >
> > I know Austin will tell me to simulate it, which I plan to do.  I am
> > just trying to get a "gut" feeling as Bob Pease would want to do.  You
> > know how easy it is to get the WRONG, right answer from a computer.
> > GIGO.
> >
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX
> >

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40940
Subject: XC2S configuration... one more time
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 18 Mar 2002 17:41:13 -0500
Links: << >>  << T >>  << A >>
I posted a question about configuration of an XC2S device using Slave
Parallel Mode (SelectMAP) a while back and got some good input.  But I
can't find the question or the answers, so I am repeating it.  Xilinx
gives names to the various configuration controls that gives me some
wrong impressions of how to connect them to a processor.  So I would
like to verify my impression just to make sure I have it straight.   

From what I understand, when configuring in SelectMAP mode, the data bus
should be connected either directly or bit reversed, depending on
whether or not you want to swap the bits in software somewhere along the
way.  The CCLK input should be connected to the WR- from the processor,
the CS- input is connected to the CSx- output from your chip or decode
logic based on addresses and not timing.  The WRITE- input should be
connected to a direction control that is timed with the address.  This
can either be an early write signal (if you have one) or an address line
that you will use like a WR- signal (addresses 0 to n for writing, n+1
to 2n for reading).  The busy can be connected to a WAIT input to the
MCU.  Or if your bus speeds are below 50 MHz, you don't need to use it
at all.  

Of course the PRGM-, INIT- and DONE are connected as expected to
discrete signals.  

The reason that I am confirming this is because I think the text in the
SpartanIIE data sheet is very confusing.  When they intend for you to
not clock data with the WRITE- signal low (or else you abort the
transfer) they say "However, to avoid aborting configuration, WRITE
must continue to be asserted while CS is asserted." which is not
correct.  You can do anything you want with WRITE-, CS- and D7:0 that
you want as long as you don't get a rising edge on CCLK.  They indicate
this elsewhere, but there are several instances of obsfucation and I
want to make sure I understand it all correctly.  

Anyone feel that I have misunderstood the SelectMAP mode?

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40941
Subject: advance in the design of controller
From: "Hristo Stevic" <hristostev@yahoo.com>
Date: Mon, 18 Mar 2002 23:51:38 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello,

Using Virtex-e, I want just an advice

In a 64 clock cycles, i want the output of my controller to 
1- swap between two values A1,A2 from 0cycle to N1 cycles
2- swap between multi values from N1+1 to N2
3- swap between the values A1,A2 from N2+1 to 63 cylces

what is the best way to implement this controller?

I can think on a toogling flip flops can implement the state 1 and 3,
and a  special state machine to implement the state 2.
a 64 counter will be used to flag the instants of the switch, but want
to know if there is  any better way to do it


thanks


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 40942
Subject: Re: High speed clock routing
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 18 Mar 2002 19:07:25 -0500
Links: << >>  << T >>  << A >>
I found another article that discusses the issue of splitting a signal
and driving stubs.  It is at
http://www.sigcon.com/articles/edn/DrivingTwoLoads.htm.  

Here Dr Howard Johnson (HJ) shows the need for series terminators at the
receivers to damp resonance oscillations.  I was surprised by this.  



rickman wrote:
> 
> This is one that I will test in simulation, but I don't hold much hope
> for it to work well.  I found an article from Howard Johnson on the web
> about designing T routes.  It showed that this could be made to work,
> but that it was not easy.  Splitting the trace four ways, would make it
> very hard to do.  Just adding a series resistor is not magic.  It is
> there to match the source impedance to the trace.  Then where the trace
> splits, the outbound traces need to have a higher impedance to prevent a
> discontinuity.
> 
> I have not looked up the formula for trace impedances, but HJ made it
> sound like they would get pretty narrow to bring the impedance up enough
> to match.  In this case it would need to be about 200 Ohms after a four
> way split if you had 50 ohms before the split.  I guess I could use a
> very small resistor, or no resistor, at the output of the chip.  This
> would give me an impedance less than 50 Ohms and would allow the traces
> after the split to be somewhat wider.
> 
> Here is the URL http://www.sigcon.com/articles/edn/tee.htm
> 
> One problem with any analysis is the lack of good data.  One data point
> I am lacking is the rise time of the clock.  In this case I need to know
> the minium rise time since this is the worst case.  The maximum is 2 nS,
> so it may be reasonable to assume 1 nS as a typical value.
> 
> Pete Dudley wrote:
> >
> > I would think about doing the star routing with a source termination
> > resistor for each leg of the star, may 20 Ohms each. Make all the legs the
> > same length and make sure there are no breaks in the ground return under
> > these legs.
> >
> > --
> > Pete Dudley
> >
> > Arroyo Grande Systems


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40943
Subject: Re: High speed clock routing
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 18 Mar 2002 16:56:01 -0800
Links: << >>  << T >>  << A >>
Rick,

The only thing that surprises me is how many people want an 'easy' solution, and
are unwilling to simulate it.

Once you simulate it, all mysteries are gone, the lights come on, the sun shines,
well, you get the idea.

Once simulated, the only issues that can go wrong are: pcb isn't fabricated per
the print, device models are completely wrong.  Since those are pretty unlikely
(at least for most reputable IC vendors and pcb houses) you are pretty safe.

Austin

rickman wrote:

> I found another article that discusses the issue of splitting a signal
> and driving stubs.  It is at
> http://www.sigcon.com/articles/edn/DrivingTwoLoads.htm.
>
> Here Dr Howard Johnson (HJ) shows the need for series terminators at the
> receivers to damp resonance oscillations.  I was surprised by this.
>
> rickman wrote:
> >
> > This is one that I will test in simulation, but I don't hold much hope
> > for it to work well.  I found an article from Howard Johnson on the web
> > about designing T routes.  It showed that this could be made to work,
> > but that it was not easy.  Splitting the trace four ways, would make it
> > very hard to do.  Just adding a series resistor is not magic.  It is
> > there to match the source impedance to the trace.  Then where the trace
> > splits, the outbound traces need to have a higher impedance to prevent a
> > discontinuity.
> >
> > I have not looked up the formula for trace impedances, but HJ made it
> > sound like they would get pretty narrow to bring the impedance up enough
> > to match.  In this case it would need to be about 200 Ohms after a four
> > way split if you had 50 ohms before the split.  I guess I could use a
> > very small resistor, or no resistor, at the output of the chip.  This
> > would give me an impedance less than 50 Ohms and would allow the traces
> > after the split to be somewhat wider.
> >
> > Here is the URL http://www.sigcon.com/articles/edn/tee.htm
> >
> > One problem with any analysis is the lack of good data.  One data point
> > I am lacking is the rise time of the clock.  In this case I need to know
> > the minium rise time since this is the worst case.  The maximum is 2 nS,
> > so it may be reasonable to assume 1 nS as a typical value.
> >
> > Pete Dudley wrote:
> > >
> > > I would think about doing the star routing with a source termination
> > > resistor for each leg of the star, may 20 Ohms each. Make all the legs the
> > > same length and make sure there are no breaks in the ground return under
> > > these legs.
> > >
> > > --
> > > Pete Dudley
> > >
> > > Arroyo Grande Systems
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 40944
Subject: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 18 Mar 2002 19:04:16 -0600
Links: << >>  << T >>  << A >>
Thanks, Utku.
Your solution was the best solution among the tips I got.
I will also like to thank everyone else for giving me various other
suggestions.
I may try out some of the suggestions later, but for the time being, I
wanted a quick fix type of solution that didn't take too much time to
implement.
So, following your advise, I created a new top module, and instantiated
the two modules, and compared the results.
In the process, I found why one of the design was finishing faster than
the other one.
I already knew that one of the design was finishing a bit faster than
the other one before I posted the question, but it was hard to pin point
the location where the one started to deviate from another.



Thanks,



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)




Utku Ozcan wrote:
> 
> 
> Or just call the testbench twice in a much higher block "dummy":
> 
> module dummy ();
> 
> testbench tb_a ();
> testbench tb_b ();
> 
> endmodule
> 
> But simulation will be twice slower, so why not running each of them
> separately and then post-processing testvectors later on?
> 
> Utku

Article: 40945
Subject: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 18 Mar 2002 19:11:26 -0600
Links: << >>  << T >>  << A >>
Yes, someone else also suggested that I should instantiate two modules
from a new top module, so I did that, and I finally figured out what was
going wrong.
I am pretty poor, so all I can afford is ModelSim XE-Starter, therefore
paying for the full version of ModelSim (PE or even XE) is not really an
option.



Thanks,



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



marc Nance wrote:
> 
> The more expensive versions some of the simulators allow you to
> compare waveform files, but if your not of a mind to spend the extra
> cash or if you dont need to do it that often, then one simple method
> is to instantiate the two designs into the same testbench say as UUT1
> and UUT2. you may need to duplicate the surrounding ics or have
> separate copies of interface lines (as in addrbus1(15 downto 0) and
> addressbus2(15 downto 0)).
> It may run slower but it is possible to have two complete copies of
> the design with two different UUTs burried in them.
> If you want to get concerned about differences in operation or timing,
> create a portion of the testbench that flags areas where the two dont
> match or are different for more than X nS.
>

Article: 40946
Subject: Re: High speed clock routing
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 18 Mar 2002 20:47:36 -0500
Links: << >>  << T >>  << A >>
I think that most people don't want to simulate because it is unfamiliar
territory for them.  I am in that camp.  I would perfer not to, but I am
not willing to take a chance on 100 MHz clock lines which may be run up
to 133 when the faster chip comes out.  Yes, I know that the clock speed
is not what is important, but rather it is the edge rate.  But to allow
the clock to speed up the edge rate will also go up.  

But I am concerned that I will not have the correct data when I perform
the simulation.  I still need to close the loop to get valid data that
reflects my PCB.  That is an item that I will have to research further. 
I am going to start with an old copy of the Motorola ECL data book.  It
has a good chapter on Stripline and Microline (if I am remembering the
terms correctly) and calculating all the relevant characteristics... if
I can get the appropriate data on the PCB materials.  

Lots of places to make mistakes... unless you have a pretty good idea of
the answer before you start.  



Austin Lesea wrote:
> 
> Rick,
> 
> The only thing that surprises me is how many people want an 'easy' solution, and
> are unwilling to simulate it.
> 
> Once you simulate it, all mysteries are gone, the lights come on, the sun shines,
> well, you get the idea.
> 
> Once simulated, the only issues that can go wrong are: pcb isn't fabricated per
> the print, device models are completely wrong.  Since those are pretty unlikely
> (at least for most reputable IC vendors and pcb houses) you are pretty safe.
> 
> Austin
> 
> rickman wrote:
> 
> > I found another article that discusses the issue of splitting a signal
> > and driving stubs.  It is at
> > http://www.sigcon.com/articles/edn/DrivingTwoLoads.htm.
> >
> > Here Dr Howard Johnson (HJ) shows the need for series terminators at the
> > receivers to damp resonance oscillations.  I was surprised by this.
> >
> > rickman wrote:
> > >
> > > This is one that I will test in simulation, but I don't hold much hope
> > > for it to work well.  I found an article from Howard Johnson on the web
> > > about designing T routes.  It showed that this could be made to work,
> > > but that it was not easy.  Splitting the trace four ways, would make it
> > > very hard to do.  Just adding a series resistor is not magic.  It is
> > > there to match the source impedance to the trace.  Then where the trace
> > > splits, the outbound traces need to have a higher impedance to prevent a
> > > discontinuity.
> > >
> > > I have not looked up the formula for trace impedances, but HJ made it
> > > sound like they would get pretty narrow to bring the impedance up enough
> > > to match.  In this case it would need to be about 200 Ohms after a four
> > > way split if you had 50 ohms before the split.  I guess I could use a
> > > very small resistor, or no resistor, at the output of the chip.  This
> > > would give me an impedance less than 50 Ohms and would allow the traces
> > > after the split to be somewhat wider.
> > >
> > > Here is the URL http://www.sigcon.com/articles/edn/tee.htm
> > >
> > > One problem with any analysis is the lack of good data.  One data point
> > > I am lacking is the rise time of the clock.  In this case I need to know
> > > the minium rise time since this is the worst case.  The maximum is 2 nS,
> > > so it may be reasonable to assume 1 nS as a typical value.
> > >
> > > Pete Dudley wrote:
> > > >
> > > > I would think about doing the star routing with a source termination
> > > > resistor for each leg of the star, may 20 Ohms each. Make all the legs the
> > > > same length and make sure there are no breaks in the ground return under
> > > > these legs.
> > > >
> > > > --
> > > > Pete Dudley
> > > >
> > > > Arroyo Grande Systems
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 40947
Subject: Re: How to deal with a high fan-out net in FPGA.
From: kayrock66@yahoo.com (Jay)
Date: 18 Mar 2002 17:51:06 -0800
Links: << >>  << T >>  << A >>
Low tech solution- You could go off chip then back into your global reset net.

"Kelvin Hsu" <qijun@okigrp.com.sg> wrote in message news:<3c9547bc@news.starhub.net.sg>...
> Hi:
> 
> I want to know how am I going to deal with a high fan-out net
> in a Spartan-II chip. The basic idea is that I have to delay the reset
> signal from another chip for 64 clock cycles in my chip. After that I
> use this delayed signal to initialize my registers. I have arround 100
> registers in my design.
> 
> I tried to instantiate a BUFG for my delayed reset,but ISE won't
> synthesize it.
> 
> Thanks for your advice.

Article: 40948
Subject: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 18 Mar 2002 19:54:00 -0600
Links: << >>  << T >>  << A >>
Tom Loftus wrote:
> 
> Kevin,
> 
> The short answer is that there is a way to do that with Modelsim
> but not with the limited XE-Starter version.
> 
> In the Modelsim SE 5.5a version I am using you can
> do a "log" command and create a waveform database which by
> default is called vsim.wlf.  This seems to work the same
> in the Starter edition.
> 
> After you finish your reference simulation, you could rename
> this file, say "vsim_ref.wlf".  Then, run a second simulation
> and create another "vsim.wlf" file.  Then, use the "Compare"
> menu to compare and highlight discrepancies.
> 
> However, the XE/Starter edition I have doesn't have the "Compare"
> menu option at all and trying to open a saved waveform file just
> gives me a licensing error.
> 


        I didn't say it in so many words, but I did try open a .wlf file
which supposedly contains already simulated waveform information, but
each time I tried opening it, I also got licensing errors.
Do you know if this feature is disabled only in ModelSim XE-Starter, or
is it disabled in ModelSim XE which is a paid version?
        Another thing I noticed was when I tried to open a .wlf file
with a ModelSim XE-Starter license that's fairly old, opening a .wlf
file caused a licensing error, but when I tried with a fairly new
license, I didn't get licensing errors, but I still couldn't figure out
how to open a .wlf file correctly.
I believe I got the old ModelSim XE-Starter license when the latest
version was 5.3, but I can be wrong with that (I don't remember when I
got the license.).
However, I got the the newer license after Xilinx started distributing
5.5b.
        Your design environment sounds to me that you have access to a
full version at work (Modelsim SE 5.5a), but not at home or for personal
use, so you know something about the limitations of ModelSim XE-Starter.
Is that because of those license lock thing (flexlm) ModelSim uses? (I
guess that is pretty obvious.)




> So, I think the other suggestions about trying to do it from
> within a single simulation is your only option if all you have
> to work with is the Starter version.
> 


        Yes, I some other people also suggested that, so I tried it, and
it worked.
I had to make copies of some design files, and modify some .do files,
but I was still able to simulate both designs, and compared them.




> (Personally, I think comparing waveforms is a terrible way to
> do verification but there seem to be many people who like to
> do it.)
> 
> Tom
> 


        Yes, I do understand that the method I used was not a very good
one (Wasn't this method called a golden vector method or something like
that? I believe I read that in Writing Testbenches by Janick Bergeron
some time ago.).
I am still in the process of implementing various features, so I am not
ready to spend serious amount of time in verification at this point, but
I still wanted to do some simple debugging, so that my design works, at
least partially.
After I finish the implementation, I am going to spend much more time in
verification.



Thanks,



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 40949
Subject: Re: High speed clock routing
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 18 Mar 2002 20:03:11 -0600
Links: << >>  << T >>  << A >>
What are the names of "most reputable pcb houses?"
Sort of off topic, but how many PCB houses offer lead-free solder?
Okay, maybe PCB houses don't do SMT, or do they? (Obviously I don't know
much about PCB related stuff)
Also, how much does it cost to make a PCI card in prototype quantity
(one or two) with a Spartan-II FG456 package (Fine-Pitch BGA 456 pin)
and an SO-DIMM socket on it?



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



Austin Lesea wrote:
> 
> Rick,
> 
> The only thing that surprises me is how many people want an 'easy' solution, and
> are unwilling to simulate it.
> 
> Once you simulate it, all mysteries are gone, the lights come on, the sun shines,
> well, you get the idea.
> 
> Once simulated, the only issues that can go wrong are: pcb isn't fabricated per
> the print, device models are completely wrong.  Since those are pretty unlikely
> (at least for most reputable IC vendors and pcb houses) you are pretty safe.
> 
> Austin
>



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