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Messages from 41150

Article: 41150
Subject: Re: more questions
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Thu, 21 Mar 2002 13:02:42 -0600
Links: << >>  << T >>  << A >>
Jimmy Zhang wrote:
> 
> For all the spartan II FPGA based PCI cards, can I expect the bandwidth to
> be a full
> blown  33Mx4 MB/s?
> 


        Although, I don't have direct knowledge regarding your question,
I have seen several postings where people said to get close to PCI's
theoretical maximum bandwidth, you have to do bus master transfer.
However, how much bandwidth you can get is chipset (host PCI bridge)
dependent, and in general, Intel chipset tends to be better than other
chipset vendors' chipsets.
Also, if you have other PCI devices on the same PCI bus, they will also
consume some of the bandwidth.
If you really need a lot of bandwidth, you should get a motherboard that
supports 64-bit PCI or 66MHz PCI, and a PCI prototype card that supports
either one or both.



> Also some cards seem to have implemented the PCI logic onto the FPGA
> already. One
> manufacture claims to have used 15K gates on the FPGA, and have left 135K
> gates left
> on the FPGA for other things. Just curious, if I download the code onto the
> FPGA, will
> I overwrite the orignal PCI logic, and from a HDL coding perspective, how do
> I interface
> the backend processing logic with their PCI design.
> 
> Jimmy


        The PCI IP core consumes only 15K gates and rest of the 135K
gates left thing sounds to me you are reading Insight Elctronics
Spartan-II PCI Development Kit's brochure.
First of all, Xilinx uses this marketing term "system gates" where they
count RAM blocks as gates.
The actual gate count of Spartan-II XC2S150 is far less than 150K gates,
and I will say it is around 20K to 25K ASIC gates, but I am not 100%
positive about that.
Counting the number of 4-input LUT (Look Up Tables) is probably the best
way to figure out the true gate count.
        No, you won't be able to overwrite the backend section only, and
swap it with your backend because to create a bit stream file for
Spartan-II, you have to P&R the PCI IP core with your backend design,
and then you can finally create a bit stream file.
To get the Spartan-II PCI card working, you will have to pay $2,000 to
Xilinx or Insight Electronics to obtain a Spartan-II LogiCORE PCI
license, use opencores.org PCI IP core , or develop your own.
I did my own PCI IP core with ISE WebPACK, and it actually worked in two
computers I tested it, so it is not impossible to do your own, but it
takes some time.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 41151
Subject: Re: synplify, quartus II 2.0
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Thu, 21 Mar 2002 13:12:52 -0600
Links: << >>  << T >>  << A >>
LeonardoSpectrum-Altera is not Synplify . . . 
LS-Altera is in general pretty buggy piece of software from my
experience using it (2001_1a_028 and OEM2002a_Altera_NIGHTLY_14), so I
am not surprised that you are having problems.
Did you start LS-Altera directly or did you try to use QII's NativeLink?
LS-Altera + QII's NativeLink is broken when you use FLEX10KE/ACEX1K
because some idiot at Altera got a file name wrong of the NativeLink
script.
It took me two days to figure out what was going wrong.
Which device are you targeting?



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)



kudla wrote:
> 
> My Synplify (Leonardo Spectrum OEM2002a_Altera_NIGHTLY_14) crashes soon
> after start.
> (License passes - that I can see before window disapears). I have w2k sp2
> and Quartus II 2.0.
> Does somebody know what I can do?
> Maciek

Article: 41152
Subject: Where to get docs regarding WEP Encryption
From: kenny@trangosys.com (Kenny)
Date: 21 Mar 2002 11:13:43 -0800
Links: << >>  << T >>  << A >>
Dear All,

I want to study WEP Encryption and implement it by FPGA later. May I
know where to get documents/books regarding WEP Encryption ?

Please advise,

Kenny

Article: 41153
Subject: Re: more questions
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Thu, 21 Mar 2002 13:15:09 -0600
Links: << >>  << T >>  << A >>
Get some kind of a PCI IP core, and synthesize it with your design.
Then Place & Route (P&R) it to see how much device resources the whole
design consumes.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 41154
Subject: Re: how to deal with signal pass through two clock domain
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Thu, 21 Mar 2002 11:24:17 -0800
Links: << >>  << T >>  << A >>
ssy wrote:
> 
> > Make sure the 25MHz is assigned to a global clock pin
> > and that the counter output is resynched to the 33 MHz
> > clock before it is read.
> but how to resynched to 33Mhz?
> 
> and my problem is that:
> the muxed clock go down the clock tree, and become an logic signal

To eliminate the clock skew warning,
I am suggesting that you make two counters
and select one count or the other
instead of gating the clocks.

 -- Mike Treseler

Article: 41155
Subject: Re: Possibility of RTL and Gate-level simulation dont match?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Thu, 21 Mar 2002 11:35:23 -0800
Links: << >>  << T >>  << A >>
Kelvin Hsu wrote:
> 
> Hi,
> 
> I am using Spartan-II chip, I want to know how much possibility that
> the RTL and gate-level simulation don't match?
> When they don't match, how can I detect that? It seemed that the synthesis
> report in ISE 4.1 doesn't give me a warning or error?

An asynchronous race condition can give this symptom.
Check your design for latches or asynchronous feedback.
Run a static timing check.

 -- Mike Treseler

Article: 41156
Subject: PCI interface
From: "Jimmy Zhang" <zhengyu@attbi.com>
Date: Thu, 21 Mar 2002 20:03:37 GMT
Links: << >>  << T >>  << A >>
Hi,

  I would also like to know if anyone is aware of PCI FPGA card where the
reconfiguration of FPGA card can be done from the devices calls via PCI
interface.

Jimmy



Article: 41157
Subject: Re: synplify, quartus II 2.0
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Thu, 21 Mar 2002 20:21:15 -0000
Links: << >>  << T >>  << A >>
Personally I find Leonardo 2001_1d to be fairly good albeit not being driven
via Quartus, but rather having Leonardo drive Quartus. (or having ActiveHDL
drive both)

I only had a brief glance at Leonardo 2002 but was discouraged by some of
the known problems. I think I'll wait till next version. Could you try with
2001_1d?

Leonardo 2001_1d certainly does better at synthesis than Quartus itself,
though this difference may be minimal if you use a lot of the megawizard
functionality.

I suggest you start up Leonardo on its own without Quartus and try and enter
a design or synthesise one of the examples.

If all goes well, then investigate using it more directly with Quartus 2

BTW You have plenty of RAM I take it? You'll need it with both running.

Paul

"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in
message news:a7darn$s1n$1@newsreader.mailgate.org...
> LeonardoSpectrum-Altera is not Synplify . . .
> LS-Altera is in general pretty buggy piece of software from my
> experience using it (2001_1a_028 and OEM2002a_Altera_NIGHTLY_14), so I
> am not surprised that you are having problems.
> Did you start LS-Altera directly or did you try to use QII's NativeLink?
> LS-Altera + QII's NativeLink is broken when you use FLEX10KE/ACEX1K
> because some idiot at Altera got a file name wrong of the NativeLink
> script.
> It took me two days to figure out what was going wrong.
> Which device are you targeting?
>
>
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)
>
>
>
> kudla wrote:
> >
> > My Synplify (Leonardo Spectrum OEM2002a_Altera_NIGHTLY_14) crashes soon
> > after start.
> > (License passes - that I can see before window disapears). I have w2k
sp2
> > and Quartus II 2.0.
> > Does somebody know what I can do?
> > Maciek



Article: 41158
Subject: HELP me, about chipscope analyzer
From: "Changchun WAN" <ccwan@phys.sinica.edu.tw>
Date: Fri, 22 Mar 2002 04:46:50 +0800
Links: << >>  << T >>  << A >>
Hi

When I opened the serial MultiLINX port in chipscope I got an error message
"Internal Error: Failed to execute api function."

Then it initialized the the port and reported success. I can setup the
boundary scan chain and got correct device information, but when I
downloaded the .bit to the device another error message appeared:

"Core version 0.0 is not valid or not supported. Please verify that all
instruction register lengths in the JTAG chain are properly specified."

But in fact the instruction register length is right and got by JTAG chain
automatically. (only XILINX device in the chain)

The device can work after download, but I can not setup trig signal etc. The
error message is also "Core version 0.0 is ... "

Who can give me some suggestion? Thanks!

By the way, my MultiLINX had never worked successfully with USB cable. Does
Win2000 need install some driver?

Changchun



Article: 41159
Subject: Re: Can't program XC4010 with JTAG without BSCAN???
From: Arthur <>
Date: Thu, 21 Mar 2002 12:58:59 -0800
Links: << >>  << T >>  << A >>
I believe if you hold INIT low upon powerup, this will stave off the FPGA attempting to configure itself via serial mode. At this point, interface with the device using JTAG and it will allow itself to be programmed with your pattern. This way you can configure the part w/o using the BSCAN component. However the downside to this is that you won't be able to perform JTAG operations (such as erase or re-program) while the device is in operation unless you toggle PROG and hold INIT low again...

Arthur

Article: 41160
Subject: coregen under Solaris
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: Thu, 21 Mar 2002 21:05:47 GMT
Links: << >>  << T >>  << A >>

Whenever I launch coregen (4.1iSP3) under Solaris 8 I get the windows,
but the contents is party empty. And the watch cursor is active
indefinitely (at least for 24 hours).

If I move the windows over overlap it using a different window I get
parts of the window redrawn, but I can't get it to update the window
to make the application usable.

I'm using a X86 based PC running Linux as a X11 server against the SUN
machine where I launch coregen. I have no problems running
floorplanner this way. I would blame it on Java, but somebody might
have a better explanation or even a solution?

Petter

-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 41161
Subject: Re: cpga : Converting PAL design
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 21 Mar 2002 22:52:47 +0100
Links: << >>  << T >>  << A >>
"Tibor" <tibi@mail.intruder.hu> schrieb im Newsbeitrag
news:ee75b27.-1@WebX.sUN8CHnE...
> How can i convert PAl design equation, for 9572

Simply type the equations, just using VHDL/Verilog syntax (which is almost
identical to ABEL etc.)

--
MfG
Falk





Article: 41162
Subject: Re: Xilinx JTAG Cables
From: engr <engr@none.com>
Date: Thu, 21 Mar 2002 14:27:47 -0800
Links: << >>  << T >>  << A >>
William Lenihan wrote:
> 
> Subject: Parallel Cable III/IV
> 
> These JTAG pods have attachments called "flying leads", where end
> #1 is a fixed connector to plug into the pod (i.e., JTAG row of pins)
> and
> end #2 is the actual flying leads to connect to the target hardware.
> 
> That's great for prototype & engineering development, but for
> production, the actual
> flying leads @ end #2 can easily be mis-placed by technicians on the
> assembly
> line.
> 
> Is there any readily available, fixed-connection cables (and mating
> sockets) for the Xilinx-programming-pod-2-target-hardware connection?
> Or is that some tooling that every customer just has to make on their
> own
> w/ catalog parts from Newark, Digi-Key, etc., ?
-------------------------------------------------------

As someone else recently posted, Mouser has the AMPMODU connectors
and receptacle pins that Xilinx uses.  You can buy the 9x1 connectors
which are Mouser p/n 571-1874995, and the pins, p/n 571-1871958
and make your own cables.  You'll also need the keying plugs, p/n
571-870772.   http://www.mouser.com


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Article: 41163
Subject: Re: coregen under Solaris
From: acher@in.tum.de (Georg Acher)
Date: 21 Mar 2002 23:11:17 GMT
Links: << >>  << T >>  << A >>
In article <87elid4pvp.fsf@filestore.home.gustad.com>,
 Petter Gustad <newsmailcomp1@gustad.com> writes:
|> 
|> Whenever I launch coregen (4.1iSP3) under Solaris 8 I get the windows,
|> but the contents is party empty. And the watch cursor is active
|> indefinitely (at least for 24 hours).
|> 
|> If I move the windows over overlap it using a different window I get
|> parts of the window redrawn, but I can't get it to update the window
|> to make the application usable.
|> 
|> I'm using a X86 based PC running Linux as a X11 server against the SUN
|> machine where I launch coregen. I have no problems running
|> floorplanner this way. I would blame it on Java, but somebody might
|> have a better explanation or even a solution?

This is a bug in the Solaris JDK, happens also with the crappy installer and all
other Java-based tools (eg. xpower).

But if you already have Linux, why don't you run coregen straight on your own
box? After all it is Java, write once, crash everywhere ;-)

I have modified the coregen startup script for that, for me it runs perfectly 
with JDK1.3 for Linux:

http://wwwbode.cs.tum.edu/~acher/xilinx/

-- 
         Georg Acher, acher@in.tum.de         
         http://www.in.tum.de/~acher/
          "Oh no, not again !" The bowl of petunias          

Article: 41164
Subject: Interconnect system for multiple FPGA's ?
From: Craig McAdam <craig.mcadam@ntlworld.com>
Date: Thu, 21 Mar 2002 23:46:12 +0000
Links: << >>  << T >>  << A >>
I'm implementing a board design that will include some FPGA prototyping
capability in addition to other required functions. There will probably
be multiple FPGA's, two or four perhaps, most likely Xilinx Virtex-E.
Perhaps also some FPGA expansion capability either by populating more
FPGA's or by a mezzanine card.
 
Anybody got any good pointers to implementing an interconnect bus
between the FPGA's ? I guess there are two possibilities -

1. Each FPGA contains a number of individual modules that are complete
in themselves and communicate with each other within each FPGA and also
with the other FPGA

2. Resources are shared between FPGA's to allow larger designs to be
implemented.

Thanks,

Regards, Craig

Article: 41165
Subject: Re: High speed clock routing
From: bobsrefusebin@hotmail.com (Bob Perlman)
Date: 21 Mar 2002 16:19:02 -0800
Links: << >>  << T >>  << A >>
John_H <johnhandwork@mail.com> wrote in message news:<3C9A0EF5.CDD53F89@mail.com>...
> Bob,
> 
> Isn't the upper limit of intrinsic impedance that of free space?  Squareroot of (absolute
> permittivity divided by absolute permeability) is about 377 ohms, isn't it?  I thought one
> couldn't get any higher than that.
> 
> Your insights into why 1300 ohms would be the better answer are much appreciated.

I found the formula for wire-over-plane in two places: appendix C of
Howard Johnson's book, and page 150 of Brian C. Wadell's Transmission
Line Handbook.  In both cases, the formula is [377/(2*pi)]*ln(4h/d),
where h is the height above the plane and d the distance between the
center of the wire and the top of the plane.  Wadell states that the
formula is good for h/d >> d, which certainly is true in this case.

I used 450-ohm ladder line of the type Austin mentioned to feed a ham
radio antenna as a kid.  The impedance equation (276log(2S/d), where S
is center to center distance and d is the diameter of the conductors)
was a typical question on the amateur radio exam.  There's no upper
bound, but after a point you have to either accept that you can't get
a higher impedance or route half the line through the neighbor's yard.

I'm not an EMC guy, but aren't we conflating two related-but-different
things?  The impedance of free space is the E/H ratio of an
electromagnetic field; trace impedance is dV/di.  Anyone care to
clarify further?

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com

> 
> - John_H
> 
> 
> Bob Perlman wrote:
> 
> > > > Here's a question that I ask students when I hold signal integrity
> > > > courses: Suppose I'm in the space shuttle and I have a length of #30
> > > > AWG wire, and there's an infinitely wide ground plane sitting on the
> > > > earth's surface 160 miles below.  What's the impedance?  Zillions of
> > > > ohms?  Any guesses?
> > >
> > > I would not have a clue.  But I want to know how you plan to measure it
> > > and verify your answer!
> >
> > It's about 1300 ohms.  I'll take the space shuttle flight if you'll
> > set up the ground plane (and remove it before the shuttle hits it).

Article: 41166
Subject: Re: Possibility of RTL and Gate-level simulation dont match?
From: "Kelvin Hsu" <qijun@okigrp.com.sg>
Date: Fri, 22 Mar 2002 08:39:51 +0800
Links: << >>  << T >>  << A >>
huh...
well...my experience was that everytime RTL and gatelevel simulation match,
thus
later i overlook gate level simulation and skipped them anyway.

second prob...er...i am soldier not the commando. i just identify the
registers and signals etc...
and the code works...exactly what the problem they are trying to solve i
feel like the boss is
waving a hammer to hit an ant...:-(

The problem here...actually i have solved them already, after many hassles
to probe synthesized
register names...it's quite troublesome why synthesizer don't give a
well-versed names for the wires
also...whenever they could...i later wire these names to outputs to
monitor...any easier ways to
monitor wire names in netlist from design-compiler and XST?

--
Best Regards,
Email: qijun@okigrp.com.sg
"Spam Hater" <spam_hater_7@email.com> wrote in message
news:3c99f70b.2196051@64.164.98.7...
>
> I see two problems here:
>
>     "i am experienced HDL designer anyway"
>
> No, you're not.  Sorry, but an experienced HDL designer has fought his
> way through many pre-post synthesis mismatches.
>
>     "I still don't know what problem the design was intended to solve"
>
> This is also a serious problem.  If you don't know what it is to do,
> how can you tell if it's doing it?
>
> And as to your last question: "how can I detect fatal bugs in my code"
> the answer is:  Knowledge, and experience.
>
>
> On Thu, 21 Mar 2002 09:35:14 +0800, "Kelvin Hsu" <qijun@okigrp.com.sg>
> wrote:
>
> >sure it's possible since i need to match the result with a C program,
while
> >i tried best
> >to match the C result, gate level simulation is not correct. One
constraint
> >is that after I
> >finished RTL and everything, I still don't know what problem the design
was
> >intended to
> >solve...faint!
> >While RTL simulation and synthesis all pass, w/o major error or
warning...i
> >am experienced
> >HDL designer anyway...prob is gate-level won't pass.
> >I want to know how can I detect fatal bugs in my code, besides RTL simu
and
> >warning in ISE 4.1?
> >
> >
> >
> >
> >
> >"Jay" <kayrock66@yahoo.com> wrote in message
> >news:d049f91b.0203201704.55c58ac8@posting.google.com...
> >> How possible is it?  Well if you're a new HDL guy then it's very
> >> possible, and if you're not, then its still possible.  You should be
> >> able to run the same test bench on RTL or gates and have them both
> >> pass.
> >>
> >> "Kelvin Hsu" <qijun@okigrp.com.sg> wrote in message
> >news:<3c97f13b@news.starhub.net.sg>...
> >> > Hi,
> >> >
> >> > I am using Spartan-II chip, I want to know how much possibility that
> >> > the RTL and gate-level simulation don't match?
> >> > When they don't match, how can I detect that? It seemed that the
> >synthesis
> >> > report in ISE 4.1 doesn't give me a warning or error?
> >
> >
>



Article: 41167
Subject: Re: Maximum device usage for successful PAR
From: Ray Andraka <ray@andraka.com>
Date: Fri, 22 Mar 2002 00:51:53 GMT
Links: << >>  << T >>  << A >>
Floorplanning will make it much easier to get the high utilization numbers.  The
automatic placement does a pretty lousy job at placing stuff, so even if it fits
it all in you are likely to not meet timing (if timing is also easy, you can
probably rethink your design to get the utilization down by trading clock speed
for hardware).  If you have RPM macros in the design, the placer can run into
trouble at surprisingly low utilizations bedause it does not try placing RPMs
first.  Also, as someone already mentioned, the mapper packs logic together in
slices somewhat blindly.  It can and will underpack slices and wind up with more
slices than are available.  THis may also be your fault if you have lots of
clocks in your design (don't laugh, I've seen it too many times) or if there are
alot of unique clock enables. or direct resets used.

John_H wrote:

> Paul, haven't you ever had routing fail?  Power and ground routing is just
> one example of where a congested part can experience routing troubles.
>
> Stephanie, I seem to racall graphs on P&R performance in marketing slides
> that suggest 80% is pretty solid while 90% utilization starts to get ugly...
> 93-95% is tough.  Was it indeed the placing that failed or was it the
> route?  If placement is indeed the problem, Paul's confusion with your
> result is understandable.  Routing is what historically got me.  One thing
> that isn't obvious to designers new to (highly utilized) Xilinx devices is
> that the mapper allocates slices;  if your design uses 93% of the LUTs or
> registers, it may use 120% of the slices because many registers don't pack
> nicely together due to unusual resets or clock enables or other
> signals/configurations that affect both registers of the slice.  The slice
> utilization is the important number.
>
> Paul Glover wrote:
>
> > Why did PAR fail? It will not fail based upon utilization, unless it is
> > greater than 100%. Did the timing constraints fail?
> >
> > Paul
> >
> > Stephanie McBader wrote:
> >
> > >Hi,
> > >
> > >I'm sorry if this issue's been brought up before, I've tried searching
> > >for similar queries but to no avail.
> > >
> > >I would like to know if there's a defined maximum device usage
> > >percentage which guarantees successful Place and Route phases,
> > >particularly for Virtex-E FPGAs. If so, what is it?
> > >
> > >I would have thought that - ideally - a device should be able to use
> > >100% of its resources, but we live in a world far from ideal, and PAR
> > >software is probably incapable of matching such idealistic usage!
> > >
> > >I use Foundation ISE 4.2 with the latest service pack, and have tried
> > >both XST and FPGA Express for synthesising a design that came up to 93%
> > >and 95% of a V600E, respectively. The Map process was successful, but
> > >Placing failed even if I set it to try with highest effort...
> > >
> > >Am I asking for too much? :)
> > >
> > >Thanks!
> > >
> > >Stephanie McBader
> > >Researcher/Design Engineer
> > >NeuriCam S.p.A
> > >


Article: 41168
Subject: Working modulo exponent routine?
From: "David Lamb" <david.lamb@videotron.ca>
Date: Thu, 21 Mar 2002 21:36:05 -0500
Links: << >>  << T >>  << A >>
Hi!
Does anyone know where I could find a working implementation of a fast
modulo exponent routine for an fpga (vhdl or schematic)  (x ^ Y mod Z) ? I
really don't have the knowledge to understand the theory behind this and
everything I can find on google is highly theoric.

Thanks a lot
David



Article: 41169
Subject: Clock termination affecting JTAG interface
From: Dean Armstrong <daa1@cs.waikato.ac.nz>
Date: Fri, 22 Mar 2002 17:03:13 +1200
Links: << >>  << T >>  << A >>
Hi All,

I have encountered a strange problem on a board we have designed. The 
board contains a Xilinx Spartan II XC2S200, two Xilinx XC95288XL CPLDs, 
and one Xilinx XC95144XL CPLD.

There are three power supply voltages on the board: 2.5V for the Spartan 
II core, 3.3V for the CPLDs and the Spartan II I/O, and 5V for some RAM 
and ROM.

There is a 19.6608MHz Crystal Oscillator Module running on the 5V rail, 
which provides a clock to the four Xilinx chips. This clock rings more 
than I would like, so I wish to terminate it using pads included in the 
design for this reason.

Using information from the manufacturer I have established that the 
impedance of the clock trace is around 90 Ohms, so I terminated it to 5V 
and to ground, each with 180 Ohm resistors.

When I do this, however, the JTAG test access port on the Spartan II 
appears to become unreliable - I am not able to configure the Spartan II 
via JTAG.

I am using the Xilinx Parallel Cable III running using the 5V supply on 
the board.

I use the IDCODE looping feature in the Xilinx iMPACT JTAG programmer 
software, and when the clock is terminated then this fails after a 
varying number of iterations (often between 200 and 8000).

As soon as I remove the clock termination, this IDCODE looping is 
successful.

One idea that was put to me was that the clock termination may be 
introducing noise into my 5V rail, which is affecting the Parallel Cable 
III. I tried decoupling this supply close to the Cable, and this had no 
effect. I also tried using an entirely seperate power supply for the 
Parallel Cable, and this also made no difference.

I tried terminating just to Ground (ie. removing the resistor from the 
clock net to 5V). This seemed to make things better, but did not fix the 
problem completely.

My 5V supply is actually ~4.72V. While this is within the +/-10% 
specified limits of all the chips that use it, it is outside the +/-5% 
specified limits of the crystal oscillator module. I cannot see how this 
could cause problems, because the JTAG interface has nothing to do with 
this clock.

Does anyone have any ideas about what may be causing this, or what I can 
try to establish the cause?

Kind regards,
Dean Armstrong
The University of Waikato
New Zealand


Article: 41170
Subject: Re: coregen under Solaris
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: Fri, 22 Mar 2002 06:04:45 GMT
Links: << >>  << T >>  << A >>
acher@in.tum.de (Georg Acher) writes:

> In article <87elid4pvp.fsf@filestore.home.gustad.com>,
>  Petter Gustad <newsmailcomp1@gustad.com> writes:
> |> 
> |> Whenever I launch coregen (4.1iSP3) under Solaris 8 I get the windows,
> |> but the contents is party empty. And the watch cursor is active
> |> indefinitely (at least for 24 hours).
> |> 
> |> If I move the windows over overlap it using a different window I get
> |> parts of the window redrawn, but I can't get it to update the window
> |> to make the application usable.
> |> 
> |> I'm using a X86 based PC running Linux as a X11 server against the SUN
> |> machine where I launch coregen. I have no problems running
> |> floorplanner this way. I would blame it on Java, but somebody might
> |> have a better explanation or even a solution?
> 
> This is a bug in the Solaris JDK, happens also with the crappy installer and all
> other Java-based tools (eg. xpower).
> 
> But if you already have Linux, why don't you run coregen straight on your own
> box? After all it is Java, write once, crash everywhere ;-)
> 
> I have modified the coregen startup script for that, for me it runs perfectly 
> with JDK1.3 for Linux:

I tried this once for the Solaris 8 Java distribution which was
installed on the SUN machine, but it did not seem to help. 

> http://wwwbode.cs.tum.edu/~acher/xilinx/

Thanks, I'll try that. 


Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 41171
Subject: Re: Interconnect system for multiple FPGA's ?
From: Muzaffer Kal <kal@dspia.com>
Date: Fri, 22 Mar 2002 06:15:08 GMT
Links: << >>  << T >>  << A >>
On Thu, 21 Mar 2002 23:46:12 +0000, Craig McAdam
<craig.mcadam@ntlworld.com> wrote:

>I'm implementing a board design that will include some FPGA prototyping
>capability in addition to other required functions. There will probably
>be multiple FPGA's, two or four perhaps, most likely Xilinx Virtex-E.
>Perhaps also some FPGA expansion capability either by populating more
>FPGA's or by a mezzanine card.
> 
>Anybody got any good pointers to implementing an interconnect bus
>between the FPGA's ? I guess there are two possibilities -
>
>1. Each FPGA contains a number of individual modules that are complete
>in themselves and communicate with each other within each FPGA and also
>with the other FPGA
>
>2. Resources are shared between FPGA's to allow larger designs to be
>implemented.
>
>Thanks,
>
>Regards, Craig

Check out Synplicity Certify
http://www.synplicity.com/products/certify.html. It is exactly for
partitioning a large design into multiple FPGAs. You can even get
Syplicity to optimize it for your board.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 41172
Subject: Re: Working modulo exponent routine?
From: Muzaffer Kal <kal@dspia.com>
Date: Fri, 22 Mar 2002 06:16:10 GMT
Links: << >>  << T >>  << A >>
On Thu, 21 Mar 2002 21:36:05 -0500, "David Lamb"
<david.lamb@videotron.ca> wrote:

>Hi!
>Does anyone know where I could find a working implementation of a fast
>modulo exponent routine for an fpga (vhdl or schematic)  (x ^ Y mod Z) ? I
>really don't have the knowledge to understand the theory behind this and
>everything I can find on google is highly theoric.
>
>Thanks a lot
>David
>

Would you be interested in licensing a core which does this ? I've
been working on this block for a while as an IP block but it is not
done yet.


Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 41173
Subject: SPI-4 interface IP core available(OIF Standard) with MAC Core
From: siva.koka@iwavesystems.net (siva koka)
Date: 21 Mar 2002 23:57:41 -0800
Links: << >>  << T >>  << A >>
Hi all,
We have developed SPI-4(From OIF)in Verilog on Xilinx virtex-II fpga
using.
This IP can be used for 10Gb Ethernet,ATM,and OC-192 applications.This
IP also contains a Ethernet MAC Core in order to use it for
EoS(Ethernet Over SONET) applications.
If any body is interested in getting the IP Core either as soft IP or
a hard core,feel free to contact us.
The contacting e-mail id is:
siva.koka@iwavesystems.net
Ph No: +91-80-6683700 extn121

Thanx and Regards
- Siva

Article: 41174
Subject: Re: High speed clock routing
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Fri, 22 Mar 2002 08:34:51 -0000
Links: << >>  << T >>  << A >>
>I understand that the die can get faster even with the slower spec'd
>parts.  But we would replace our earlier design with a new design to
>take advantage of the speed and would not be buying the slower speed
>part (at least that is the most likely senario).  

That doesn't make sense to me.

How long does it take you to crank out a new design?

What do you do if customers want your existing product now?

How long does it take you to even figure out that the problem
is that a chip got faster when you weren't looking so you know
that you need to do a redesign?



What sort of volumes are you working in?

Do you carefully monitor batch numbers and process changes?
Some large organizations do this.  It's a huge amount of
paperwork.  Some IC companys will tell you when they change
things that might be interesting - like do a die shrink where
they don't change the part number or data sheet.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.




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