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Messages from 41175

Article: 41175
Subject: another from newbie
From: "Jimmy Zhang" <zhengyu@attbi.com>
Date: Fri, 22 Mar 2002 08:39:55 GMT
Links: << >>  << T >>  << A >>
Hi,

  I would also like to know if anyone is aware of PCI FPGA card where the
reconfiguration of FPGA card can be done from the devices calls via PCI
interface.

Jimmy





Article: 41176
Subject: Re: more questions
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Fri, 22 Mar 2002 08:47:27 -0000
Links: << >>  << T >>  << A >>
>Unlikely, for any PCI implementation I would think.  You can get that
>in a burst, but I doubt you will achieve sustained transfers of that
>magnitude.  Anyone got any experience of real-world sustained
>transfer rates on PCI?

It depends...

Are you doing reads from device and writes to memory?  That
direction pipelines nicely.  You can get close to burst rate
if you use large blocks.

Writes to a device (reads from memory) are usually much
slower because of memory latency.  Half of the burst rate
is a good guess.

Servers are often slower than small PCs/workstations because
they have a more complicated (and hence slower) memory system.
But sometimes they are willing to do a lot of prefetching
so as long as you use big transfers, they get good bandwidth
reading from memory.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 41177
Subject: Re: which is the fastest FPGA ?
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Fri, 22 Mar 2002 08:51:08 -0000
Links: << >>  << T >>  << A >>
>                                          An option for high data
>rate is to use a demux such as the Atmel TS81102G0 to break a high
>data rate ADC output stream into several parallel interleaved
>streams at rates the FPGA can easily handle.  We did this recently
>for a 960 MS/S FFT design.

Wow!  Thanks for the info.

I haven't been looking at ADCs recently.  How fast do they go
now?  What sort of signaling do the fast ones use?

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 41178
Subject: Re: Clock termination affecting JTAG interface
From: Paul Burke <paul@scazon.com>
Date: Fri, 22 Mar 2002 08:58:39 +0000
Links: << >>  << T >>  << A >>
Dean Armstrong wrote:
> 

> Using information from the manufacturer I have established that the
> impedance of the clock trace is around 90 Ohms, so I terminated it to 5V
> and to ground, each with 180 Ohm resistors.
> 

Can your clock source and sink 28mA? Try isolating the termination with
a capacitor of negligible impedance at 20MHz, say 10nF. Or try a 91 ohm
resistor in series with the clock close to the oscillator.

Paul Burke

Article: 41179
Subject: Re: synplify, quartus II 2.0
From: "kudla" <kudla@fuw.edu.pl>
Date: Fri, 22 Mar 2002 10:02:53 +0100
Links: << >>  << T >>  << A >>
Of course Leonardo (Mentor) is not Synplify (Synplicity)... Sorry - I have
just installed Synplify waiting for
Leonardo problems fixing - so those two systems has been mixed up in my
writing...
I am starting LS-Altera directly.
I am targeting Apex 20K now.
From previous experience LS was not so bad in comparison to the FPGA Express
(our main tool to develop Acex 1k designs).
Maciek


Uzytkownik "Kevin Brace"
<ihatespam99kevinbraceusenet@ihatespam99hotmail.com> napisal w wiadomosci
news:a7darn$s1n$1@newsreader.mailgate.org...
> LeonardoSpectrum-Altera is not Synplify . . .
> LS-Altera is in general pretty buggy piece of software from my
> experience using it (2001_1a_028 and OEM2002a_Altera_NIGHTLY_14), so I
> am not surprised that you are having problems.
> Did you start LS-Altera directly or did you try to use QII's NativeLink?
> LS-Altera + QII's NativeLink is broken when you use FLEX10KE/ACEX1K
> because some idiot at Altera got a file name wrong of the NativeLink
> script.
> It took me two days to figure out what was going wrong.
> Which device are you targeting?
>
>
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)
>
>
>
> kudla wrote:
> >
> > My Synplify (Leonardo Spectrum OEM2002a_Altera_NIGHTLY_14) crashes soon
> > after start.
> > (License passes - that I can see before window disapears). I have w2k
sp2
> > and Quartus II 2.0.
> > Does somebody know what I can do?
> > Maciek



Article: 41180
Subject: Re: Clock termination affecting JTAG interface
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Fri, 22 Mar 2002 09:03:11 GMT
Links: << >>  << T >>  << A >>
> There is a 19.6608MHz Crystal Oscillator Module running on the 5V rail,
> which provides a clock to the four Xilinx chips. This clock rings more
> than I would like, so I wish to terminate it using pads included in the
> design for this reason.

One 'primitiv' suggestion: use a simple RC low pass in the clock line (e.g.
fg=60MHz).

I'm not shure, if this is a good way. Just have seen it on a board and the
clock looks
fine (after the LP).

Martin



Article: 41181
Subject: Re: XPOWER accuracy? Commendations
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Fri, 22 Mar 2002 09:05:46 -0000
Links: << >>  << T >>  << A >>
[snip lots of good info]
>4.
>As a conscientious designer, you must assume that the data sheet guarantees are
>valid. But you should also know that this particular leakage-current parameter is
>usually much lower than the guaranteed spec.

Is there any way to turn that "usually" into something solid
I can use for worst-case designing?  (or something helpful
like that)

Is sub-threshold leakage current linear with temperature
and supply voltage?

"typical" parameters are great for trying to understand
measurements in the lab.  But they don't help much when
you get back to your desk and try to verify that your
design will work in all the ugly corner cases.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 41182
Subject: Re: which is the fastest FPGA ?
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Fri, 22 Mar 2002 10:08:48 +0100
Links: << >>  << T >>  << A >>

> >                                          An option for high data
> >rate is to use a demux such as the Atmel TS81102G0 to break a high
> >data rate ADC output stream into several parallel interleaved
> >streams at rates the FPGA can easily handle.  We did this recently
> >for a 960 MS/S FFT design.
>
> Wow!  Thanks for the info.
>
> I haven't been looking at ADCs recently.  How fast do they go
> now?  What sort of signaling do the fast ones use?
>

A couple of giga samples per second

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.


> --
> These are my opinions, not necessarily my employer's.  I hate spam.
>



Article: 41183
Subject: Re: another from newbie
From: "Josh Pfrimmer" <yeah_spam_me@thisaddress.com>
Date: Fri, 22 Mar 2002 01:21:12 -0800
Links: << >>  << T >>  << A >>
alphadata sells some.. the ADM-XRCs..  Come with all sorts of Xilinx Virtex
and Virtex II chips.
www.alphadata.co.uk

The FPGA itself doesn't ever see the PCI interface, though.. there's a
bridge.  You write the bitfile to on-board memory and hit some
register-mapped signals in the bridge to trigger the reconfigure (from
on-board mem) of the FPGA.

I had pretty good experience with the guys at Alphadata, though....

JP

"Jimmy Zhang" <zhengyu@attbi.com> wrote in message
news:v5Cm8.88861$af7.53864@rwcrnsc53...
> Hi,
>
>   I would also like to know if anyone is aware of PCI FPGA card where the
> reconfiguration of FPGA card can be done from the devices calls via PCI
> interface.
>
> Jimmy
>
>
>
>



Article: 41184
Subject: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Fri, 22 Mar 2002 09:33:37 -0000
Links: << >>  << T >>  << A >>
[context is reducing cycle time because of clock jitter]

>Now if the probability that you get something out at the +peak,
> or -peak is one in tens of millions, then getting two in a row
> is that squared.
>
>I think that is called, extremely unlikely, or maybe not in your lifetime.

Thanks.  Much good info in your msg.

But I get very nervous when somebody is arguing probabilities
and there might be mechanisims that I don't understand biasing
things.

Your initial statement that triggered my reply was that we
only needed to reduce the cycle time by 1/2 the peak-peak
jitter.  That seems low to me.  (But I do agree that 2/2 may
be too high.)

Suppose we have nice gausian noise.  We wait a while and get a
very late clock.  If the jitter is really noise (thermal?) then
the next clock has a 50-50 chance of being early.  If it's early
enough then we have made a clock cycle that is under the "1/2"
you allowed for.

How about another simple case.  Suppose all the jitter is due to
DCM stepping.  Should I reduce my cycle time by a 1/2 step?
Whenever it steps in the wrong direction that clock cycle
will be short by a whole step.  (Or do your specs/testing
include that much extra slop in the guard band?)


This problem area feels like metastability.  It's a hard problem.
The solution is easy - just wait longer.  But we (often) don't like
that answer.

If you are going to make statistical arguments, then I think it's
important that the designer be able to do the calcualtions to
make sure they are good enough for his application.


Suppose I wanted to check the clock jitter on my board.  How
much gear do I need?  How much extra testing circuitry do I
need to add to a board?  Is a good test point and fancy scope
with DSP good enough?


Sorry if any of this seems nasty.  Thanks again for reminding
us about this (very) important consideration.

-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 41185
Subject: Re: coregen under Solaris
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 22 Mar 2002 11:27:06 +0100
Links: << >>  << T >>  << A >>
Petter Gustad <newsmailcomp1@gustad.com> writes:

> acher@in.tum.de (Georg Acher) writes:
> 
> > In article <87elid4pvp.fsf@filestore.home.gustad.com>,
> >  Petter Gustad <newsmailcomp1@gustad.com> writes:
> > |> 
> > |> Whenever I launch coregen (4.1iSP3) under Solaris 8 I get the windows,
> > |> but the contents is party empty. And the watch cursor is active
> > |> indefinitely (at least for 24 hours).
> > |> 
> > |> If I move the windows over overlap it using a different window I get
> > |> parts of the window redrawn, but I can't get it to update the window
> > |> to make the application usable.
> > |> 
> > |> I'm using a X86 based PC running Linux as a X11 server against the SUN
> > |> machine where I launch coregen. I have no problems running
> > |> floorplanner this way. I would blame it on Java, but somebody might
> > |> have a better explanation or even a solution?
> > 
> > This is a bug in the Solaris JDK, happens also with the crappy installer and all
> > other Java-based tools (eg. xpower).
> > 
> > But if you already have Linux, why don't you run coregen straight on your own
> > box? After all it is Java, write once, crash everywhere ;-)
> > 
> > I have modified the coregen startup script for that, for me it runs perfectly 
> > with JDK1.3 for Linux:
> 
> I tried this once for the Solaris 8 Java distribution which was
> installed on the SUN machine, but it did not seem to help. 
> 
> > http://wwwbode.cs.tum.edu/~acher/xilinx/
> 
> Thanks, I'll try that. 

It almost worked. It appears that all dialog boxes have the bottom ok,
cancel, etc. buttons missing... You said it, crash everywhere...

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 41186
Subject: Re: another from newbie
From: "Ken Mac" <aeu96186@yahoo.co.uk>
Date: Fri, 22 Mar 2002 10:29:00 -0000
Links: << >>  << T >>  << A >>

I am not too clear on exactly what you want but the cards from
www.nallatech.com use a Xilinx FPGA to interface with the PCI bus and then
feed the bitstream to another on-board FPGA.

Cheers,

Ken


"Jimmy Zhang" <zhengyu@attbi.com> wrote in message
news:v5Cm8.88861$af7.53864@rwcrnsc53...
> Hi,
>
>   I would also like to know if anyone is aware of PCI FPGA card where the
> reconfiguration of FPGA card can be done from the devices calls via PCI
> interface.
>
> Jimmy
>
>
>
>



Article: 41187
Subject: Altera Stratix compared to Xilinx Virtex
From: "Peter Lang" <Peter.Lang@rmvmachinevision.de>
Date: Fri, 22 Mar 2002 11:34:46 +0100
Links: << >>  << T >>  << A >>
Hi,
I am about to specify a new System doing some image processing.
I used for this kind of work Xilinx FPGAs for about 8 years.
Now I had a look at the new Altera Stratix FPGAs and
they sound really great.
I think especially the included really large RAM Blocks and
DSP cores are really useful for image processing.
So is it true that Altera is nowadays the better choice?
Anybody using already the Stratix devices?
Any Comments?

thanks peter



Article: 41188
Subject: Re: Altera Stratix compared to Xilinx Virtex
From: Ray Andraka <ray@andraka.com>
Date: Fri, 22 Mar 2002 12:55:11 GMT
Links: << >>  << T >>  << A >>
Not yet, so far they are only available on marketing slides.

Peter Lang wrote:

>
> Anybody using already the Stratix devices?
> Any Comments?
>
> thanks peter


Article: 41189
Subject: Re: which is the fastest FPGA ?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 22 Mar 2002 13:00:18 GMT
Links: << >>  << T >>  << A >>
several that sample at well over 1GS/sec.  These seem to be mostly LVDS
interfaces, mostly 8 bit.

Hal Murray wrote:

> >                                          An option for high data
> >rate is to use a demux such as the Atmel TS81102G0 to break a high
> >data rate ADC output stream into several parallel interleaved
> >streams at rates the FPGA can easily handle.  We did this recently
> >for a 960 MS/S FFT design.
>
> Wow!  Thanks for the info.
>
> I haven't been looking at ADCs recently.  How fast do they go
> now?  What sort of signaling do the fast ones use?
>
> --
> These are my opinions, not necessarily my employer's.  I hate spam.


Article: 41190
Subject: SystemC compiler
From: "Jacke" <magz@citiz.net>
Date: Fri, 22 Mar 2002 13:10:13 -0000
Links: << >>  << T >>  << A >>
Hi, there
Are there anyone know where I can find a free systemC compiler?
or just convert systemC to verilog , VHDL is also acceptable.

Thanks.



Article: 41191
Subject: Re: coregen under Solaris
From: acher@in.tum.de (Georg Acher)
Date: 22 Mar 2002 13:17:00 GMT
Links: << >>  << T >>  << A >>
In article <m3vgbo6gp1.fsf@scimul.dolphinics.no>,
 Petter Gustad <newsmailcomp1@gustad.com> writes:
<coregen troubles>
|> It almost worked. It appears that all dialog boxes have the bottom ok,
|> cancel, etc. buttons missing... You said it, crash everywhere...

This can be a font problem in the Swing libraries... What JDK/JRE-version are you
running? I have no problems with java version "1.3.0" on a Suse7.2-system.  

-- 
         Georg Acher, acher@in.tum.de         
         http://www.in.tum.de/~acher/
          "Oh no, not again !" The bowl of petunias          

Article: 41192
Subject: Re: which is the fastest FPGA ?
From: Johann Glaser <Johann.Glaser@gmx.at>
Date: Fri, 22 Mar 2002 14:39:02 +0100
Links: << >>  << T >>  << A >>
Hi!

> I haven't been looking at ADCs recently.  How fast do they go now?  What
> sort of signaling do the fast ones use?

Look at the Maxim MAX104 (1GSps) or MAX108 (1.5GSps) at
http://www.maxim-ic.com/. Quite impressive devices. The datasheet at
http://pdfserv.maxim-ic.com/arpdf/MAX108.pdf shows how the digital
outputs are connected. (192 pin BGA package!)

But others surely have comparable fast ADCs. Agilent, AD, ...

Bye
  Hansi

Article: 41193
Subject: Re: Interconnect system for multiple FPGA's ?
From: Christopher.Saunter@durham.ac.uk (Christopher Saunter)
Date: Fri, 22 Mar 2002 14:26:51 +0000 (UTC)
Links: << >>  << T >>  << A >>
Craig McAdam (craig.mcadam@ntlworld.com) wrote:

: Anybody got any good pointers to implementing an interconnect bus
: between the FPGA's ? I guess there are two possibilities -

: 1. Each FPGA contains a number of individual modules that are complete
: in themselves and communicate with each other within each FPGA and also
: with the other FPGA

If you are following this approach and manually partitioning different
blocks into different chips, Xilinx appnote 234 (SelectLink comms) may be
of interest for Virtex / E series chips - I'm looking at it at the moment,
and it uses various virtex resources to provide a 'virtual fifo' between
two devices - data writen into the fifo on chip 1 appears in the fifo on
chip 2.  The core generator takes care of all signalling etc, leaving you
to design a suitable PCB.

This should suit what I am doing very well, as it processes data in
chunks, passing chunks between different blocks in a unidirectional flow.
I guess these 'SelectLink' channels are less suitable for designs such as
processors where data is flying all over the place, with a very low
latency requirement.

Cheers,
	Chris Saunter
(who is wondering why so many Xilinx components are prefaced with
'Select'...)

Article: 41194
Subject: Re: High speed clock routing
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 22 Mar 2002 09:58:27 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> >I understand that the die can get faster even with the slower spec'd
> >parts.  But we would replace our earlier design with a new design to
> >take advantage of the speed and would not be buying the slower speed
> >part (at least that is the most likely senario).
> 
> That doesn't make sense to me.
> 
> How long does it take you to crank out a new design?
> 
> What do you do if customers want your existing product now?
> 
> How long does it take you to even figure out that the problem
> is that a chip got faster when you weren't looking so you know
> that you need to do a redesign?

You make it sound like you are working in a vacuum.  Typically you find
out that they are cranking out a faster version some 4 to 6 months
before it is available.  Before all of the old, slower die are gone from
the supply chain, you can order the faster speed grade of the chip at
least as a sample and often as a production device.  

So it will be no mystery that they are producing a faster part and we
can make whatever changes are needed to accomodate it.  


> What sort of volumes are you working in?
> 
> Do you carefully monitor batch numbers and process changes?
> Some large organizations do this.  It's a huge amount of
> paperwork.  Some IC companys will tell you when they change
> things that might be interesting - like do a die shrink where
> they don't change the part number or data sheet.

A die shrink is normally done to save money or production costs or to
get a new speed grade out.  Certainly we will know in advance if they
are producing a new speed grade.  In the DSP market, it will be very
seldom that they are producing faster parts and they won't want to
provide a new speed grade.  It is almost like the PC world where they
will have clock speeds 10% apart.  In the DSP world they will provide
clock speeds as close as 20% apart.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 41195
Subject: Re: Altera Stratix compared to Xilinx Virtex
From: mikeandmax@aol.com (Mikeandmax)
Date: 22 Mar 2002 15:17:27 GMT
Links: << >>  << T >>  << A >>
Ray pointed out-
>Not yet, so far they are only available on marketing slides.
>
>Peter Lang wrote:
>
>>
>> Anybody using already the Stratix devices?
>> Any Comments?

but Ray, they are really high performance slides!

Mike Thomas

Article: 41196
Subject: JTAG under Linux
From: =?iso-8859-1?Q?St=E9phane?= Guyetant <sguyetanREMOVE@irisa.fr>
Date: Fri, 22 Mar 2002 16:23:36 +0100
Links: << >>  << T >>  << A >>
Hi,

I've got a Xilinx JTAG cable (on serial port) and I'd like to debug with
chipscope-like features under Linux.
Any link on available linux/unix software would be very helpful,
even if I have to buy another JTAG cable.

Thanks,
Stephane


Article: 41197
Subject: Re: simple Free FPGA tool
From: sunny <sunny@sunrise.at>
Date: Fri, 22 Mar 2002 07:35:30 -0800
Links: << >>  << T >>  << A >>
Hi Kevin,

is there any specific reason why you do use a free and limited version of Xilinx synthesis and P&R tools and the Modelsim simulator. I assume the reason is that you are not in the positon to spend some money on full versions and well sophisticated software like Synplify or Leonardo and a full (and fast) versions of MTI or NC-Sim. What is the reason why you are not in the position to afford that kind of tools? Could it be that you have a big mouth but not the brains to be succsessfull enough to spend some money on the right tools?

I donīt know what your problem is. Thousands of users do take advantage of Altera free tool offerings. Why dont you just shut up and get lost. Your comments really suck. Iīve never read a comment or posting from you which was of any help to any user.

sunny

Article: 41198
Subject: Ligthning strikes & EMI - SPARTAN II design in flight
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 22 Mar 2002 10:37:28 -0500
Links: << >>  << T >>  << A >>
Hello,

I am designing a Spartan II board. It will be installed in an aircraft. The
customer wants special care taken in the design for lightning & EMI.

Where can I get info on proper design guidelines ?

Sincerely
Dan



Article: 41199
Subject: Poor availability problems on Coolrunner
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 22 Mar 2002 10:40:56 -0500
Links: << >>  << T >>  << A >>
I was planning on using a Coolrunner part, the XCR3256XL in the FT256
package on a new design that we want to prototype the end of April.  I
kept trying to get P&A (price and availability) from my disti and was
not getting an answer for weeks, it was always left off of the message
that had the P&A of the other parts.  I finally got an answer Wednesday
and they are telling me they aren't making parts until MAY/JUNE with a 6
week lead time.  I expected this meant I needed to order them 6 weeks
ahead.  Now they are telling me that I won't be able to get them until 6
weeks AFTER May/June.  

Obviouly I need to find a different part.  

The coolrunner was pretty much perfect for the job.  It had 256
Macrocells and 164 IOs along with 20 mA power consumption that dropped
to nearly zero when it was not needed.  Of course, it ran from 3.3volts
and was fully 5 volt tolerant.  Finally it supported JTAG boundary
scan.  

Is there any chance of finding a part like this elsewhere?  How about if
I drop the zero power?  I can live with a bit higher power consumption,
but all of the parts I have found use 100 mA or more when idling!  That
is more than the MCU!


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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